CN102013410A - Inductance element and forming method thereof - Google Patents
Inductance element and forming method thereof Download PDFInfo
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- CN102013410A CN102013410A CN2009101956191A CN200910195619A CN102013410A CN 102013410 A CN102013410 A CN 102013410A CN 2009101956191 A CN2009101956191 A CN 2009101956191A CN 200910195619 A CN200910195619 A CN 200910195619A CN 102013410 A CN102013410 A CN 102013410A
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Abstract
The invention relates to an inductance element and a forming method thereof. The inductance element comprises a substrate, a first metal wire array, a dielectric layer, a first plug, a second plug and a second metal wire array, wherein the first metal wire array is formed on the surface of the substrate; the dielectric layer is formed on the surface of the substrate and covers on the first metal wire array; the first plug is formed in the dielectric layer and is connected with an initial end of metal wires of the first metal wire array; the second plug is formed in the dielectric layer and is connected with a final end of the metal wires of the first metal wire array; the second metal wire array is formed on the surface of the medium layer; the kth metal wire in the second metal wire array is conducted with the first plug connected with the initial end of the hth metal wire and the second plug connected with the final end of the (h+1)th metal wire in the first metal wire array; the (k+1)th metal wire in the second metal wire array is conducted with the first plug connected with the first plug connected with the initial end of the (h+1)th metal wire and the second plug connected with the final end of the (h+2)th metal wire in the first metal wire array; and k and h are natural numbers. The invention reduces the surface area of the inductance element on the substrate.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly inductance element and forming method thereof.
Background technology
Semiconductor integrated circuit is to adopt semiconductor fabrication process to form.For example, making elements such as many transistors and resistance, electric capacity, inductance on the monocrystalline silicon piece, and elements combination is being become complete electronic circuit according to the method for multilayer wiring or tunnel wiring.Semiconductor integrated circuit extensively applies in the various electronic products, for example: mobile phone, computer, personal gaming device, guider etc.
The main effect of inductance element be to AC signal isolate, filtering or form resonant circuits with capacitor, resistor etc.Because inductance element plays an important role, therefore the semi-conductor electricity sensing unit is used also relatively extensively in chip.
In the prior art, the formation technology of inductance element generally includes: the semiconductor-based end is provided, and the described semiconductor-based end, comprise insulating medium layer; On described insulating medium layer, form certain thickness metal level; Patterned metal layer forms wire coil, and described wire coil shape in the shape of a spiral distributes.In being 94113747.3 Chinese patent file, the patent No. can also find the relevant technical scheme information of the formation technology of more relevant inductance elements.
But the inductance element that prior art forms need form 3 microns metal levels to 4 micron thickness on the semiconductor-based end, described metal level is carried out patterning, forms inductance element.Prior art not only needs extra inductance element to form technology, and described inductance element also needs to take the surface area of substrate.
Summary of the invention
The technical problem that the present invention solves is to reduce the surface area that inductance element takies substrate.
For addressing the above problem, the invention provides a kind of formation method of inductance element: provide substrate; Form first array of metal lines at described substrate surface, described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect; Form the dielectric layer that covers described first array of metal lines at described substrate surface; The described dielectric layer of etching, the metal wire that forms the contact hole of the metal wire initiating terminal expose described first array of metal lines and described first array of metal lines finishes the contact hole of end; Fill described contact hole with conductive materials, form first connector of the metal wire initiating terminal that connects first array of metal lines and second connector of the metal wire end end that is connected described first array of metal lines; Form second array of metal lines on described dielectric layer surface, described second array of metal lines comprises the m metal line and the m metal line is non-intersect, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines; Wherein m, k and h are natural number, and m is the natural number greater than 2, and k is less than m, and h is less than n.
The present invention also provides a kind of inductance element, comprising: substrate; Be formed on first array of metal lines of described substrate surface; Be formed on substrate surface and cover the dielectric layer of described first array of metal lines; Be formed in the dielectric layer and connect described first array of metal lines the metal wire initiating terminal first connector and is connected second connector that the metal wire end of described first array of metal lines is held; Be formed on second array of metal lines on dielectric layer surface, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines.
Compared with prior art, the present invention has the following advantages: inductance element provided by the invention and forming method thereof, can combine with the semiconductor fabrication process of standard, do not need extra inductance element to form technology, and the surface area of the substrate that the inductance element that forms takies is little, the magnetic field that the inductance element that forms produces is parallel to substrate, avoids producing the reciprocal magnetic field of inducting of substrate, improves the Q value of inductance element.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is the schematic flow sheet of an embodiment of the formation method of inductance element of the present invention;
Fig. 2 to Fig. 8 is the process schematic diagram of an embodiment of the formation method of inductance element of the present invention.
Embodiment
By background technology as can be known, the formation method of existing inductance element is generally: the semiconductor-based end is provided, and the described semiconductor-based end, comprise insulating medium layer; On described insulating medium layer, form metal level; Patterned metal layer forms wire coil, and described wire coil shape in the shape of a spiral distributes.
The inductance element that prior art forms wants extra inductance element to form technology, and for example metal level forms technology; Etching sheet metal forms the mask of wire coil technology and extra formation wire coil etc.And the inductance that forms need take the surface area of substrate.
For this reason, the present inventor provides a kind of formation method of inductance element: provide substrate through a large amount of creative works; Form first array of metal lines at described substrate surface, described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect; Form the dielectric layer that covers described first array of metal lines at described substrate surface; The described dielectric layer of etching forms the contact hole of the metal wire initiating terminal that exposes described first array of metal lines and the contact hole of the metal wire end end that exposes described first array of metal lines; Fill described contact hole with conductive materials, form first connector of the metal wire initiating terminal that connects first array of metal lines and second connector of the metal wire end end that is connected described first array of metal lines; Form second array of metal lines on described dielectric layer surface, described second array of metal lines comprises the m metal line and the m metal line is non-intersect, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines; Wherein m, k and h are natural number, and m is the natural number greater than 2, and k is less than m, and h is less than n.
Preferably, the step that forms described first array of metal lines comprises: form the first metal layer on described dielectric layer surface; At described the first metal layer surface spin coating photoresist, then by exposure with on the mask with the corresponding figure transfer of first array of metal lines to photoresist, utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist figure; With described photoresist figure is mask, and the described the first metal layer of etching forms first array of metal lines.
Preferably, described metal wire is straight line, broken line or curve.
Preferably, the formation method of described dielectric layer is a chemical vapor deposition method.
Preferably, the technology of the described dielectric layer of described etching is plasma etch process.
Preferably, the step that forms described second array of metal lines comprises: form metal level on described dielectric layer surface; Form the photoresist figure corresponding at described layer on surface of metal with second array of metal lines; With described photoresist figure is mask, and the described metal level of etching forms second array of metal lines.
Preferably, the described first array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Preferably, the described second array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Preferably, described dielectric layer is single coating or multiple-level stack structure.
Preferably, described first connector and/or second connector are that the contact hole that is positioned at the different stack layers of dielectric layer is electrically connected to form.
The invention provides a kind of inductance element, comprising: substrate; Be formed on first array of metal lines of described substrate surface; Be formed on substrate surface and cover the dielectric layer of described first array of metal lines; Be formed in the dielectric layer and connect described first array of metal lines the metal wire initiating terminal first connector and is connected second connector that the metal wire end of described first array of metal lines is held; Be formed on second array of metal lines on dielectric layer surface, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines.
Preferably, described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect.
Preferably, described second array of metal lines comprises the m metal line, and m is the natural number greater than 2, and the m metal line is non-intersect.
Preferably, the described first array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Preferably, the described second array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Preferably, described dielectric layer is single coating or multiple-level stack structure.
Because the present invention is for the research of problems of the prior art, and performing creative labour has all been paid in the research of this invention.Inductance element provided by the invention and forming method thereof, can combine with the semiconductor fabrication process of standard, do not need extra inductance element to form technology, and the surface area of the substrate that the inductance element that forms takies is little, the magnetic field that the inductance element that forms produces is parallel to substrate, avoid producing the reciprocal magnetic field of inducting of substrate, improve the Q value of inductance element.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 is the schematic flow sheet of an embodiment of the formation method of inductance element of the present invention, Fig. 2 to Fig. 8 is the process schematic diagram of an embodiment of the formation method of inductance element of the present invention, below with reference to Fig. 1 to Fig. 8 the formation method of inductance element of the present invention is described, comprises step:
Step S101 provides substrate.
With reference to figure 2, concrete, described substrate 100 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate, epitaxial silicon substrate, section processes or the substrate that is not patterned.Though in these several examples of having described the material that can form the semiconductor-based end 100, any material that can be used as the semiconductor-based end all falls into the spirit and scope of the present invention.
In a kind of preferred implementation, described substrate 100 also comprises functional layer (not shown) and covers the dielectric layer 100a of described functional layer, a part that comprises integrated circuit and other elements in the described functional layer, described other elements can here not exemplify one by one for transistor, electric capacity, resistance or plain conductor.
Step S102 forms first array of metal lines at described substrate surface, and described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect;
With reference to figure 3, form the first metal layer 110 on described dielectric layer 100a surface.
Described the first metal layer 110 materials are aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps are the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.Described metal level 110 thickness are 200 dust to 3000 dusts.
With reference to figure 4, the described the first metal layer 110 of etching forms first array of metal lines 120.
Concrete steps comprise: at described the first metal layer 110 surperficial spin coating photoresists, then by exposure with on the mask with first array of metal lines, 120 corresponding figure transfer to photoresist, utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist figure.
With described photoresist figure is mask, and the described the first metal layer 110 of etching forms first array of metal lines 120.
It needs to be noted, in a kind of preferred implementation, described first array of metal lines 120 can and the semiconductor standard processes cambium layer between metal level be positioned at same one deck, specifically comprise, the mask that employing is formed with first array of metal lines 120 and interlayer metal layer forms the photoresist figure, with the photoresist figure is mask, etching forms first array of metal lines 120 and interlayer metal layer, the mask of first array of metal lines 120 that first array of metal lines 120 that forms with this preferred implementation is can savings outer and the formation technology of first array of metal lines 120.
First array of metal lines 120 that forms with above-mentioned method comprises the n metal line, for example metal wire 120a, 120b, 120c ..., for example can comprise 3,4,5 ....N is the natural number greater than 2, and the n metal line is non-intersect, above-mentioned can be by using the mask prepare described first array of metal lines 120 in advance, select for use semiconductive thin film deposition, graphical and etching technics to realize, here do not do and give unnecessary details.
The concrete numerical value of described n can be it needs to be noted that form technology in order to simplify described inductance element, described metal wire can be straight line or broken line, the curve that certain angle is arranged by the parameter decision of required inductance element here.
In the present embodiment, the broken line with 90 degree is that example is done exemplary illustrated.
Step S103 forms the dielectric layer that covers described first array of metal lines at described substrate surface.
With reference to figure 5, form the dielectric layer 130 that covers described first array of metal lines 120 on described dielectric layer 100a surface.
The thickness of described dielectric layer 130 is 20 nanometer to 5000 nanometers, described dielectric layer 130 is used for lead on the substrate and the isolation between the lead, concrete described dielectric layer 130 can be before-metal medium layer (Pre-Metal Dielectric, PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD), it needs to be noted that described dielectric layer can also be that single coating also can be the multiple-level stack structure.
Before-metal medium layer is to be deposited on the substrate with MOS device, utilize depositing operation to form, can form groove at subsequent technique in before-metal medium layer, form connecting hole with metal filled groove, described connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can form groove in the interlayer dielectric layer in subsequent technique, forms connecting hole with metal filled groove, and described connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of described dielectric layer 130 is selected from SiO usually
2The perhaps SiO of Can Zaing
2USG (Undoped Silicon Glass for example, the silex glass that does not have doping), BPSG (BorophosphosilicateGlass, the silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Described dielectric layer 130 generally selects for use the dielectric material of low-k, the material of described dielectric layer 130 specifically to be selected from the carborundum (BLOK) that silica (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of described dielectric layer 130 can be any conventional vacuum coating technology, for example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are not here done and are given unnecessary details.
Step S104, the described dielectric layer of etching forms the contact hole of the metal wire initiating terminal that exposes described first array of metal lines and the contact hole of the metal wire end end that exposes described first array of metal lines.
With reference to figure 6, the described dielectric layer 130 of etching forms the contact hole 121 of the metal wire initiating terminal that exposes described first array of metal lines 120 and the contact hole 122 of the metal wire end end that exposes described first array of metal lines 120.
Described dielectric layer 130 technologies of described etching can be any conventional etching technics, for example chemical etching or plasma etch process.In the present embodiment, the using plasma etching technics adopts CF
4, CHF
3, CH
2F
2, CH
3F, C
4F
8Perhaps C
5F
8In one or several as reacting gas etching dielectric layer 130.
Concrete processing step comprises: form the photoresist figure corresponding with contact hole 121 and contact hole 122 on described dielectric layer 130 surfaces; For described photoresist figure is a mask, the described dielectric layer 130 of etching forms contact hole 121 and contact hole 122; Remove described photoresist figure.
The concrete parameter of described etching technics is: concrete etching technics parameter can for: select the plasma-type etching apparatus for use, the etching apparatus chamber pressure is 10 millitorr to 50 millitorrs, the top radio-frequency power is 200 watts to 500 watts, and the bottom radio-frequency power is 150 watts to 300 watts, C
4F
8Flow is that per minute 10 standard cubic centimeters (10SCCM) are to per minute 50 standard cubic centimeters, the CO flow is that per minute 100 standard cubic centimeters are to per minute 200 standard cubic centimeters, the Ar flow is that per minute 300 standard cubic centimeters are to per minute 600 standard cubic centimeters, O
2Flow be per minute 10 standard cubic centimeters to per minute 50 standard cubic centimeters, etching dielectric layer 130 exposes the contact hole 121 of metal wire initiating terminal of described first array of metal lines 120 and the contact hole 122 that the metal wire that exposes described first array of metal lines 120 finishes end until formation.
Step S105 fills described contact hole with conductive materials, forms first connector 121a of the metal wire initiating terminal that connects first array of metal lines and the second connector 122a of the metal wire end end that is connected described first array of metal lines.
With reference to figure 7, described conductive materials can be aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Described step of filling described contact hole with conductive materials can be positioned at dielectric layer 130 surface and fill the metal level of described contact hole 121 and described contact hole 122 for formation, adopts to remove technology and remove part metals layer and part dielectric layer until forming the first connector 121a and the second connector 122a.
The formation technology of described metal level can be physical gas-phase deposition, described removal technology can be CMP (Chemical Mechanical Polishing) process, here it needs to be noted, diffuse to dielectric layer 130 for fear of conductive materials, before with conductive materials filling contact hole 121 and contact hole 122, can also form the barrier layer at the sidewall of described contact hole 121 and 122.
In other embodiment, for example dielectric layer is the multiple-level stack structure, and the described first connector 121a and/or the second connector 122a can be that the contact hole that is positioned at the different stack layers of dielectric layer is electrically connected to form.
With reference to figure 8, as described in step S106, form second array of metal lines 140 on described dielectric layer 130 surfaces, described second array of metal lines 140 comprises the m metal line and the m metal line is non-intersect, and the first connector 121a of h metal line initiating terminal and h+1 metal line finish the second connector 122a of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; Wherein m, k and h are natural number, and m is the natural number greater than 2, and k is less than m, and h is less than n.
Described formation second array of metal lines 140 steps comprise: form metal level on described dielectric layer 130 surfaces; Form the photoresist figure corresponding at described layer on surface of metal with second array of metal lines 140; With described photoresist figure is mask, and the described metal level of etching forms second array of metal lines 140.
Described second array of metal lines, 140 materials are aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps are the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
Second array of metal lines 140 that forms with above-mentioned method comprises the m metal line, for example metal wire 140a, 140b ..., for example can comprise 3,4,5 ....M is the natural number greater than 2, and the m metal line is non-intersect, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines; Above-mentioned can be by using the mask prepare described second array of metal lines 140 in advance, select for use semiconductive thin film deposition, graphical and etching technics to realize, here do not do and give unnecessary details.
Inductance element by above-mentioned technology forms comprises: substrate 100; Be formed on first array of metal lines 120 on described substrate 100 surfaces; Be formed on substrate 100 surface and cover the dielectric layer 130 of described first array of metal lines 120; Be formed in the dielectric layer 130 and connect described first array of metal lines 120 the metal wire initiating terminal the first connector 121a and is connected the second connector 122a that the metal wire end of described first array of metal lines is held; Be formed on second array of metal lines 140 on dielectric layer 130 surfaces, and the first connector 121a of h metal line initiating terminal and h+1 metal line finish described first connector 121a of h+1 metal line initiating terminal in first array of metal lines 120 and the second connector 122a that the h+2 metal line finishes end of being connected of k+1 metal line conducting in described second array of metal lines 140 of the second connector 122a of end in described connection first array of metal lines 120 of the k metal line conducting in described second array of metal lines 140.
Inductance element provided by the invention and forming method thereof, can combine with the semiconductor fabrication process of standard, do not need extra inductance element to form technology, and the surface area of the substrate that the inductance element that forms takies is little, the magnetic field that the inductance element that forms produces is parallel to substrate, avoid in the reciprocal magnetic field of inducting of other elements of substrate, improve the Q value of inductance element.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (16)
1. the formation method of an inductance element is characterized in that, comprises the steps:
Substrate is provided;
Form first array of metal lines at described substrate surface, described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect;
Form the dielectric layer that covers described first array of metal lines at described substrate surface;
The described dielectric layer of etching forms the contact hole of the metal wire initiating terminal that exposes described first array of metal lines and the contact hole of the metal wire end end that exposes described first array of metal lines;
Fill described contact hole with conductive materials, form first connector of the metal wire initiating terminal that connects first array of metal lines and second connector of the metal wire end end that is connected described first array of metal lines;
Form second array of metal lines on described dielectric layer surface, described second array of metal lines comprises the m metal line and the m metal line is non-intersect, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines; Wherein m, k and h are natural number, and m is the natural number greater than 2, and k is less than m, and h is less than n.
2. the formation method of inductance element as claimed in claim 1 is characterized in that, the step that forms described first array of metal lines comprises: form the first metal layer on described dielectric layer surface; At described the first metal layer surface spin coating photoresist, then by exposure with on the mask with the corresponding figure transfer of first array of metal lines to photoresist, utilize developer solution that the photoresist of corresponding site is removed then, to form the photoresist figure; With described photoresist figure is mask, and the described the first metal layer of etching forms first array of metal lines.
3. the formation method of inductance element as claimed in claim 1 is characterized in that, described metal wire is straight line, broken line or curve.
4. the formation method of inductance element as claimed in claim 1 is characterized in that, the formation method of described dielectric layer is a chemical vapor deposition method.
5. the formation method of inductance element as claimed in claim 1 is characterized in that, the technology of the described dielectric layer of described etching is plasma etch process.
6. the formation method of inductance element as claimed in claim 1 is characterized in that, the step that forms described second array of metal lines comprises: form metal level on described dielectric layer surface; Form the photoresist figure corresponding at described layer on surface of metal with second array of metal lines; With described photoresist figure is mask, and the described metal level of etching forms second array of metal lines.
7. the formation method of inductance element as claimed in claim 1, it is characterized in that, the described first array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
8. the formation method of inductance element as claimed in claim 1, it is characterized in that, the described second array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
9. the formation method of inductance element as claimed in claim 1 is characterized in that, described dielectric layer is single coating or multiple-level stack structure.
10. the formation method of inductance element as claimed in claim 1 is characterized in that, described first connector and/or second connector are that the contact hole that is positioned at the different stack layers of dielectric layer is electrically connected to form.
11. an inductance element is characterized in that, comprising:
Substrate;
Be formed on first array of metal lines of described substrate surface;
Be formed on substrate surface and cover the dielectric layer of described first array of metal lines;
Be formed in the dielectric layer and connect described first array of metal lines the metal wire initiating terminal first connector and is connected second connector that the metal wire end of described first array of metal lines is held;
Be formed on second array of metal lines on dielectric layer surface, and first connector of h metal line initiating terminal and h+1 metal line finish second connector of end in described connection first array of metal lines of the k metal line conducting in described second array of metal lines; First connector of h+1 metal line initiating terminal and h+2 metal line finish second connector of end in described connection first array of metal lines of k+1 metal line conducting in described second array of metal lines; K and h are natural number.
12. inductance element as claimed in claim 11 is characterized in that, described first array of metal lines comprises the n metal line, and n is the natural number greater than 2, and the n metal line is non-intersect.
13. inductance element as claimed in claim 11 is characterized in that, described second array of metal lines comprises the m metal line, and m is the natural number greater than 2, and the m metal line is non-intersect.
14. inductance element as claimed in claim 11, it is characterized in that, the described first array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
15. inductance element as claimed in claim 11, it is characterized in that, the described second array of metal lines material is aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper, perhaps is the alloy of aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum or copper.
16. inductance element as claimed in claim 11 is characterized in that, described dielectric layer is single coating or multiple-level stack structure.
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| CN2009101956191A CN102013410A (en) | 2009-09-07 | 2009-09-07 | Inductance element and forming method thereof |
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| CN2009101956191A CN102013410A (en) | 2009-09-07 | 2009-09-07 | Inductance element and forming method thereof |
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| CN2009101956191A Pending CN102013410A (en) | 2009-09-07 | 2009-09-07 | Inductance element and forming method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800648B (en) * | 2012-08-29 | 2017-03-08 | 上海华虹宏力半导体制造有限公司 | Semiconductor inductor structure and semiconductor circuit arrangement |
| CN106571358A (en) * | 2016-11-16 | 2017-04-19 | 华南师范大学 | Visible light communication emitting device adopting micro-inductor patterned substrate |
| CN107369653A (en) * | 2016-05-13 | 2017-11-21 | 北京中电网信息技术有限公司 | A kind of system-in-a-package method of high interference component, structure and separation array structure |
| CN116052981A (en) * | 2023-03-31 | 2023-05-02 | 北京航天微电科技有限公司 | Magnetic film inductor and preparation method thereof |
-
2009
- 2009-09-07 CN CN2009101956191A patent/CN102013410A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800648B (en) * | 2012-08-29 | 2017-03-08 | 上海华虹宏力半导体制造有限公司 | Semiconductor inductor structure and semiconductor circuit arrangement |
| CN107369653A (en) * | 2016-05-13 | 2017-11-21 | 北京中电网信息技术有限公司 | A kind of system-in-a-package method of high interference component, structure and separation array structure |
| CN106571358A (en) * | 2016-11-16 | 2017-04-19 | 华南师范大学 | Visible light communication emitting device adopting micro-inductor patterned substrate |
| CN106571358B (en) * | 2016-11-16 | 2019-03-15 | 华南师范大学 | Using the visible light communication ballistic device of micro- inductive graph substrate |
| CN116052981A (en) * | 2023-03-31 | 2023-05-02 | 北京航天微电科技有限公司 | Magnetic film inductor and preparation method thereof |
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Application publication date: 20110413 |