CN100536107C - Single inlay structure and dual inlay structure and their open hole forming method - Google Patents
Single inlay structure and dual inlay structure and their open hole forming method Download PDFInfo
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- CN100536107C CN100536107C CNB2006101030955A CN200610103095A CN100536107C CN 100536107 C CN100536107 C CN 100536107C CN B2006101030955 A CNB2006101030955 A CN B2006101030955A CN 200610103095 A CN200610103095 A CN 200610103095A CN 100536107 C CN100536107 C CN 100536107C
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Abstract
The invention relates to a method for forming a single embedded open. The method includes that a basement is firstly provided with a formed conducting wire in the basement; secondly, a barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom anti-reflective layer and a patterned photoresist layer are formed sequentially on the basement; thirdly, the bottom anti-reflective layer, the silicon oxynitride layer and the metal hard mask layer, which are uncovered by the patterned photoresist layer, are directly removed until the part surface of the dielectric layer is exposed; later, the patterned photoresist layer and the bottom anti-reflective layer are removed; next, with the silicon oxynitride layer and the metal hard mask acting as the mask, the part of the dielectric layer and the part of the barrier layer are removed to form an embedded open which exposes the surface of the conducting wire.
Description
Technical field
The present invention relates to the formation method of a kind of internal connection-wire structure and opening thereof, relate in particular to the formation method of a kind of single inlay structure and dual-damascene structure and opening thereof.
Background technology
Along with the progress of semiconductor technology, the size of semiconductor element is also constantly dwindled, and enters in the field of deep-submicron (Deep Sub-Micron).When the integrated level of integrated circuit increases, the surface of wafer can't provide enough areas to make required intraconnections (Interconnect), therefore dwindle the intraconnections that the back is increased for the conjunction with semiconductors element, the design of multi-layer conductive line, just become the ultra-large type integrated circuit technique the mode that must adopt.
Generally speaking, multiple internal connecting lines is to utilize mosaic technology to form mostly, comprising singly inlaying (single-damascene) technology or dual damascene (dual-damascene) technology.At present, mosaic technology defines irrigation canals and ditches (or opening) in dielectric layer mode is to form earlier titanium nitride layer (TiN) on dielectric layer.Then, on titanium nitride layer, form photoresist layer with irrigation canals and ditches (or opening) pattern.Then, with irrigation canals and ditches (or opening) design transfer of photoresist layer to titanium nitride layer.Then, be used as hard mask, in dielectric layer, define irrigation canals and ditches (or opening) with titanium nitride layer with irrigation canals and ditches (or opening) pattern.And; because the restriction of photoetching process; in mosaic technology, can on titanium nitride layer, be formed with one deck plasma enhanced oxide layer (plasma-enhanced oxide usually; PE-oxide); improving process window (process window), and with titanium nitride layer and plasma enhanced oxide layer as the hard mask layer in the mosaic technology.
Yet, in mosaic technology, still have some problems to be solved.For instance, in dielectric layer, define the step of irrigation canals and ditches (or opening) before, must can in hard mask layer, define irrigation canals and ditches (or opening) pattern through the second etch step.So-called second etch step comprises: etching step and etching step for the first time for the second time.Wherein, etching step is for the first time, is mask with the photoresist layer, removes part plasma enhanced oxide layer, to exposing the titanium nitride layer surface.Etching step is that the etching part titanium nitride layer is to exposing the dielectric layer surface for the second time.Therefore, existing mosaic technology need just can be finished through considerable step, and can expend the more process time (cycle time).
Summary of the invention
The purpose of this invention is to provide a kind of formation method of singly inlaying opening, can simplify processing step, and can save the process time.
Another purpose of the present invention provides a kind of single inlay structure, can simplify processing step equally, and can save the process time.
A further object of the present invention provides a kind of formation method of dual damascene opening, can simplify processing step, and can save the process time.
Another object of the present invention provides a kind of dual-damascene structure, can simplify processing step, and can save the process time.
The present invention proposes a kind of formation method of singly inlaying opening.The method is that substrate is provided earlier, has been formed with lead in the substrate.Then, in substrate, form barrier layer, dielectric layer, metal hard mask layer, silicon oxynitride layer, bottom anti-reflection layer and patterning photoresist layer in regular turn.Then, directly remove the bottom anti-reflection layer, silicon oxynitride layer and the metal hard mask layer that are not patterned the photoresist layer and cover, to exposing part dielectric layer surface.Afterwards, remove patterning photoresist layer and bottom anti-reflection layer.Then, be mask with silicon oxynitride layer and metal hard mask, remove the dielectric layer of part and the barrier layer of part, expose with formation lead the surface inlay opening.
Described according to one embodiment of the invention, in the above-mentioned formation method of singly inlaying opening, after forming silicon oxynitride layer, and form before the bottom anti-reflection layer, can also form one deck silicon oxide layer.In another embodiment, also can carry out a surfaction technology to silicon oxynitride layer, to form an oxide layer on silicon oxynitride layer, wherein surfaction technology comprises with oxygen-containing gas and carries out a plasma process.Described according to one embodiment of the invention, in the formation method of above-mentioned damascene opening, the material of lead for example is a copper.The material of metal hard mask layer for example is tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) or tungsten nitride (WN).The material of dielectric layer for example is an advanced low-k materials.
The present invention proposes a kind of single inlay structure, and this single inlay structure comprises substrate, barrier layer, dielectric layer, metal hard mask layer, silicon oxynitride layer and conductor layer.Wherein, dispose lead in the substrate.Barrier layer is positioned in the substrate.Dielectric layer is positioned on the barrier layer.Metal hard mask layer is positioned on the dielectric layer.Silicon oxynitride layer is positioned on the metal hard mask layer.Wherein, have in silicon oxynitride layer, metal hard mask layer, dielectric layer and the barrier layer expose portion lead the surface inlay opening.Conductor layer is disposed to be inlayed in the opening.
Described according to one embodiment of the invention, in the above-mentioned single inlay structure, can comprise that also one deck silicon oxide layer is disposed on the silicon oxynitride layer.In another embodiment, can comprise that also layer of oxide layer is disposed on the silicon oxynitride layer.
Described according to one embodiment of the invention, in the above-mentioned single inlay structure, the material of dielectric layer for example is an advanced low-k materials.The material of metal hard mask layer for example is tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.The material of lead for example is a copper.
The present invention proposes a kind of formation method of dual damascene opening, and the method is that a substrate is provided earlier, has been formed with a lead in the substrate.Then, in substrate, form barrier layer, dielectric layer, metal hard mask layer, silicon oxynitride layer, first bottom anti-reflection layer and the first patterning photoresist layer in regular turn.Then, directly remove first bottom anti-reflection layer, silicon oxynitride layer and the metal hard mask layer that are not covered, expose one first opening on part dielectric layer surface with formation by the first patterning photoresist layer.Afterwards, remove the first patterning photoresist layer and first bottom anti-reflection layer.Then, form the second patterning photoresist layer, cover silicon oxynitride layer and part dielectric layer in the substrate top.Then, be mask with the second patterning photoresist layer, remove the dielectric layer of part, in dielectric layer, to form second opening.Then, remove the second patterning photoresist layer.Subsequently, be mask with silicon oxynitride layer and metal hard mask layer, remove the dielectric layer of part and the barrier layer of part, expose the dual damascene opening of conductive line surfaces with formation.
Described according to one embodiment of the invention, in the formation method of above-mentioned dual damascene opening, after forming silicon oxynitride layer, and form before first bottom anti-reflection layer, can also form one deck silicon oxide layer.In another embodiment, also can carry out a surfaction technology to silicon oxynitride layer.To form an oxide layer on silicon oxynitride layer, wherein surfaction technology comprises with oxygen-containing gas and carries out a plasma process.
Described according to one embodiment of the invention, in the formation method of above-mentioned dual damascene opening, the material of lead for example is a copper.The material of metal hard mask layer for example is tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.The material of dielectric layer for example is an advanced low-k materials.
The present invention proposes a kind of dual-damascene structure, and this dual-damascene structure comprises substrate, barrier layer, dielectric layer, metal hard mask, silicon oxynitride layer and conductor layer.Wherein, dispose lead in the substrate.Barrier layer is positioned in the substrate.Dielectric layer is positioned on the barrier layer.Metal hard mask layer is positioned on the dielectric layer.Silicon oxynitride layer is positioned on the metal hard mask layer.Wherein, the dual damascene opening that has the surface that exposes lead in silicon oxynitride layer, metal hard mask layer and the dielectric layer.Conductor layer is disposed in the dual damascene opening.
Described according to one embodiment of the invention, in the above-mentioned dual-damascene structure, can comprise that also one deck silicon oxide layer is disposed on the silicon oxynitride layer.In another embodiment, can comprise that also layer of oxide layer is disposed on the silicon oxynitride layer.
Described according to one embodiment of the invention, in the above-mentioned dual-damascene structure, the material of dielectric layer for example is an advanced low-k materials.The material of metal hard mask layer for example is tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.The material of lead for example is a copper.
Method of the present invention and structure are to replace existing plasma enhanced oxide layer (PE-oxide) with silicon oxynitride layer, and the present invention defines in dielectric layer before the step of irrigation canals and ditches (or opening), only need single etching step, can in hard mask layer, define irrigation canals and ditches (or opening) pattern.Therefore, method of the present invention and structure can be simplified processing step, and can save the process time.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is a kind of structural profile schematic diagram of singly inlaying the formation flow process of opening according to one embodiment of the invention illustrated;
Fig. 2 A to Fig. 2 G is the structural profile schematic diagram according to the formation flow process of a kind of dual damascene opening that one embodiment of the invention illustrated.
The main element symbol description
100: substrate
102: lead
104: barrier layer
106: dielectric layer
108: metal hard mask layer
110: silicon oxynitride layer
112: bottom anti-reflection layer
114,122: patterning photoresist layer
116: inlay opening
118,128: conductor layer
120,121: irrigation canals and ditches
123: patterns of openings
124,125: opening
126: dual damascene opening
Embodiment
Figure 1A to Fig. 1 D is the flow process generalized section according to the formation method of singly inlaying opening that one embodiment of the invention illustrated.
At first, please refer to Figure 1A, a substrate 100 is provided.Be formed with lead 102 in this substrate 100, the material of lead 102 for example is a copper.
Then, please continue, in substrate 100, form barrier layer 104, dielectric layer 106, metal hard mask layer 108, silicon oxynitride layer 110, bottom anti-reflection layer 112 and patterning photoresist layer 114 in regular turn with reference to Figure 1A.
Wherein, the material of barrier layer 104 for example is silicon nitride (SiN) or other suitable materials, and its formation method for example is a chemical vapour deposition technique.Barrier layer 104 can be avoided the copper surface oxidation and avoid copper to be diffused into dielectric layer 106.Dielectric layer 106 for example is a dielectric layer with low dielectric constant, the material of dielectric layer with low dielectric constant for example is the material that advanced low-k materials comprises mineral-type, for example silane sesquichloride (HSQ), mix the silica (FSG) of fluorine etc., and the material of organic class, for example poly aromatic alkene ether (Flare), aromatic hydrocarbons (SILK), poly-arylene ether (Parylene) etc.The formation method of dielectric layer 106 for example is a chemical vapour deposition technique.In one embodiment, dielectric layer 106 is made of an one deck dielectric layer with low dielectric constant and a layer insulating.The material of this insulating barrier for example is to be the silica that reacting gas source forms with tetraethoxysilane (TEOS), and its formation method for example is a chemical vapour deposition technique.Insulating barrier can be used as the chemico-mechanical polishing stop layer again, when avoiding carrying out chemical mechanical polishing method (CMP), may have the anxiety that is polished to dielectric layer 106.The material of metal hard mask layer 108 for example is tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride, and its formation method for example is a chemical vapour deposition technique.Bottom anti-reflection layer 112 for example is organic bottom antireflective layer or inorganic bottom anti-reflection layer, and wherein the formation method of antireflecting inorganic layer for example is a chemical vapour deposition technique, and its material can comprise amorphous phase carbon film, silicon nitride, silicon oxynitride and titanium oxide etc.
In one embodiment, after silicon oxynitride layer 110 forms, and before bottom anti-reflection layer 112 formation, can also on silicon oxynitride layer 110, form one deck silicon oxide layer (not illustrating), so that the refractive index of silicon oxynitride layer 110 (n) can not change along with the time with dielectric constant (k).
In another embodiment, after silicon oxynitride layer 110 forms, and before bottom anti-reflection layer 112 formation, can also carry out surfaction technology to silicon oxynitride layer 110, on silicon oxynitride layer 110, to form an oxide layer (not illustrating), with refractive index and the dielectric constant of keeping silicon oxynitride layer 110.Surfaction technology for example is with oxygen-containing gas a plasma process to be carried out on the surface of silicon oxynitride layer 110.
Particularly, silicon oxynitride layer 110 can reduce the reverberation of beneath reflection material (metal hard mask layer 108), therefore helps the carrying out of photoetching process.
Then, please refer to Figure 1B, directly remove the bottom anti-reflection layer 112, the silicon oxynitride layer 110 and metal hard mask layer 108 that are not patterned photoresist layer 114 and cover, to the surface that exposes part dielectric layer 106.More specifically, the above-mentioned bottom anti-reflection layer 112, the silicon oxynitride layer 110 that are not patterned photoresist layer 114 and cover of directly removing is to carry out an etch process promptly to finish with the method for metal hard mask layer 108, that is is only to carry out single etching step.
Then, please refer to Fig. 1 C, remove patterning photoresist layer 114 and bottom anti-reflection layer 112, it removes method for example is to carry out an etch process.Afterwards, be mask with silicon oxynitride layer 110 with metal hard mask layer 108, remove the dielectric layer 106 of part and the barrier layer 104 of part, expose with formation lead 102 the surface inlay opening 116.Above-mentioned, the method that removes part dielectric layer 106 and part barrier layer 104 for example is, removes the dielectric layer 106 that is not covered by silicon oxynitride layer 110 and metal hard mask layer 108 earlier, and it removes method for example is to carry out an etch process.Afterwards, remove the barrier layer 104 of exposure again, it removes method for example is to carry out an etch process.
Subsequently, please refer to Fig. 1 D, in inlaying opening 116, insert conductor layer 118, and fiting chemical mechanical polishing (CMP) method grinds off unnecessary metal, to form single inlay structure.The material of conductor layer 118 for example is metal material or polysilicon.
What deserves to be mentioned is that the present invention defines before the step of opening in dielectric layer, only need single etching step, can in hard mask layer, define patterns of openings, therefore can simplify processing step, and can save the process time.
Below, illustrate and utilize the formed single inlay structure of method of the present invention.Wherein, the material of all members illustrates in the foregoing description, so repeat no more in this.
Please referring again to Fig. 1 D, single inlay structure comprises, substrate 100, barrier layer 104, dielectric layer 106, metal hard mask layer 108, silicon oxynitride layer 110 and conductor layer 118.Wherein, dispose lead 102 in the substrate 100.Barrier layer 104 is positioned in the substrate 100.Dielectric layer 106 is positioned on the barrier layer 104.Metal hard mask layer 108 is positioned on the dielectric layer 106.Silicon oxynitride layer 110 is positioned on the metal hard mask layer 108.Wherein, have in silicon oxynitride layer 110, metal hard mask layer 108, dielectric layer 106 and the barrier layer 104 expose portion lead 102 the surface inlay opening 116.Conductor layer 118 is disposed to be inlayed in the opening 116.
In one embodiment, single inlay structure of the present invention also can include one silica layer (not illustrating), and it is disposed on the silicon oxynitride layer 110.
In another embodiment, single inlay structure of the present invention also can include an oxide layer (not illustrating), and it is disposed on the silicon oxynitride layer 110, and this oxide layer is to carry out a plasma process with utilization, and it is formed that upgrading is carried out on silicon oxynitride layer 110 surfaces.Above-mentioned silicon oxide layer and oxide layer act as refractive index and the dielectric constant that can keep silicon oxynitride layer 110, it can not changed in time.
Fig. 2 A to Fig. 2 G is the flow process generalized section according to the formation method of the dual damascene opening that one embodiment of the invention illustrated.In Fig. 2 A to Fig. 2 G, omit the explanation with the identical components of Figure 1A to Fig. 1 D, and represent with same numeral.
At first, please refer to Fig. 2 A, a substrate 100 is provided.Be formed with lead 102 in the substrate 100, the material of metal 102 for example is a copper.
Then, A be please continue, barrier layer 104, dielectric layer 106, metal hard mask layer 108, silicon oxynitride layer 110, bottom anti-reflection layer 112 and patterning photoresist layer 114 in substrate 100, formed in regular turn with reference to Fig. 2.
In one embodiment, after silicon oxynitride layer 110 forms, and before bottom anti-reflection layer 112 formation, one deck silicon oxide layer (not illustrating) can also be formed, on silicon oxynitride layer 110 so that the refractive index of silicon oxynitride layer 110 and dielectric constant can not change along with the time.
In another embodiment, after silicon oxynitride layer 110 forms, and before bottom anti-reflection layer 112 formation, can also carry out surfaction technology to silicon oxynitride layer 110, on silicon oxynitride layer 110, to form an oxide layer (not illustrating), with refractive index and the dielectric constant of keeping silicon oxynitride layer 110.Surfaction technology for example is with oxygen-containing gas a plasma process to be carried out on the surface of silicon oxynitride layer 110.
Then, please refer to Fig. 2 B, directly remove the bottom anti-reflection layer 112, silicon oxynitride layer 110 and the metal hard mask layer 108 that are not patterned photoresist layer 114 and cover, expose the irrigation canals and ditches 120 on part dielectric layer 106 surfaces with formation.
Similarly, silicon oxynitride layer 110 can remove with same etching condition with metal hard mask layer 108, do not need as in the prior art because of metal hard mask layer is different with the material behavior of rete on it, and need remove with two kinds of different etch process conditions.Therefore processing step can be simplified, saving time, and then production capacity can be improved.
Then, please refer to Fig. 2 C, remove patterning photoresist layer 114 and bottom anti-reflection layer 112.Afterwards, form a patterning photoresist layer 122, cover the dielectric layer 106 of silicon oxynitride layer 110 and part in substrate 100 tops.Has a patterns of openings 123 in this patterning photoresist layer 122.
In one embodiment, also can before patterning photoresist layer 122 forms, form one deck bottom anti-reflection layer (not illustrating), cover silicon oxynitride layer 110 and dielectric layer 106 in substrate 100 tops.
Then, please refer to Fig. 2 D.With patterning photoresist layer 122 is mask, removes the dielectric layer 106 of part, to form opening 124 in dielectric layer 106.
Then, please refer to Fig. 2 E, remove patterning photoresist layer 122.The method that removes patterning photoresist layer 122 for example is to carry out an etch process.
Subsequently, please refer to Fig. 2 F, is mask with silicon oxynitride layer 110 with metal hard mask layer 108, removes the dielectric layer 106 of part and the barrier layer 104 of part, to exposing lead 102 surfaces, to form irrigation canals and ditches 121 and opening 125.And irrigation canals and ditches 121 and opening 125 are as dual damascene opening 126.
Afterwards, please refer to Fig. 2 G, in dual damascene opening 126, insert conductor layer 128, and fiting chemical mechanical polishing grinds off unnecessary metal, with respectively at forming lead in the irrigation canals and ditches 121, and in opening 125, form connector, and lead and connector constitute a dual-damascene structure.The material of conductor layer 128 for example is metal material or polysilicon.
Below, illustrate and utilize the formed dual-damascene structure of method of the present invention.Wherein, the material of all members illustrates in the foregoing description, so repeat no more in this.
Please referring again to Fig. 2 G, dual-damascene structure mainly comprises: substrate 100, barrier layer 104, dielectric layer 106, metal hard mask layer 108, silicon oxynitride layer 110 and conductor layer 128.Wherein, dispose lead 102 in the substrate 100.Barrier layer 104 is positioned in the substrate 100.Dielectric layer 106 is positioned on the barrier layer 104.Metal hard mask layer 108 is positioned on the dielectric layer 106.Silicon oxynitride layer 110 is positioned on the metal hard mask layer 108.Wherein, the dual damascene opening 126 that has the surface of expose portion lead 102 in silicon oxynitride layer 110, metal hard mask layer 108 and the dielectric layer 106.Conductor layer 128 is disposed in the dual damascene opening 126.
In one embodiment, dual-damascene structure of the present invention also can include one silica layer (not illustrating), and it is disposed on the silicon oxynitride layer 110.
In another embodiment, dual-damascene structure of the present invention also can include an oxide layer (not illustrating), and it is disposed on the silicon oxynitride layer 110, and this oxide layer is to carry out a plasma process with utilization, and it is formed that upgrading is carried out on silicon oxynitride layer 110 surfaces.Above-mentioned silicon oxide layer and oxide layer act as refractive index and the dielectric constant that can keep silicon oxynitride layer 110, it can not changed in time.
In sum, the present invention defines in dielectric layer before the step of irrigation canals and ditches (or opening), only needs single etching step, can define irrigation canals and ditches (or opening) pattern in hard mask layer.Therefore, method of the present invention and structure can be simplified processing step, and can save the process time.On the other hand, silicon oxynitride layer can also absorb the reverberation from metal hard mask layer, and helps the carrying out of photoetching process.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (23)
1. formation method of singly inlaying opening comprises:
Substrate is provided, has been formed with lead in this substrate;
In this substrate, form barrier layer, dielectric layer, metal hard mask layer, silicon oxynitride layer, bottom anti-reflection layer and patterning photoresist layer in regular turn;
Directly remove this bottom anti-reflection layer, this silicon oxynitride layer and this metal hard mask layer that are not covered, to exposing this dielectric layer surface of part by this patterning photoresist layer;
Remove this patterning photoresist layer and this bottom anti-reflection layer; And
With this silicon oxynitride layer and this metal hard mask layer is mask, removes this dielectric layer of part and this barrier layer of part, expose with formation this lead the surface inlay opening.
2. formation method of singly inlaying opening as claimed in claim 1 wherein after forming this silicon oxynitride layer, and before forming this bottom anti-reflection layer, also comprises: form silicon oxide layer on this silicon oxynitride layer.
3. formation method of singly inlaying opening as claimed in claim 1, wherein after forming this silicon oxynitride layer, and form before this bottom anti-reflection layer, also comprise: this silicon oxynitride layer is carried out surfaction technology, on this silicon oxynitride layer, to form oxide layer.
4. formation method of singly inlaying opening as claimed in claim 3, wherein this surfaction technology comprises with oxygen-containing gas and carries out plasma process.
5. formation method of singly inlaying opening as claimed in claim 1, wherein the material of this metal hard mask layer comprises tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.
6. formation method of singly inlaying opening as claimed in claim 1, wherein the material of this dielectric layer comprises advanced low-k materials.
7. formation method of singly inlaying opening as claimed in claim 1, wherein the material of this lead comprises copper.
8. single inlay structure comprises:
Substrate is disposed lead in this substrate;
Barrier layer is positioned in this substrate;
Dielectric layer is positioned on this barrier layer;
Metal hard mask layer is positioned on this dielectric layer;
Silicon oxynitride layer is positioned on this metal hard mask layer; With
Oxide layer is disposed on this silicon oxynitride layer,
Wherein have in this oxide layer, this silicon oxynitride layer, this metal hard mask layer, this dielectric layer and this barrier layer this lead of expose portion the surface inlay opening; And
Conductor layer is disposed at this and inlays in the opening.
9. single inlay structure as claimed in claim 8, wherein the material of this dielectric layer comprises advanced low-k materials.
10. single inlay structure as claimed in claim 8, wherein the material of this metal hard mask layer comprises tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.
11. single inlay structure as claimed in claim 8, wherein the material of this lead comprises copper.
12. the formation method of a dual damascene opening comprises:
Substrate is provided, has been formed with lead in this substrate;
In this substrate, form barrier layer, dielectric layer, metal hard mask layer, silicon oxynitride layer, first bottom anti-reflection layer and the first patterning photoresist layer in regular turn;
Directly remove this first bottom anti-reflection layer, this silicon oxynitride layer and this metal hard mask layer that are not covered, expose first opening on this dielectric layer surface of part with formation by this first patterning photoresist layer;
Remove this first patterning photoresist layer and this first bottom anti-reflection layer;
Form the second patterning photoresist layer in this substrate top, cover this silicon oxynitride layer and this dielectric layer of part;
With this second patterning photoresist layer is mask, removes this dielectric layer of part, to form second opening in this dielectric layer;
Remove this second patterning photoresist layer; And
With this silicon oxynitride layer and this metal hard mask layer is mask, removes this dielectric layer of part and this barrier layer of part, exposes the dual damascene opening of this conductive line surfaces with formation.
13. the formation method of dual damascene opening as claimed in claim 12 wherein after forming this silicon oxynitride layer, and before forming this first bottom anti-reflection layer, also comprises: form silicon oxide layer on this silicon oxynitride layer.
14. the formation method of dual damascene opening as claimed in claim 12, wherein after forming this silicon oxynitride layer, and before forming this first bottom anti-reflection layer, also comprise: this silicon oxynitride layer is carried out surfaction technology, on this silicon oxynitride layer, to form oxide layer.
15. the formation method of dual damascene opening as claimed in claim 14, wherein this surfaction technology comprises with oxygen-containing gas and carries out plasma process.
16. the formation method of dual damascene opening as claimed in claim 12 wherein before this second patterning photoresist layer forms, also comprises: form second bottom anti-reflection layer in this substrate top, fill up this first opening, and cover this silicon oxynitride layer.
17. the formation method of dual damascene opening as claimed in claim 12, wherein the material of this metal hard mask layer comprises tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.
18. the formation method of dual damascene opening as claimed in claim 12, wherein the material of this dielectric layer comprises advanced low-k materials.
19. the formation method of dual damascene opening as claimed in claim 12, wherein the material of this lead comprises copper.
20. a dual-damascene structure comprises:
Substrate is disposed lead in this substrate;
Barrier layer is positioned in this substrate;
Dielectric layer is positioned on this barrier layer;
Metal hard mask layer is positioned on this dielectric layer;
Silicon oxynitride layer is positioned on this metal hard mask layer; And
Oxide layer is disposed on this silicon oxynitride layer,
The dual damascene opening that wherein has the surface of this lead of expose portion in this oxide layer, this silicon oxynitride layer, this metal hard mask layer, this dielectric layer and this barrier layer; And
Conductor layer is disposed in this dual damascene opening.
21. dual-damascene structure as claimed in claim 20, wherein the material of this dielectric layer comprises advanced low-k materials.
22. dual-damascene structure as claimed in claim 20, wherein the material of this metal hard mask layer comprises tantalum, tantalum nitride, titanium, titanium nitride, tungsten or tungsten nitride.
23. dual-damascene structure as claimed in claim 20, wherein the material of this lead comprises copper.
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| CN101937868B (en) * | 2009-06-30 | 2013-02-13 | 上海华虹Nec电子有限公司 | Method for making through hole in integrated circuit |
| CN102054753B (en) * | 2009-11-10 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for dual-inlay structure |
| CN102820254B (en) * | 2011-06-07 | 2017-03-01 | 联华电子股份有限公司 | The manufacture method of semiconductor integrated circuit |
| CN102315163A (en) * | 2011-09-28 | 2012-01-11 | 上海华力微电子有限公司 | Manufacturing method of ultralow-dielectric-constant film copper-interconnecting layer |
| US8932911B2 (en) * | 2013-02-27 | 2015-01-13 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects |
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| TW580756B (en) * | 2003-01-07 | 2004-03-21 | United Microelectronics Corp | Dual damascene process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW580756B (en) * | 2003-01-07 | 2004-03-21 | United Microelectronics Corp | Dual damascene process |
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| CN101106101A (en) | 2008-01-16 |
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