TW580756B - Dual damascene process - Google Patents

Abstract

A method for eliminating nodule defects during a dual damascene process is disclosed. A semiconductor substrate provided thereon with a dielectric layer, a hard mask layer over the dielectric layer, and a first bottom anti-reflection coating (BARC) layer over the hard mask layer, wherein the hard mask layer comprises a metal layer. On the first BARC layer, a pattern of a first photoresist layer comprising a trench opening exposing a portion of the subjacent first BARC layer is formed. The exposed first BARC layer and the underlying hard mask layer is etched through the trench opening to form a trench recess in the hard mask layer. The first photoresist layer and the first BARC layer are stripped. A second BARC layer is deposited over the hard mask layer and filling the trench recess thereof. On the second BARC layer, a pattern of a second photoresist layer comprising a via opening, which is located above the trench recess, exposing a portion of the subjacent second BARC layer is formed. The exposed second BARC layer, the underlying hard mask layer and the dielectric layer are etched to form a via recess in an upper portion of the dielectric layer. Thereafter the second photoresist layer and the second BARC layer are etched by using a plasma created by a mixture etching gas containing oxygen and fluorocarbon substance, wherein the fluorocarbon substance contains hydrogen.

Description

580756 V. Description of the invention (1) '----- The technical field to which the invention belongs The present invention relates to a metal interconnection process, especially a dual damascene process, which can effectively remove metal polymerization (metallic P 〇lymer) micro-mask or nodule formed by the residue to improve the reliability of the metal interconnecting elements. Prior technology copper dual damascene technology with low dielectric constant dielectric layer is currently known. For high-integration, high-speed logic integrated circuit chip manufacturing, and for deeper than 8 microns The best metal interconnect solution for sub-micro (dee ^ sub-micro) semiconductor manufacturing process. This is because copper has a low resistance value (30% lower than aluminum) and better resistance to electricity.

And migration (electromigration resistance) characteristics, and low dielectric node materials can help reduce the RC delay (RC de lay) between metal wires. It can be seen that the copper-metal dual-damascene interconnect technology is used in integrated circuit manufacturing processes. China appears to be important. Figures 1 to 6 show cross-sectional schematic diagrams of the six main stages of the dual-mounting process using conventional 193nm photoresist. As shown in FIG. 1 (stage i), a dielectric layer is deposited on a 2 conductor substrate (not shown), and then a carbon dioxide (SiC) layer 2, a metal layer 3, and a silicon oxide layer 4 are sequentially formed. Take 180756 V. Invention description (2) and bottom anti-reflective coating (BARC) 5. Next, I93nm photoresist 6 is coated, and a photolithography process and a photomask are used to define a wire trench opening 7 in the photoresist 6. The metal layer 3 is generally made of titanium nitride (TiN) or tantalum nitride (TaN). The purpose is to serve as an etching hard mask to make up for the lack of resistance of the 193nm photoresist to the etching plasma in the subsequent etching step. As shown in FIG. 2 (stage 2), continue to pass downward through the wire trench opening 7 for a while to form a trench opening 8 in the stacking mask composed of the carbonized stone layer 2, the metal layer 3, and the stone layer oxygen layer 4, and stop In the silicon carbide layer 2. Show them one by one (stage 3), connect | ~ ^^^^^ ~ ^ 1 to the anti-reflection bottom layer 9 and form an I93nm photoresistor 10 on the anti-reflection bottom layer 9 and use lithography in the optical array 10 The process definition of the contact hole opening 11 ° is shown in Figure 4 (stage 4). Continue to use the photoresist 10 as the etching mask, and pass through the contact hole opening 11 to ^ #etch the anti-reflective bottom layer 9, the silicon carbide layer 2, and the money is engraved. To part of the dielectric | electrical broadcasting 1 stops, and a contact hole opening 12 is formed. Then proceed to stage 5 to remove the remaining photoresist 10 and anti-reflection base 9 with g gas plasma or hydrogen plasma. However, the oxygen plasma ashing step from stage 4 to stage 5 will cause radon gas. The plasma reacts with the metal layer 3 exposed in the trench opening 8 to form a metal structure 1 3, which may remain in the double inlay opening in the form of micro particles, as shown by ^^. If these metal polymerized residues are not removed, protrusion structures 14 will be formed in the subsequent engraving steps, as shown in Fig. 6 (stage 6). Summary of the Invention

Page 9! 80756 V. Description of the invention (3) Therefore, the main purpose of the present invention is to provide a metal interconnect process that can eliminate the etched metal polymerization residues generated during the dual damascene process and prevent it from affecting subsequent etching. step. To achieve the above object, the present invention provides a no nodule dual damascene process, which includes the following steps: providing a semiconductor substrate on which a dielectric layer and a hard mask layer are sequentially formed on the dielectric An electrical layer and a first anti-reflection underlayer (BARC) are disposed on the hard mask layer, wherein the hard mask layer includes at least a metal layer; the first anti-reflection substrate is on the first anti-reflection portion. Etch the first anti-reflection bottom layer and the hard mask layer through the wire trench opening to etch a recessed trench in the hard mask layer; remove the first photoresist layer and the first anti-reflection bottom layer; deposit a first A second anti-reflection bottom layer fills the recessed trench on the hard mask layer; a second photoresist layer is formed on the second anti-reflection bottom layer and has a contact hole opening to expose a portion of the second anti-reflection layer A bottom layer; etching through the second anti-reflective bottom layer, the hard mask layer, and an etched portion of the dielectric layer through the contact hole opening to etch a contact hole depression in the dielectric layer; and oxygen / hydrofluorocarbon-containing Similar Plasma Gas Etching Ash The second photoresist layer and the second anti-reflection layer. In order to allow your reviewers to further understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the attached δ. However, the drawings are for reference and explanation only.

Those who limit it. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Schematic examples are only preferred embodiments of the present invention, and are not in the scope of S U. The scope of the invention should actually be based on what is claimed in the scope of the patent application. ^ Refer to Figures 7 (a) and (b). Figures 7 (3) and (b) are the first 4 of the present invention. The inlaying process can also be roughly divided into six stages. Stages 1 to 2 of the present invention are double Phase 4 is the same as the aforementioned conventional dual-mosaic phase 1 to phase 4 ′, so it will not be described again. The method of the first preferred embodiment of the present invention will be described from the stage 4 to the stage 5, and those with the same components also use the same symbol or number. First, as shown in FIG. 7 (a), dry etching is performed using a l93nm photoresist 10 as a field-etching mask, and the anti-reflection bottom layer 9, silicon carbide doctor 2 'is etched down to a part of the dielectric layer. 1 stops, forming a partial via opening 12. According to a preferred embodiment of the present invention, the metal layer 3 is composed of titanium nitride (TiN) or nitride button (TaN), and the dielectric layer 1 is a CVD-type carbon-doped oxide layer (CVD-type carbon-doped). silicon oxide) or a low dielectric constant black diamond from Applied Materials Co. Next, as compared with the conventional method, the remaining photoresist 10 and the anti-reflective bottom layer 9 are removed by ashing with an oxygen or hydrogen plasma. The present invention solves the conventional metal polymerization.

Page 11 580756 V. Description of the invention (5) Residual matter, use the oxygen / carbon monoxide / fluoromethane (CH3F) mixed gas plasma to ash the remaining photoresistance 10 and the anti-reflective bottom layer 9 Remove. Among them, the addition of fluoromethane (CH3F) can instantly decompose the metal polymer compounds generated in the etching process, and it can also be replaced by other hydrofluorine-containing alkane gases, such as CH2Frong CHF3. The selective addition of carbon monoxide can improve corner passivation caused by money engraving (c0 r n e r rounding). In other embodiments, carbon monoxide may be omitted and not added. In terms of dosage, according to a preferred embodiment of the present invention, the flow rate of the oxygen / carbon monoxide / fluoromethane (CH 3F) mixed gas is respectively oxygen: 2 0 to " 5—OOsccm7 —: 5 0seem (< 1 0 ( CH3F): 2 ~ 3sccm (< 5scc m is better). The result is shown in Fig. 7 (b), that is, the ashing removal of the remaining photoresist 10 and the anti-reflective bottom layer 9 is completed. Please refer to Fig. 8 (a) and (B), Figures 8 (a) and (b) are schematic diagrams of the method of the second preferred embodiment of the present invention. The method of the second preferred embodiment of the present invention is also only described starting from stage 4 to stage 5, and the same elements The same symbols or numbers are also used. First, as shown in Fig. 8 (a), a 193 nm photoresistor 10 is used as a mask for money engraving, and the anti-reflective bottom layer 9 and the silicon carbide layer are engraved to the last name. 2. Etching until a portion of the dielectric layer 1 stops, forming a ^ via opening (partialial opening) 12. According to a preferred embodiment of the present invention, the 'dielectric layer 1 may be a CVD-type carbon-doped silicon-oxygen layer or Applied Materials ’low dielectric constant black diamond. Next, the residual photoresistance 10 and the anti-reflective bottom layer 9 were performed with an oxygen or hydrogen plasma. OK ashing present invention is to solve the conventional problems metal polymer residues, then taken to a solution containing I "in half, guide

580756 V. Description of the invention (6) The body wafer is wet-cleaned. Among them, the fluorine-containing solution may be a solvent containing NH4 F, CH3C00F or a diluted hydrofluoric acid solution. The result is shown in Figure 8 (b), that is, the removal of the remaining photoresist 10 and the anti-reflective bottom layer 9 is completed. Other viable wet solutions include ST25 0, ST210, and ST 2 55 of ATMI, and commercial cleaning solutions such as NE14 and NE89 of ACT. Please refer to Figs. 9 (a) to (c). Figs. 9 (a) to (c) are schematic diagrams of the method of the third preferred embodiment of the present invention. The dual-inlaying process of the present invention can be roughly divided into six stages similar to the conventional dual-inlaying process described above. The double-inlaying process of the present invention is the same as the four steps from stage 1 to stage 4, and thus will not be described again. The method of the third preferred embodiment of the present invention will only be described starting from stage 4 to stage 6, and those with the same components also use the same symbols.

Number or number. First, as shown in Figure 9 (a), use 19 3 nm photoresist 10 as an etching mask for dry etching, and etch down the anti-reflective bottom layer 9 and the carbide layer 2 'all the way to the part. The dielectric layer 1 is stopped to form a contact via opening 12. According to a preferred embodiment of the present invention, the dielectric layer 1 may be a CVD-type carbon-doped silicon-oxygen layer or a black constant of an applied material public constant. -

Next, compared to the conventional ashing removal of the remaining resistance 10 and the anti-reflective bottom layer 9 with an oxygen or hydrogen plasma, the problem of metal polymer residues is known, and oxygen / fluoride is used instead. The sintering (CH 疋) mixed gas plasma performs ashing (―) to remove the remaining photoresist layer 1 and layer 9. Among them, fluoromethyl

580756 V. Description of the invention (7) Replaced by other hydrofluorine-containing alkane gas, such as CH2F and CHF3. Selective addition of carbon monoxide can improve corner rounding caused by etching. In other embodiments, carbon monoxide may be omitted and not added. In terms of dosage, according to a preferred embodiment of the present invention, the flow rate of the oxygen / carbon monoxide / fluoromethane (CH 3F) mixed gas is oxygen ·· 20 to 50 sccm, carbon monoxide · 50 sccm (< lOOsccm is preferred) 'Fluorocarbon (CH3F) ... 2 ~ 3sccm (< 5scc m is preferred). The result is shown in FIG. 9 (b), that is, the remaining photoresist 10 and the ashing removal of the anti-reflective bottom layer 9 are completed. Then, a double damascene etching step is performed to further ensure that metal poly is not generated during the etching process. ^ Cover phenomenon, plate--argon / oxygen / fluoromethane (CH3F) mixed gas plasma or argon / oxygen / fluoromethane (CFJ / difluoromethane (CH2F2) mixed gas plasma). In the preferred embodiment of the invention, all equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 14 580756 Brief description of the diagrams Brief description of the diagrams Figures 1 to 6 show cross-sectional schematic diagrams of the dual damascene process that is conventionally performed using a 1 93nm photoresist. Figures 7 (a) and (b) are schematic diagrams of the method of the first preferred embodiment of the present invention. Figures 8 (a) and (b) are schematic views of the method of the second preferred embodiment of the present invention. Figures 9 (a), (b) and (c) are schematic views of the method of the third preferred embodiment of the present invention. Explanation of the symbols in the figure 1 Dielectric layer 2 SiC layer 3 Metal layer 4 Silicon oxide layer 5 Anti-reflective bottom layer 6 Photoresist 7 Wire trench opening 8 Trench opening D 9 Anti-reflective bottom layer 10 Photoresist 11 Contact hole opening D 12 Contact hole opening 13 Metal polymer 14 protrusion structure

Claims (1)

580756 6. Scope of patent application1. A no-dule dual damascene process includes the following steps: Provide a semiconductor substrate on which a dielectric layer is sequentially formed, and a hard mask layer is formed on the dielectric layer And a first anti-reflection underlayer (BARC) is disposed on the hard mask layer, wherein the hard mask layer includes at least & a metal layer; and a first photoresist layer is formed on the first anti-reflection substrate. It has a wire trench opening to expose part of the first anti-reflection bottom layer; the first anti-reflection bottom layer and the ^ ^ ^ U ^ ^ ^ 4k Μ are carved through the wire trench opening #;-removing the first photoresist Layer and the first anti-reflection bottom layer; depositing a second anti-reflection bottom layer and filling the recessed trench on the hard mask layer; forming a second photoresist layer on the second anti-reflection bottom layer, which has a A portion of the second anti-reflective underlayer is exposed through the contact hole opening; the second anti-reflective underlayer, the hard mask layer and the dielectric layer are etched through the contact hole opening to etch a portion of the dielectric layer. Contact hole depression; and, with oxygen / The hydroflurane-containing mixed plasma gas is etched to ash and ash the second photoresist layer and the second anti-reflective bottom layer. 2 · The no-protrusion dual damascene process described in item 1 of the scope of the patent application, wherein the hard mask layer further includes a silicon carbide layer and a silicon oxide layer, and the metal layer is sandwiched between the silicon carbide layer and the silicon carbide layer. Between the silicon and oxygen layers. Page 16 580756 6. Scope of patent application 3. The double-inlay process without protrusions as described in item 2 of the scope of patent application, wherein the metal layer is composed of titanium nitride (TiN) or nitride button (TaN). 4. The no-damascene dual damascene process described in item 1 of the scope of patent application, wherein the first photoresist layer is a 193n m photoresist. 5. The process of dual damascene without protrusion as described in item 1 of the scope of patent application, wherein the second photoresist layer is a 193 nm photoresist. 6. The non-protrusion double inlay process as described in item 1 of the scope of the patent application, wherein the oxygen / hydrofluoroalkane mixed plasma gas contains CH 3F, CH 2F $ or CHF3. 7. The process without double protrusions as described in item 6 of the scope of patent application, wherein the oxygen / hydrofluorocarbon-containing mixed plasma gas further includes carbon monoxide. 8. The non-protrusion dual damascene process as described in item 1 of the scope of the patent application, wherein after the second photoresist layer and the second anti-reflective underlayer are ashed by etching with an oxygen / hydrofluorocarbon-based mixed plasma gas. The dual damascene process further includes the following steps: using the hard mask layer as an etching mask, using an argon / oxygen / fluoromethane (CH 3 F) mixed gas plasma or argon / oxygen / fluoromethane (CF4 ) / Difluoromethane (CH Page 17 580756 VI. Patent Application Fanyuan 2F 2) Mixed gas electro-polymerization #engraving for double inlaying funnel ’to form a double inlaid structure (wire trench and contact hole) in the dielectric layer. g A dual damascene process includes the following steps: Provide a semiconductor substrate on which a dielectric layer is sequentially formed, a hard mask layer is formed on the dielectric layer, and a first anti-reflection underlayer (BARC) device is provided. On the hard mask layer, wherein the hard mask layer includes at least a metal layer; a first photoresist layer is formed on the first anti-reflection bottom layer, and a wire washer is exposed to part of the trench opening. A first anti-reflection bottom etches the first anti-reflection bottom layer and the hard mask layer through the opening of the wire trench, so that a hard trench is etched by the hard mask layer; removing the first photoresist layer and the first anti-reflection bottom layer Depositing a second anti-reflection bottom layer and filling the recessed trench on the hard mask layer; forming a second photoresist layer on the second anti-reflection bottom layer having a contact hole opening exposing part of the A second anti-reflective underlayer; etch through the second anti-reflective underlayer, the hard mask layer, and an etched portion of the dielectric layer through the contact hole opening to etch a contact hole depression in the dielectric layer; Gas ash the second A second barrier layer and the anti-reflective substrate; and a fluorine-containing solution followed by wet cleaning the semiconductor substrate. 580756 VI. Application for patent scope I 0. The dual inlaying process as described in item 9 of the scope of patent application, wherein the hard mask layer further includes a carbonized carbide layer and an oxygen fragmentation layer, and the metal layer is sandwiched between the Between the silicon carbide layer and the silicon-oxygen layer. II. The dual damascene process according to item 10 of the patent application, wherein the metal layer is composed of titanium nitride (TiN) or tantalum nitride (TaN). 1 2. The dual damascene process as described in item 9 of the scope of patent application, wherein the first photoresist layer is a 193nm photoresist. 13. The dual damascene process according to item 9 of the scope of patent application, wherein the second photoresist layer is a 193nm photoresist. 1 4. The dual inlaying process as described in item 9 of the scope of patent application, wherein the fluorine-containing solution may be a solvent containing NH4F, CH3C00F or a diluted hydrofluoric acid solution. Page 19