TW200412650A - Dual damascene process - Google Patents

Abstract

A method for eliminating nodule defects during a dual damascene process is disclosed. A semiconductor substrate provided thereon with a dielectric layer, a hard mask layer over the dielectric layer, and a first bottom anti-reflection coating (BARC) layer over the hard mask layer, wherein the hard mask layer comprises a metal layer. On the first BARC layer, a pattern of a first photoresist layer comprising a trench opening exposing a portion of the subjacent first BARC layer is formed. The exposed first BARC layer and the underlying hard mask layer is etched through the trench opening to form a trench recess in the hard mask layer. The first photoresist layer and the first BARC layer are stripped. A second BARC layer is deposited over the hard mask layer and filling the trench recess thereof. On the second BARC layer, a pattern of a second photoresist layer comprising a via opening, which is located above the trench recess, exposing a portion of the subjacent second BARC layer is formed. The exposed second BARC layer, the underlying hard mask layer and the dielectric layer are etched to form a via recess in an upper portion of the dielectric layer. Thereafter the second photoresist layer and the second BARC layer are etched by using a plasma created by a mixture etching gas containing oxygen and fluorocarbon substance, wherein the fluorocarbon substance contains hydrogen.

Description

200412650 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a metal interconnect process, especially a dual damascene process, which can effectively remove metal polymer residues Micro-mask or nodule can improve the reliability of metal interconnecting components. The prior art copper dual damascene technology with low dielectric constant dielectric layer is currently known for the fabrication of high-integration, high-speed logic integrated circuit wafers, and for deeper depths below 0.8 microns. Cdeep sub_micro) best metal interconnect solution for semiconductor process. This is because copper has a low resistance value (30% lower than aluminum) and better resistance to electromigration, and low dielectric constant materials can help reduce the RC delay between metal wires. ), It can be seen that the copper-metal dual-damascene interconnect technology appears to be of great importance in the integrated circuit manufacturing process. Figures 1 to 6 show cross-sectional schematic diagrams of the six main stages of a dual damascene process that is conventionally performed using a 1 93nm photoresist. As shown in FIG. 1 (stage 1), a dielectric layer 1 is deposited on a semiconductor substrate (not shown), and then a silicon carbide (SiC) layer 2, a metal layer 3, and a silicon oxide (si 1 icon oxide) layer 4 are sequentially formed. To

Page 8 200412650 V. Description of the invention (2) and bottom anti-reflective coating (BARC) 5. Next, a 193 nm photoresist 6 is coated, and a photolithography process is used with a photomask to define a wire trench opening 7 in the photoresist 6. The metal layer 3 is generally made of titanium nitride (T i N) or nitride button (TaN), the purpose of which is to serve as an etching hard mask to compensate for the resistance of 193 nm photoresistance to the electrical damage of the etching in the subsequent etching step. Insufficient power. As shown in FIG. 2 (stage 2), the etching is continued through the wire trench opening 7 to form a trench opening 8 'in a stacked mask composed of silicon carbide layer 2, metal layer 3, and silicon oxide layer 4. Evening layer 2. As shown in FIG. 3 (stage 3), an anti-reflective bottom layer 9 'is filled in the trench opening 8 and a 19 3 nm photoresist 10 is formed on the anti-reflective bottom layer 9. A photolithography process is used in the photoresist 10 Define the contact hole opening u. As shown in Figure 4, (Jiefeng and 4) 'continue to use the photoresistor 10 as a mask for the rest of the time, through the contact hole opening 1 1 down to etch the anti-reflective bottom layer 9, the fossil evening layer 2' Part of the dielectric layer 1 stops, forming a contact hole opening 12. Then proceed to stage 5 to remove the remaining photoresist 10 and the anti-reflective bottom 9 with oxygen or hydrogen polymerization. However, the oxygen plasma ashing step from stage 4 to stage 5 will cause the oxygen electrode to react with the metal layer 3 exposed in the trench opening 8 to form a metal polymer 1 3, which may remain in the form of micro particles in the dual mosaic This is shown in Figure 5. If these metal polymerized residues are not happy, "the protrusion structure 14 is formed in the step of engraving, as shown in Fig. 6 (stage 6)." SUMMARY OF THE INVENTION

200412650 V. Description of the invention (3) Therefore, the main purpose of the present invention is to provide a metal interconnection process, which can eliminate the etched metal polymer residues generated during the dual damascene process and avoid affecting the subsequent etching steps. To achieve the above object, the present invention provides a no nodule dual damascene process, which includes the following steps: providing a semiconductor substrate on which a dielectric layer is sequentially formed, and a hard mask layer is formed on the dielectric And a first anti-reflection underlayer (BARC) is disposed on the hard mask layer, wherein the hard mask layer includes at least a metal layer; a first photoresist layer is formed on the first anti-reflection bottom layer, It has a wire trench opening exposing part of the first anti-reflective bottom layer; the first anti-reflective bottom layer and the hard mask layer are etched through the wire trench opening to etch a recessed trench in the hard mask layer; removing the A first photoresist layer and the first anti-reflection bottom layer; a second anti-reflection bottom layer is deposited and fills the recessed trench on the hard mask layer; a second photoresist layer is formed on the second anti-reflection bottom layer It has a contact hole opening exposing part of the second anti-reflective underlayer; through the contact hole opening, the second anti-reflective underlayer, the hard mask layer, and an etched part of the dielectric layer are etched to the dielectric. Electrical layer etching-contact Pits and depressions; and ashing the second photoresist layer and the second anti-reflective underlayer by etching with an oxygen / hydrofluorocarbon-based mixed plasma gas. In order for your reviewers to further understand the features and technical contents of the present invention, please refer to the following detailed description and attached drawings of the present invention. However, the drawings are for reference and explanation only, not for

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5. Description of the invention (4) Those who are restricted. Embodiments The following examples are only preferred embodiments of the present invention through the drawings, and those in the scope of the invention. The scope of the present invention should actually be based on what is claimed in the patent application scope. ▲ Please refer to Fig. 7 (a) and (b). . The dual-mosaic process of the present invention can be roughly divided into six stages similar to the aforementioned conventional dual-mosaic process. The steps 1 to 4 of the dual-mosaic process of the present invention are the same as the conventional dual-mosaic stage 1 to 4, and therefore will not be described again. . The method of the first preferred embodiment of the present invention will only be described starting from stage 4 to stage 5, and those with the same components also use the same symbols or numbers. First, as shown in FIG. 7 (a), a 14-mask mask is used for the 193 nm photoresist 10, and dry etching is performed to etch the anti-reflective bottom layer 9 and the silicon carbide layer 2 'all the way to the dielectric layer 1 Stop, forming a contact hole opening (P artia 1 via 〇pening) 1 2. According to a preferred embodiment of the present invention, the metal layer 3 is composed of titanium nitride (TiN) or tantalum nitride (TaN), and the dielectric layer 1 may be a CVD-type carbon-doped silicon oxide) or Applied Materials Co.'s low dielectric constant black diamond. Next, as compared with the conventional method, the remaining photoresist 10 and the anti-reflective bottom layer 9 are removed by ashes (as s h i n g) with conventional oxygen or hydrogen plasma. The present invention solves the conventional metal polymerization

200412650 V. Description of the invention (5) The problem of residues was changed to oxygen / carbon monoxide / fluoromethane (CH3F) mixed gas plasma to remove the remaining photoresistance 0 and the anti-reflective bottom layer 9 by ashing. Among them, the addition of chloromethane (Ch3F) can instantly decompose the metal polymer compounds generated during the etching process, and it can also be replaced by other hydrogen-fluorine-containing alkane gases, such as (: 11 疋 Rong CHF3. The carbon monoxide is selectively added It can improve corner rounding caused by the rest of the time. In other embodiments, carbon monoxide can also be omitted and not added. In terms of dosage, according to a preferred embodiment of the present invention, oxygen / carbon monoxide / fluoromethane ( The flow rate of CH 3F) mixed gas is oxygen: 200 to 500 sccm ', carbon monoxide: 50 sccm (< 100 sccm), flumethane (CH3F): 2 ~ 3 sccm (&5; scsc m is better). The results are as follows: As shown in Fig. 7 (b), the ashing removal of the remaining photoresist 10 and the anti-reflective bottom layer 9 is completed. Please refer to Figs. 8 (a) and (b). Figs. 8 (a) and (b) are the first embodiment of the present invention. Schematic diagram of the method of the second preferred embodiment. The method of the second preferred embodiment of the present invention is also only described from the stage 4 to the stage 5, and the same components are also designated by the same symbols or numbers. First, as shown in FIG. 8 (a) 'Using 1 9 3 nm light 10 is an etching mask, dry etching is performed, and the anti-reflective bottom layer 9 and the silicon carbide layer 2 are etched downward until the dielectric layer 1 stops to form a partial via opening 12. According to the present invention In a preferred embodiment, the dielectric layer 1 may be a CVD-type carbon-doped silicon-oxygen layer or a low dielectric constant black diamond of Applied Materials. Then, the remaining photoresist 10 and the anti-reflection bottom layer are performed with an oxygen or hydrogen plasma. 9 to carry out ashing removal. In order to solve the problem of conventionally known metal polymer residues, the present invention adopts a fluorine-containing solution

200412650

5. Description of the invention (6) The body wafer is wet-cleaned. Among them, the fluorine-containing solution may be a solvent containing NH 4 F, CHsCOOF or a diluted hydrofluoric acid solution. The result is shown in Figure 8 (b), that is, the removal of the remaining photoresist 10 and the anti-reflective bottom layer 9 is completed. Other viable wet solutions include ST25 0, ST210 and ST25 5 from ATMI, and commercial cleaning solutions such as NE14 and NE89 from ACT.

Please refer to Figs. 9 (a) to (c). Figs. 9 (a) to (c) are schematic diagrams of the method of the third preferred embodiment of the present invention. The dual inlaying process of the present invention can be roughly divided into six stages similar to the conventional dual inlaying process described above. The steps 1 to 4 of the dual inlaying process of the present invention are the same as the conventional dual inlaying stage 1 to stage 4 and therefore, No longer. The method of the third preferred embodiment of the present invention will only be described starting from the stage 4 to the stage 6, and the same components will also use the same symbols or numbers. First, as shown in FIG. 9 (a), using j 93nm photoresist as an etching mask, dry etching is performed, and the anti-reflective bottom layer 9 and the silicon carbide layer 2 are etched down to the dielectric layer. Stop, forming a partial via opening 12. According to a preferred embodiment of the present invention, the dielectric layer 1 may be a CVD-type carbon-doped silicon-oxygen layer or a low-constant black diamond of Applied Materials. One

Next, compared to the conventional ashing removal of the remaining photoresist 10 and the anti-reflective bottom layer 9 with an oxygen or hydrogen plasma, the present invention uses an oxygen / The oxidized rat methane (CLF) mixed gas plasma removes the remaining photoresist 10 and the anti-reflection layer 9 by ashes. Among them, fluoromethane (cH3F) can also be used

Page 13 200412650 V. Description of the invention (7) Replaced by other hydrogen-fluorine-containing alkane gases, such as the selective addition of carbon monoxide to CH 2F or CHF π can improve corner rounding caused by the rest of the time. 〇 In other In the examples, the thorium oxidation inhibitor can be omitted and not added. In terms of dosage, according to a preferred embodiment of the present invention, the flow rate of the oxygen / carbon monoxide / fluoromethane (CH 3F) mixed gas is respectively oxygen: 20 to 50 sccm, carbon monoxide: 50 sccm (< lOOsccm is preferred) ' Fluormethane (CH3F): 2 ~ 3sccm (< 5scc m is preferred). The result is shown in Figure 9 (b), that is, the remaining photoresist 10 and the ashing removal of the anti-reflective bottom layer 9 are completed. Next, a double damascene etching step is performed. To further ensure that the metal polymer micro-masking phenomenon does not occur during the etching process, the etching gas is an argon / oxygen / clinker (C Η 丨) mixed gas plasma or argon / oxygen. / Fluoromethane (CF4) Ar · fluoromethane (CHD mixed gas plasma.) The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to The scope of this post ^.

200412650 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 6 show the schematic cross-sections of the dual damascene process using a conventional 19 3nm photoresist. Figures 7 (a) and (b) are schematic diagrams of the method of the first preferred embodiment of the present invention. Figures 8 (a) and (b) are schematic diagrams of the method of the second preferred embodiment of the present invention. Figures 9 (a), (b) and (c) are schematic views of the method of the third preferred embodiment of the present invention. Explanation of the symbols in the figure 1 Dielectric layer 2 Silicon carbide layer 3 Metal layer 4 Silicon oxide layer 5 Anti-reflective bottom layer 6 Photoresist 7 Wire channel trench opening 8 Trench opening π 9 Anti-reflective bottom layer 10 Photoresistance 11 Contact hole opening π 12 Contact hole opening 13 Metal polymer 14 protrusion structure

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Claims (1)

200412650 6. Scope of patent application 1. A double damascene process with no nodule, including the following steps: Provide a semiconductor substrate on which a dielectric layer is sequentially formed, and a hard mask layer is formed on the dielectric And a first anti-reflective underlayer (B ARC) is disposed on the hard mask layer, wherein the hard mask layer includes at least a metal layer; a first photoresist layer is formed on the first anti-reflective substrate; Having a wire trench opening exposing part of the first anti-reflective bottom layer; etching the first anti-reflective bottom layer and the hard mask layer through the wire trench opening to etch a recessed trench in the hard mask layer; removing The first photoresist layer and the first anti-reflection bottom layer; depositing a second anti-reflection bottom layer and filling the recessed trench on the hard mask layer; forming a second photoresist on the second anti-reflection bottom layer A layer having a contact hole opening to expose a portion of the second anti-reflective underlayer; through the contact hole opening to etch through the second anti-reflective underlayer, the hard mask layer, and an etched portion of the dielectric layer to the Dielectric layer Contacting a hole engraved recess; and an oxygen / hydrogen-containing fluorocarbons mixed gas plasma ashing etch the second light-blocking layer and the second anti-reflection layer. 2. The non-protrusion dual damascene process described in item 1 of the scope of the patent application, wherein the hard mask layer further includes a silicon carbide layer and a silicon oxide layer, and the metal layer is sandwiched between the silicon carbide layer and the silicon carbide layer. Between the silicon and oxygen layers. Page 16 200412650 6. Scope of patent application 3. The double-inlay process without protrusions as described in item 2 of the scope of patent application, wherein the metal layer is composed of titanium nitride (TiN) or nitride button (TaN). 4. The process of the dual damascene process without protrusions described in item 1 of the scope of patent application, wherein the first photoresist layer is a 193n m photoresist. 5. The process of dual damascene without protrusion as described in item 1 of the scope of patent application, wherein the second photoresist layer is a 193 nm photoresist. 6. The double-inlaying process without protrusions as described in item 1 of the scope of the patent application, wherein the oxygen / hydrofluorocarbon-based mixed plasma gas includes ch3f, ch2f $, or chf3. 7. The process without double protrusions as described in item 6 of the scope of patent application, wherein the oxygen / hydrofluorocarbon-containing mixed plasma gas further includes carbon monoxide. 8. The non-protrusion dual damascene process as described in item 1 of the scope of the patent application, wherein after the second photoresist layer and the second anti-reflective underlayer are ashed by etching with an oxygen / hydrofluorocarbon-based mixed plasma gas. The dual damascene process further includes the following steps: using the hard mask layer as an etching mask, using an argon / oxygen / fluoromethane (CH 3 F) mixed gas plasma or argon / oxygen / fluoromethane (CF4) / Difluoromethane (CH Page 17 200412650 VI. Application scope 2f 2) Mixed gas plasma etching for double damascene etching to form a double damascene (conductor trench and contact hole) structure in the dielectric layer. 9. A dual damascene process comprising the steps of: providing a semiconductor substrate with a dielectric layer formed thereon, a hard mask layer formed on the dielectric layer, and a first anti-reflection underlayer (BARC) Provided on the hard mask layer, wherein the hard mask layer includes at least a metal layer; a first photoresist layer is formed on the first anti-reflection bottom layer, and a wire trench opening is exposed to part of the first Anti-reflection bottom layer; etching the first anti-reflection bottom layer and the hard mask layer through the wire trench opening to etch a recessed trench in the hard mask layer; removing the first photoresist layer and the first anti-reflection bottom layer; Depositing a second anti-reflection bottom layer and filling the recessed trench on the hard mask layer; forming a second photoresist layer on the second anti-reflection bottom layer having a contact hole opening exposing part of the first Two anti-reflective underlayers; etch through the second anti-reflective underlayer, the hard mask layer, and an etched portion of the dielectric layer through the opening of the contact hole to etch a contact hole depression in the dielectric layer; Ashes the first A second photoresist layer and the anti-reflective substrate; and a fluorine-containing solution followed by wet cleaning the semiconductor substrate. Page 18 200412650 VI. Application scope of patent 10. The dual-mosaic process as described in item 9 of the scope of patent application, wherein the hard mask layer further comprises a carbonized stone layer and a stone oxygen layer, and the metal layer system Sandwiched between the silicon carbide layer and the silicon oxide layer. 11. The dual damascene process according to item 10 of the scope of the patent application, wherein the metal layer is composed of titanium nitride (TiN) or tantalum nitride (TaN). 12. The dual damascene process as described in item 9 of the scope of patent application, wherein the first photoresist layer is a 193nm photoresist. 1 3. The dual damascene process as described in item 9 of the scope of patent application, wherein the second photoresist layer is a 193nm photoresist. 1 4. The dual inlaying process as described in item 9 of the scope of patent application, wherein the fluorine-containing solution may be a solvent containing NH4F, CH3C00F or a diluted hydrofluoric acid solution. Page 19