1254986 九、發明說明： 【發明所屬之技術領域】 本發明提供一種製作雙鑲嵌結構之方法，尤指一種能有 效去除在蝕刻過程中產生之殘餘聚合物之雙鑲嵌結構的製 作方法。 【先前技術】 銅雙鑲嵌(dual damascene)技術搭配低介電常數(i〇w_k) 介電層為目前所知高積集度、高速(high-speed)邏輯積體電 路晶片製造以及0.18微米以下半導體製程之最佳金屬内連 線解決方案。其原因在於銅具有低電阻值（比鋁低3〇%)以 及較佳抗電致遷(electromigration resistance)等特性，而具 有低介電常數之介電層材料能幫助降低金屬導線之間的 RC延遲(RC delay)，由此可知，具有低介電常數之介電層 材料搭配銅金屬雙鑲嵌内連線技術在積體電路製程中顯得 曰益重要。其中，具有低介電常數之介電層材料包含有含 氟二氧化石夕（fluorinated silica glass，FSG)、有機石夕玻璃 (organosilicate，OSG)以及超低介電常數(Ultra low-k，ULK) 材料(k<2.5)等。 1254986 一般製作雙鑲嵌結構的製程包含有先形成溝渠 (trench-first)之雙鑲嵌製程或是先形成介層洞（via_first)之 雙鑲嵌製程。請參考第1圖至第5圖，第1圖至第5圖顯 示習知以先形成溝渠之方式製作一雙鑲嵌結構之製程的剖 面示意圖。如第1圖所示，首先提供一基底12，其上具有 一導電層14，而在導電層η上具有一由氮化矽（silicon nitride)所構成之底層16。接著，在底層16上依序形成一 第一介電層18、一姓刻停止層2〇、一第二介電層21以及 一抗反射（anti_reflective coating，ARC)層 22，其中，蝕刻停 & 20係由氮化碎材料所形成。接著以旋塗(spin_c〇ating) 方式於抗反射層22之上形成一第一光阻層24，並以微影 衣耘配合光罩在第一光阻層24中定義出具有導線圖案之 溝渠開口 26。 凊參考第2圖所示，然後執行一第一蝕刻製程，透過定 義在第一光阻層24内的溝渠開口 26向下姓刻，在第二介 電層21中形成一溝渠圖案28，並使蝕刻停止在蝕刻停止 層2〇。然後，將第一光阻層24以及抗反射層22去除。接 著如第3圖所示，全面形成一平坦層30，同時，在溝渠圖 案28内亦填入平坦層30之材料。接著，在平坦層3〇上形 成弟一光阻層32。然後於弟二光阻層32中利用微影製 程定義介層洞開口 34。 1254986 繼續，如第4圖所示，以第二光阻層32為蝕刻遮罩， 透過介層洞開口 34向下蝕刻平坦層30、蝕刻停止層20、 第一介電層18直至底層16停止，形成介層洞36。隨後如 第5圖所示，去除剩下的第二光阻層32以及平坦層30， 再蝕刻底層16，以形成具有溝渠以及介層洞之雙鑲嵌結構 38 〇 然而在進行上述蝕刻製程時，往往會伴隨產生許多聚合 物40殘留在雙鑲嵌結構38之側壁及底部，因此若直接於 雙鑲嵌結構38中填入金屬導電層42以製作金屬導線以及 導電插塞，則會產生電阻值增高之情形。習知技術之解決 方法係將基底12移送至一濕式清洗裝置中，對其進行一濕 式清洗製程。但是，當雙鑲嵌結構係結合如OSG等低介電 常數材料以及利用碳化矽材料作為蝕刻停止層時，其所產 生之殘留聚合物，例如具有碳氟原子鍵結之聚合物，已無 法使用習知的濕式清洗製程有效清除。 另一方面，在先形成介層洞之雙鑲嵌結構製程中，係先 以一第一光阻層定義出介層洞圖案，進行貫穿蝕刻至底層 導電層，待去除第一光阻層後，再形成一第二光阻層，定 義出導線溝渠圖案，並以遮罩層中之碳化矽層為蝕刻停止 層，進行溝渠結構之蝕刻，以完成雙鑲嵌結構。在此種雙 1254986 鑲欣結構之衣私中’亦會在介電層侧壁及介層洞底部殘留 聚合物’泣成禮值提馬及RC延遲效應等瑕，疵。同樣地， 傳統濕式清洗方式在面對_由低介電常數材料形成的介 電層以及碳化矽蝕刻停止層所產生之殘留聚合物時，仍然 產生無法有效清除聚合物之問題。 在美國專利弟6,713,402號「清除j虫刻停止層之姓刻後 聚合物的方法(Method for polymer removal following etch-stop layer etch)」中，雖然有揭露在雙鑲嵌結構蝕刻完 成後，將半導體基底傳送至一電漿清洗室中，通入含氣之 電漿以移除殘留之聚合物。然而，如何以更簡便及有效之 方式去除蝕刻介電層後所產生之聚合物，且不會在清除中 破壞雙鑲嵌結構，仍然是業界亟待研究改良之課題。 【發明内容】 因此本發明之主要目的在於提供一種製作雙鑲嵌結構 以及清除其殘留聚合物之方法，以解決上述習知在製作雙 鑲嵌結構時以濕式清洗方式無法有效清除殘留聚合物的問 題0 1254986 根據本發明之申請專利範圍，係揭露一種製作一雙鑲 後結構之方法。首先提供—半導縣底，該半導體基底之 上包含有-導電層。然後於半導體基底上依序形成一介電 層 更遮罩層、一第一抗反射底層以及一第一光阻層， 其中第-光阻層具有—溝渠開口，暴露出部份第一抗反射 底層然後進行—第m]製程，透過溝渠開口姓刻第-抗反射底層以及硬遮罩層，於硬遮罩層蝕刻出一溝渠凹 陷’再去除第—光阻層以及第—抗反射底層。接著，於半 v體基底上依序形成一第二抗反射底層以及一第二光阻 層’其中第二抗反射底層填入該溝渠凹陷中，而第二光阻 層具有一介層洞開口’暴露出部份第二抗反射底層。隨後 進行一第二蝕刻製程，透過介層洞開口蝕穿第二抗反射底 層、硬遮罩層以及餘刻部份介電層，以於介電層中钱刻出 一介層洞凹陷。然後去除第二光阻層以及第二抗反射底 層，並進行一第三钱刻製程，經由介層洞凹陷以及溝渠凹 陷蝕刻介電層，直至暴露出導電層，形成一雙鑲喪結構。 最後進行一乾式清洗製程，去除上述步驟所產生之殘留聚 合物，其中第三蝕刻製程以及乾式清洗製程係於同—反應 室中連續完成。 由於本發明方法係在同一反應室中連續進行第二餘刻 製程、清除第二光阻層、第三蝕刻製程以及乾式清洗製程， 1254986 故能以較低成本和簡單製程，心清除时次個所產生 之殘留聚合物。而且本發明方法係在進行侧製程之同一 反應室中通人氣體’較佳為含氫之氣體，以改變殘留聚合 物的組成，形成較容易清除之物質。 【實施方式】 凊芩考第6圖至第η圖，第6圖至第u圖為本發明製 作雙鑲嵌結構之製程的剖面示意圖，此實例中係採用先形 成溝渠之方式製作雙鑲嵌結構。如第6圖所示，首先提供 一半導體基底100，其上具有一導電層1〇2，設於一第一介 私層104中。接著，於第一介電層1〇4以及導電層1〇2之 上依序形成一底層105、一第二介電層1〇6、一蝕刻停止層 108、一金屬層110、一遮罩層112以及一第一抗反射底層 116。其中，蝕刻停止層108、金屬層u〇以及遮罩層112 係用來作為後續蝕刻製程之硬遮罩層114,而蝕刻停止層 108之材料較佳為碳化石夕，金屬層110之材料較佳為氮化 鈦(TiN)或氮化组(TaN)，遮罩層112則可選擇以電襞形成之 電漿增強氧化(plasma enhanced oxide，PEOX)層。此外，底 層105係為一氮化矽層，而第二介電層ι〇6之材料為低介 電常數材料(k$2.9)，例如FSG、0SG或ULK(k<2.5)材料。 接著，在第一抗反射底層116上沉積一第一光阻層118，並 進行一微影製程，在第一光阻層118中定義出具有導線圖 1254986 案之溝渠開口 120。 然後如第7圖所示，執行一第一蝕刻製程，透過第一光 阻層118内的溝渠開口 120蝕刻遮罩層丨π、金屬層110 以及蝕刻停止層108，在硬遮罩層114中形成一溝渠凹陷 122 ’並使餘刻停止在姓刻停止層1 。然後，將第一光阻 層118以及第一抗反射底層116去除。接著，如第8圖所 示，於硬遮罩層114上形成一第二抗反射底層124，並在 溝渠凹陷122内填入第二抗反射底層124，然後在第二抗 反射底層124上形成一第二光阻層126，再利用微影製程 於第二光阻層126上定義出金屬内連線之介層洞圖案的介 層洞開口 128。如第9圖所示，接著以第二光阻層126為 蚀刻遮罩進行一第二姓刻製程，透過介層洞開口 128向下 姓刻弟一抗反射底層124、蚀刻停止層1 ，一直姓刻至部 伤的第一介電層106停止，形成一介層洞凹陷13〇，形成 「部分(partial)」介層洞開口。所以稱為「部分」介層洞開 口是因為此時蝕刻之介層洞並未穿過整層第二介電層。 隨後如第10圖所示，通入氧氣以清除剩下的第二光阻 層126以及第二抗反射底層124。接著，再利用蝕刻停止 層1〇8作為蝕刻遮罩，進行一第三蝕刻製程，例如一反應 性離子蝕刻（reactive ion etching，RIE)製程，透過介層洞凹 陷130及溝渠凹陷122姓刻第二介電層1〇6以及底層 1254986 直至暴露出導電層102,以在第二介電層106中形成具有 導線溝渠以及介層洞之雙鑲嵌結構132。此時，由於第二 介電層106之材料為低介電常數材料，因此在蝕刻時會產 生具有碳氟鍵結（C-F)之聚合物133殘留於雙鑲嵌結構132 内。另一方面，蝕刻含金屬之硬遮罩層114亦可能產生較 難清除之金屬衍生物。故本發明方法係在第三次蝕刻製程 之後隨即於同一反應室中通入含有氫氣(hydrogen)、氧氣或 四氟化碳(CF4)之氣體，較佳為含氫氣之氣體，以對雙鑲嵌 結構132進行一乾式清洗製程134。其中，乾式清洗製程 134可利用如氬氣(argon)等惰性氣體或氮氣(nitrogen)伴隨 氫氣一同通入反應室中。通入反應室中之氫氣會產生氫自 由基(H)，能取代氟原子，產生較容易清除的碳氫鍵結 (C-H)。此外，當氮氣伴隨氫氣通入反應室時，氮氣會撞擊 聚合物，破壞碳氟鍵結，同時亦會撞擊氫氣，促使氫氣產 生大量氫自由基，提高氫自由基濃度，以增進乾式清洗製 程134之效能。 值得注意的是，本發明之第二蝕刻製程、去除第二光阻 層130與第二抗氧化底層124之步驟、第三蝕刻製程以及 乾式清洗製程134較佳皆於同一反應室中連續完成，以在 乾式清洗製程134中能有效清除殘留聚合物。 12 1254986 接著，請參考第11圖，此時可選擇性將半導體基底丨〇〇 移至一濕式清洗裝置中，對雙鑲嵌結構132進行一濕式清 洗製程。再於雙鑲嵌結構132中填入金屬導電層136，例 如銅金屬，並進行-研磨製程，以完成金屬導線以及導電 · 插基之製作。 在本發明之另-實施例中，先形成介層洞之雙鑲嵌結構 的製作方式係先餘穿第二介電層以形成—介層洞，再於第 -’I電層之上部形成連通於介層洞的導線溝渠，隨後於同· /餘刻反應室中通入含氫氣、氧氣、四氟化碳之氣體，進 行-乾式清洗製程，以清洗餘刻第二介電層後所殘留之聚 合物。 簡而έ之，本發明方法係在同一反應室中，連續進行雙 鑲肷孔洞的部分介層洞蝕刻、去除光阻層、蝕穿介層洞以 及乾式清洗製程，以簡單之製程有效去除蝕刻製程所產生 的殘留聚合物，以使後續製作之金屬導線以及導電插塞能 有較佳電性效能。相較於習知技術，本發明乾式清洗製程 係應用於多步驟之蝕刻製程之後，在蝕刻製程或清除光阻 層之同一反應室直接進行通入氮氣等氣體的乾式清洗方 去可有效去除含破氟鍵結之聚合物。 13 1254986 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖至第5圖為習知製作一雙鑲嵌結構之製程的剖面示 意圖。 第6圖至第11圖為本發明製作雙鑲嵌結構之製程的剖面示 意圖。1254986 IX. Description of the Invention: [Technical Field] The present invention provides a method of fabricating a dual damascene structure, and more particularly to a method of fabricating a dual damascene structure capable of effectively removing residual polymer generated during etching. [Prior Art] Dual damascene technology with low dielectric constant (i〇w_k) The dielectric layer is currently known for high-accumulation, high-speed logic integrated circuit chip fabrication and below 0.18 microns. The best metal interconnect solution for semiconductor processes. The reason is that copper has low resistance (3〇% lower than aluminum) and better resistance to electromigration resistance, while dielectric layer materials with low dielectric constant can help reduce RC between metal wires. RC delay, it can be seen that the dielectric layer material with low dielectric constant and copper metal dual damascene interconnect technology is very important in the integrated circuit process. Among them, the dielectric layer material having a low dielectric constant includes fluorinated silica glass (FSG), organosilicate (OSG), and ultra low dielectric constant (Ultra low-k, ULK). ) Materials (k < 2.5), etc. 1254986 Generally, a process for fabricating a dual damascene structure includes a dual damascene process that first forms a trench-first or a dual damascene process that first forms a via_first. Referring to Figures 1 through 5, FIGS. 1 through 5 are schematic cross-sectional views showing a process for fabricating a dual damascene structure by forming a trench first. As shown in Fig. 1, a substrate 12 is first provided having a conductive layer 14 thereon and a conductive layer η having a bottom layer 16 of silicon nitride. Then, a first dielectric layer 18, a first stop layer 2, a second dielectric layer 21, and an anti-reflective coating (ARC) layer 22 are sequentially formed on the bottom layer 16, wherein the etching stops & The 20 series is formed of nitrided material. Then, a first photoresist layer 24 is formed on the anti-reflective layer 22 by spin coating, and a trench having a wire pattern is defined in the first photoresist layer 24 by using a micro shadow mask and a photomask. Opening 26. Referring to FIG. 2, a first etching process is then performed to form a trench pattern 28 in the second dielectric layer 21 through the trench opening 26 defined in the first photoresist layer 24. The etching is stopped at the etch stop layer 2〇. Then, the first photoresist layer 24 and the anti-reflection layer 22 are removed. Next, as shown in Fig. 3, a flat layer 30 is integrally formed, and at the same time, the material of the flat layer 30 is also filled in the trench pattern 28. Next, a photoresist layer 32 is formed on the flat layer 3A. The via opening 34 is then defined in the second photoresist layer 32 using a lithography process. 1254986 continues, as shown in FIG. 4, with the second photoresist layer 32 as an etch mask, the planarization layer 30, the etch stop layer 20, and the first dielectric layer 18 are etched down through the via opening 34 until the bottom layer 16 stops. A via hole 36 is formed. Then, as shown in FIG. 5, the remaining second photoresist layer 32 and the planar layer 30 are removed, and the underlayer 16 is etched to form a dual damascene structure 38 having trenches and via holes. However, when performing the above etching process, A plurality of polymers 40 are often caused to remain on the sidewalls and the bottom of the dual damascene structure 38. Therefore, if the metal conductive layer 42 is directly filled in the dual damascene structure 38 to form metal wires and conductive plugs, an increase in resistance value is generated. situation. The solution of the prior art is to transfer the substrate 12 to a wet cleaning apparatus for a wet cleaning process. However, when a dual damascene structure is combined with a low dielectric constant material such as OSG and a tantalum carbide material is used as an etch stop layer, the residual polymer produced, for example, a polymer having a carbon fluorine atom bond, is no longer usable. The known wet cleaning process is effectively removed. On the other hand, in the dual damascene structure process in which the via hole is formed first, the via hole pattern is defined by a first photoresist layer, and the through-etching is performed to the underlying conductive layer. After the first photoresist layer is removed, A second photoresist layer is formed to define a wire trench pattern, and the ruthenium stop layer in the mask layer is used as an etch stop layer to etch the trench structure to complete the dual damascene structure. In the case of this double 1254986 inlaid structure, the polymer will remain on the side wall of the dielectric layer and the bottom of the via hole, and the RC delay effect will be the same. Similarly, the conventional wet cleaning method still has a problem that the polymer cannot be effectively removed when faced with a dielectric layer formed of a low dielectric constant material and a residual polymer produced by a ruthenium carbide etch stop layer. In US Patent No. 6,713,402, "Method for polymer removal following etch-stop layer etch", although it is disclosed that the semiconductor substrate is completed after the double damascene structure is etched Transfer to a plasma cleaning chamber and pass a gas-containing plasma to remove residual polymer. However, how to remove the polymer produced by etching the dielectric layer in a more convenient and efficient manner without destroying the dual damascene structure during cleaning is still an issue that needs to be researched and improved in the industry. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for fabricating a dual damascene structure and removing residual polymer thereof, so as to solve the above problem that the residual polymer cannot be effectively removed by wet cleaning when the dual damascene structure is fabricated. 0 1254986 In accordance with the scope of the present invention, a method of making a double inlaid structure is disclosed. First, a semiconducting bottom is provided, and the semiconductor substrate includes a conductive layer thereon. Forming a dielectric layer further mask layer, a first anti-reflective underlayer, and a first photoresist layer on the semiconductor substrate, wherein the first photoresist layer has a trench opening to expose a portion of the first anti-reflection The bottom layer then performs the -mth process, and the first anti-reflective underlayer and the hard mask layer are etched through the trench opening, and a trench recess is etched in the hard mask layer to remove the first photoresist layer and the first anti-reflective underlayer. Then, a second anti-reflective underlayer and a second photoresist layer are formed on the half-v body substrate, wherein the second anti-reflective underlayer is filled in the trench recess, and the second photoresist layer has a via opening A portion of the second anti-reflective underlayer is exposed. A second etching process is then performed to etch through the second anti-reflective underlayer, the hard mask layer, and the remaining portion of the dielectric layer through the via opening to deposit a via recess in the dielectric layer. Then, the second photoresist layer and the second anti-reflective underlayer are removed, and a third etching process is performed, and the dielectric layer is etched through the via recess and the trench recess until the conductive layer is exposed to form a double-inserted structure. Finally, a dry cleaning process is performed to remove the residual polymer produced by the above steps, wherein the third etching process and the dry cleaning process are continuously performed in the same reaction chamber. Since the method of the present invention continuously performs the second engraving process, the second photoresist layer, the third etching process, and the dry cleaning process in the same reaction chamber, the 1254986 can remove the second time at a lower cost and a simple process. Residual polymer produced. Further, in the method of the present invention, a gas, preferably a hydrogen-containing gas, is introduced into the same reaction chamber in which the side process is carried out to change the composition of the residual polymer to form a substance which is easier to remove. [Embodiment] Referring to Figs. 6 to η, FIG. 6 to FIG. u are schematic cross-sectional views showing a process for fabricating a dual damascene structure according to the present invention. In this example, a dual damascene structure is formed by forming a trench first. As shown in Fig. 6, first, a semiconductor substrate 100 having a conductive layer 1〇2 disposed in a first dielectric layer 104 is provided. Then, a bottom layer 105, a second dielectric layer 1〇6, an etch stop layer 108, a metal layer 110, and a mask are sequentially formed on the first dielectric layer 1〇4 and the conductive layer 1〇2. Layer 112 and a first anti-reflective underlayer 116. The etch stop layer 108, the metal layer u 〇 and the mask layer 112 are used as the hard mask layer 114 for the subsequent etching process, and the material of the etch stop layer 108 is preferably carbon carbide, and the material of the metal layer 110 is more Preferably, the titanium nitride (TiN) or the nitrided layer (TaN), the mask layer 112 may be selected from a plasma enhanced oxide (PEOX) layer formed by electrolysis. Further, the underlayer 105 is a tantalum nitride layer, and the second dielectric layer ι6 is made of a low dielectric constant material (k$2.9) such as FSG, 0SG or ULK (k<2.5) material. Next, a first photoresist layer 118 is deposited on the first anti-reflective underlayer 116, and a lithography process is performed. A trench opening 120 having a trace pattern of 1254986 is defined in the first photoresist layer 118. Then, as shown in FIG. 7, a first etching process is performed to etch the mask layer 丨π, the metal layer 110, and the etch stop layer 108 through the trench opening 120 in the first photoresist layer 118, in the hard mask layer 114. A trench depression 122' is formed and the remainder is stopped at the surviving stop layer 1 . Then, the first photoresist layer 118 and the first anti-reflective underlayer 116 are removed. Next, as shown in FIG. 8, a second anti-reflective underlayer 124 is formed on the hard mask layer 114, and a second anti-reflective underlayer 124 is filled in the trench recess 122, and then formed on the second anti-reflective underlayer 124. A second photoresist layer 126 is further defined on the second photoresist layer 126 by a lithography process to define a via opening 128 of the via pattern of the metal interconnect. As shown in FIG. 9 , the second photoresist layer 126 is used as an etch mask to perform a second process, and the interlayer opening 128 is passed through the via hole to form an anti-reflection underlayer 124 and an etch stop layer 1 . The first dielectric layer 106, whose last name is wounded, is stopped, and a via depression 13 is formed to form a "partial" via opening. Therefore, it is called the "partial" via opening because the etched via hole does not pass through the entire second dielectric layer. Subsequently, as shown in Fig. 10, oxygen is introduced to remove the remaining second photoresist layer 126 and the second anti-reflection underlayer 124. Then, the etch stop layer 1 〇 8 is used as an etch mask to perform a third etching process, such as a reactive ion etching (RIE) process, through the via hole recess 130 and the trench recess 122 The second dielectric layer 1〇6 and the bottom layer 1254986 are exposed until the conductive layer 102 is exposed to form a dual damascene structure 132 having wire trenches and via holes in the second dielectric layer 106. At this time, since the material of the second dielectric layer 106 is a low dielectric constant material, the polymer 133 having a fluorocarbon bond (C-F) is left in the double damascene structure 132 during etching. On the other hand, etching the metal-containing hard mask layer 114 may also produce metal derivatives which are difficult to remove. Therefore, in the method of the present invention, a gas containing hydrogen, oxygen or carbon tetrafluoride (CF4), preferably a gas containing hydrogen, is introduced into the same reaction chamber after the third etching process, so that the dual damascene is applied. Structure 132 performs a dry cleaning process 134. Among them, the dry cleaning process 134 can be introduced into the reaction chamber together with an inert gas such as argon or nitrogen with hydrogen. The hydrogen gas introduced into the reaction chamber generates a hydrogen radical (H) which can replace the fluorine atom and produce a hydrocarbon bond (C-H) which is easier to remove. In addition, when nitrogen is introduced into the reaction chamber with hydrogen, nitrogen will strike the polymer, destroy the fluorocarbon bond, and also impact the hydrogen, causing hydrogen to generate a large amount of hydrogen radicals, increasing the concentration of hydrogen radicals to enhance the dry cleaning process. Performance. It should be noted that the second etching process of the present invention, the step of removing the second photoresist layer 130 and the second anti-oxidation underlayer 124, the third etching process, and the dry cleaning process 134 are preferably continuously performed in the same reaction chamber. The residual polymer is effectively removed in the dry cleaning process 134. 12 1254986 Next, please refer to Fig. 11, in which the semiconductor substrate can be selectively transferred to a wet cleaning apparatus to perform a wet cleaning process on the dual damascene structure 132. Further, a metal conductive layer 136, such as copper metal, is filled in the dual damascene structure 132, and a -grinding process is performed to complete the fabrication of the metal wires and the conductive and interposer. In another embodiment of the present invention, the dual damascene structure in which the via hole is first formed is formed by first passing through the second dielectric layer to form a via hole, and then forming a connection on the upper portion of the first-I electrical layer. In the wire trench of the interlayer hole, a gas containing hydrogen, oxygen, and carbon tetrafluoride is then introduced into the same/remaining reaction chamber to perform a dry cleaning process to remove the residue after the second dielectric layer is removed. The polymer. Briefly, the method of the present invention is to continuously perform partial via etching, removal of photoresist layer, etch through via hole and dry cleaning process in the same reaction chamber in the same reaction chamber, and effectively remove the etching by a simple process. The residual polymer produced by the process enables the subsequent fabrication of the metal wires and the conductive plugs to have better electrical performance. Compared with the prior art, the dry cleaning process of the present invention is applied to a multi-step etching process, and the dry cleaning of a gas such as nitrogen gas is directly performed in the same reaction chamber of the etching process or the photoresist layer to remove the gas. A fluorine-bonded polymer. 13 1254986 The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 5 are schematic cross-sectional views showing a process for fabricating a dual damascene structure. 6 to 11 are schematic cross-sectional views showing a process for fabricating a dual damascene structure of the present invention.
14 1254986 【主要元件符號說明】 12 基底 14 導電層 16 底層 18 第一介電層 20 名虫刻停止層層 21 第二介電層 22 抗反射層 24 第一光阻層 26 溝渠開口 28 溝渠圖案 30 平坦層 32 第二光阻層 34 介層洞開口 36 介層洞 38 雙銀散結構 40 聚合物 42 金屬導電層 100 基底 102 導電層 104 第一介電層 105 底層 106 第二介電層 108 名虫刻停止層 110 金屬層 112 遮罩層 114 硬遮罩層 116 第一抗反射底層 118 第一光阻層 120 溝渠開口 122 溝渠凹陷 124 第二抗反射底層 126 第二光阻層 128 介層洞開口 130 介層洞凹陷 132 雙鑲嵌結構 133 聚合物 134 乾式清洗製程 136 金屬導電層14 1254986 [Description of main components] 12 Substrate 14 Conductive layer 16 Underlayer 18 First dielectric layer 20 Insect stop layer 21 Second dielectric layer 22 Anti-reflection layer 24 First photoresist layer 26 Ditch opening 28 Ditch pattern 30 flat layer 32 second photoresist layer 34 via opening 36 via 38 double silver structure 40 polymer 42 metal conductive layer 100 substrate 102 conductive layer 104 first dielectric layer 105 bottom layer 106 second dielectric layer 108 Insect stop layer 110 metal layer 112 mask layer 114 hard mask layer 116 first anti-reflection bottom layer 118 first photoresist layer 120 trench opening 122 trench recess 124 second anti-reflective bottom layer 126 second photoresist layer 128 interlayer Hole opening 130 via hole recess 132 dual damascene structure 133 polymer 134 dry cleaning process 136 metal conductive layer
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