JP2004363447A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a high resistance layer can be removed without changing the shapes of a via hole and a wiring groove. <P>SOLUTION: Plasma treatment of the high resistance layer 12 on the surface of a copper wiring layer 1 exposed to the bottom of the via hole 10 is carried out using etching gas containing reducing gas. The reducing gas can contain at least one in a group of gas consisting of hydrogen, ammonia and hydrazine. An interlayer insulating film 6 whose Young's modulus is 7 or more GPa and whose specific inductive capacity is less than 3 is used. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device by a damascene method using a low dielectric constant insulating film.
[0002]
[Prior art]
In recent years, the speed of a semiconductor device has been remarkably increased, and a transmission delay due to a reduction in signal propagation speed due to wiring resistance and a parasitic capacitance between wirings or between wiring layers in a multilayer wiring portion has become a problem. Such a problem tends to be more remarkable because the wiring resistance and the parasitic capacitance increase as the wiring width and the wiring interval become finer due to the higher integration of semiconductor devices.
[0003]
In order to prevent signal delay due to an increase in wiring resistance and parasitic capacitance, a copper wiring instead of an aluminum wiring has been conventionally introduced, and an insulating film having a low dielectric constant (hereinafter, a Low-k film) is used as an interlayer insulating film. Has been attempted.
[0004]
As a method of forming a copper wiring using a low-k film, there is a method by a damascene method. This is known as a technique for forming a wiring without etching copper in view of the fact that copper is more difficult to control the etching rate than aluminum.
[0005]
A conventional copper wiring forming process by the damascene method will be described with reference to FIGS.
[0006]
First, a stopper film 22 and a Low-k film 23 are formed in this order on a silicon substrate 21 on which a copper wiring layer 20 is formed, to obtain a structure shown in FIG. Here, the copper wiring layer 20 has a barrier metal film 24 and a copper layer 25. Next, the low-k film 23 and the stopper film 22 are etched to form a via hole 26 and a wiring groove 27 shown in FIG.
[0007]
[Problems to be solved by the invention]
A high resistance layer 28 such as copper oxide is formed on the surface of the copper wiring layer 20 exposed by the formation of the via hole 26. Conventionally, the high resistance layer 28 has been removed by physical etching using argon plasma. However, in this method, not only the high-resistance layer 28 but also the inner walls of the via holes 26 and the wiring grooves 27 are etched, so that the opening area is widened and the cross-sectional shape thereof becomes tapered. 7 (a)). In particular, when a porous film is used as the low-k film 23, such a phenomenon is remarkably observed.
[0008]
After removing the high-resistance layer 28, a barrier metal film 29 is formed on the inner surface of the via hole 26 and the wiring groove 27, and a copper layer 30 is embedded in the via hole 26 and the wiring groove 27 to form a via plug 31 and a copper wiring layer 32. I do. Through the above steps, a copper wiring in which the copper wiring layer 20 formed on the silicon substrate 21 and the upper copper wiring layer 32 are electrically connected via the via plug 31 is formed (FIG. 7B). Here, according to the conventional method, there is a problem that the opening area of the via hole 26 and the wiring groove 27 becomes large, so that the distance R between adjacent wirings becomes short and a short circuit occurs.
[0009]
There is also a problem that the plasma-etched copper adheres to the side wall of the via hole 26. The adhered copper diffuses in the low-k film 23 by heating in a later step, and increases the leak current between the wirings.
[0010]
Further, as a result of the low-k film 23 being damaged by the argon plasma, there is a problem that the capacitance between the wirings increases, and the low-k film 23 shrinks to lower the reliability.
[0011]
The present invention has been made in view of such a problem. That is, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of removing a high resistance layer without changing the shapes of via holes and wiring grooves.
[0012]
Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing adhesion of copper to an inner wall of a via hole or a wiring groove when removing a high-resistance layer and reducing a leakage current. .
[0013]
A further object of the present invention is to provide a semiconductor device having excellent electrical characteristics and reliability by using a low-k film that is not easily damaged by plasma.
[0014]
Other objects and advantages of the present invention will become apparent from the following description.
[0015]
[Means for Solving the Problems]
The present invention is a semiconductor device having a metal wiring, wherein an interlayer insulating film on the metal wiring has a Young's modulus of 7 GPa or more and a relative dielectric constant of less than 3. In the present invention, the metal wiring can be a copper wiring. Further, the interlayer insulating film is selected from the group consisting of a porous SiO ₂ film, a SiOC film, a polyallyl ether derivative film, a fluorinated allylene film, a PSG film, a BPSG film, a USG film, a FSG film, a PE-TEOS film, and a SOG film. Any one selected film can be used.
[0016]
The present invention also relates to a method of manufacturing a semiconductor device having a metal wiring, comprising: forming a stopper film on the metal wiring; and forming a stopper film having a Young's modulus of 7 GPa or more and a relative dielectric constant of 3 on the stopper film. Forming an interlayer insulating film that is less than, a step of etching the interlayer insulating film to form an opening reaching the stopper film, and forming a via hole by etching the stopper film exposed at the opening. A step of exposing the metal wiring by etching, a step of forming a wiring groove by etching the interlayer insulating film, and a step of plasma-treating the exposed surface of the metal wiring with a reducing gas.
[0017]
In the method for manufacturing a semiconductor device according to the present invention, the reducing gas may include at least one gas selected from the group consisting of hydrogen, ammonia, and hydrazine.
[0018]
In the method of manufacturing a semiconductor device according to the present invention, the reducing gas may include a hydrogen gas having a concentration of 5 atom% or less. Further, the reducing gas preferably contains a hydrogen gas having a concentration of 0.5 atom% to 2 atom%.
[0019]
In the method for manufacturing a semiconductor device of the present invention, the reducing gas may further include at least one gas selected from the group consisting of nitrogen, helium, neon, argon, krypton, and xenon, in addition to the above-mentioned gases. it can.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
1 to 3 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment.
[0022]
First, a semiconductor substrate 2 on which a copper wiring layer 1 as a metal wiring layer is formed is prepared. Here, the copper wiring layer 1 has a barrier metal film 4 and a copper layer 5. As the semiconductor substrate 2, for example, a silicon substrate or the like can be used.
[0023]
Next, a stopper film 3 is formed on the semiconductor substrate 2 to obtain a structure shown in FIG. The stopper film 3 is preferably made of a material having a high etching selectivity with respect to an interlayer insulating film formed thereon. Specifically, is suitably determined according to the type of the interlayer insulating film, for example, SiC film, _Si x _{N y (e.g., Si 3 N 4, Si 2} N 3, SiN , etc..) Film, SiCN film or An SiOC film or the like can be used. These films can be formed by a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.
[0024]
Next, an interlayer insulating film 6 is formed on the stopper film 3 (FIG. 1B).
[0025]
In the present invention, the interlayer insulating film 6 is preferably an insulating film having a low dielectric constant (hereinafter, referred to as a Low-k film), more preferably a Low-k film having a relative dielectric constant of less than 3. It is particularly preferable that the low-k film has a Young's modulus of 7 GPa or more and a relative dielectric constant of less than 3. By reducing the relative dielectric constant of the interlayer insulating film, the capacitance between wirings can be reduced and the wiring delay time can be reduced. By using a material having a Young's modulus of 7 GPa or more, an interlayer insulating film having sufficient mechanical strength for plasma resistance can be obtained.
[0026]
Examples of the Low-k film having a relative dielectric constant of less than 3 include a porous SiO ₂ film, a SiOC film, a polyallyl ether derivative film, a fluorinated allylene film, a PSG (phosphorus-containing silicate glass) film, and a BPSG (boron) film. Phosphorus-containing silicate glass) film, USG (undoped silicate glass) film, FSG (fluorine-doped silicate glass) film, PE-TEOS (Plasma Enhanced-tetra Ethyl Ortho Silicate) film or SOG (Spin on Glass) film And the like. Further, as a material of the SOG film, for example, hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ) can be given. These films can be formed by a CVD method, a PVD (Physical Vapor Deposition) method, a SOD (Spin on Dielectric Coating) method, or the like.
[0027]
Further, the Young's modulus of the Low-k film can be controlled by, for example, changing the skeleton of the resin constituting the interlayer insulating film, or changing the size and amount of the porous material. Since the hardness of the film increases as the Young's modulus increases, the Young's modulus of the Low-k film is preferably higher in order to improve the resistance to plasma. As a result of intensive studies, the present inventor has found that if the Young's modulus has a value of 7 GPa or more, the level of increase in the capacitance between wirings and the level of film shrinkage fall within a range where there is no practical problem.
[0028]
After the formation of the interlayer insulating film 6, a hard mask 7 is formed thereon (FIG. 1B).
[0029]
The hard mask 7 has a role of preventing the interlayer insulating film 6 from being etched when a resist film described later is formed. The hard mask 7, for example, is deposited by a CVD method or a sputtering method, SiO ₂ film or _Si x _{N y (e.g., Si 3 N 4, Si 2} N 3, SiN , etc..) Film be used as the Can be.
[0030]
After the hard mask 7 is formed, a resist film 8 having a predetermined pattern is formed thereon to obtain a structure shown in FIG. More specifically, a resist film 8 can be formed by applying a photoresist on the hard mask 7 and then exposing and developing the photoresist.
[0031]
Next, the opening 9 is formed by anisotropically etching the hard mask 7 and the interlayer insulating film 6 using the resist film 8 as a mask. This etching automatically stops when the stopper film 3 is reached. Then, as shown in FIG. 2A, a portion 3a of the stopper film 3 is exposed at the bottom of the opening 9.
[0032]
As the etching apparatus, for example, a dual-frequency excitation parallel plate type reactive ion etcher that can apply a predetermined high frequency to each of the upper electrode and the lower electrode can be used. Further, as an etching gas, tetrafluoromethane (CF ₄ ), hexafluorobutine (C ₄ F ₆ ), octafluorobutene (C ₄ F ₈ ), octafluoropentine (C ₅ F ₈ ), trifluoromethane (CHF ₃₎ ) And difluoromethane (CH ₂ F ₂ ) and at least one gas selected from the group consisting of helium (He), argon (Ar), nitrogen (N ₂ ), and carbon monoxide as a diluent gas other than the etching gas. A mixed gas containing at least one gas selected from the group consisting of (CO) and oxygen (O ₂ ) can be used. For example, a mixed gas of octafluorobutene (C ₄ F ₈ ), nitrogen (N ₂ ), and argon (Ar) is introduced into the apparatus as an etching gas, and the upper electrode is maintained in a state where the inside of the etching chamber is maintained at a predetermined pressure. A predetermined power is applied to each of the first and second electrodes to generate plasma.
[0033]
After the etching of the hard mask 7 and the interlayer insulating film 6 is completed, the unnecessary resist film 8 is removed by ashing. For example, ashing can be performed using oxygen (O ₂ ) gas, ammonia (NH ₃ ) gas, or a mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ).
[0034]
Next, the stopper film 3a exposed in the opening 9 is etched to form a via hole 10 (FIG. 2B). For example, a mixed gas of tetrafluoromethane (CF ₄ ) and nitrogen (N ₂ ) is introduced into the above-described two-frequency-excited parallel-plate reactive ion etcher, and while maintaining a predetermined pressure in the etching chamber, A predetermined power is applied to each of the upper electrode and the lower electrode. The stopper film 3a can be etched by the generated plasma.
[0035]
Next, a wiring groove 11 is formed on the via hole 10 by a photolithography method to obtain a structure shown in FIG.
[0036]
In FIG. 2C, the surface of the lower copper wiring layer 1 is exposed at the bottom of the via hole 10. Then, on the exposed surface of the copper wiring layer 1, a high-resistance layer 12 mainly composed of copper oxide generated by reacting copper with oxygen in the atmosphere is formed (FIG. 3A). If an upper copper wiring layer is formed while the high resistance layer 12 is present, the contact resistance increases and the electrical characteristics of the semiconductor device deteriorate. Therefore, after forming the via hole 10 and the wiring groove 11, the high resistance layer 12 is removed as shown in FIG. 3A, and then the process proceeds to the upper copper wiring layer forming step.
[0037]
The present invention is characterized in that the high resistance layer 12 is removed by plasma treatment of the surface of the copper wiring layer 1 using a reducing gas. As the reducing gas, for example, at least one gas selected from the group consisting of hydrogen, ammonia, and hydrazine can be used. Alternatively, plasma treatment may be performed using a mixed gas of a reducing gas and an inert gas. The gas inert to the reducing gas is selected, for example, from the group consisting of nitrogen (N ₂ ), helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe). At least one gas can be mentioned. If an oxidizing gas such as oxygen is contained in the etching gas, it is not preferable because it reacts with the reducing gas to reduce the reducing action.
[0038]
When a plasma treatment is performed using a reducing gas, active hydrogen generated in the plasma is adsorbed on the surface of the copper wiring layer 1 to reduce copper oxide to copper. The active hydrogen also collides with the surface of the copper wiring layer 1 to perform physical etching. When an inert gas is contained in the etching gas, physical etching is also performed using active species generated from the inert gas.
[0039]
In the removal of the high-resistance layer by the conventional method, only physical etching by argon plasma has been performed. On the other hand, the present invention is characterized in that both chemical etching for reducing copper oxide, which is a main component of the high-resistance layer, to copper and physical etching by collision of active species are used in combination. This makes it possible to efficiently remove the high-resistance layer, thereby suppressing etching on the inner walls of the wiring grooves and via holes and reducing damage to the interlayer insulating film. Further, since copper oxide is removed by a reduction reaction to copper, adhesion of copper to the inner walls of via holes and wiring grooves can be reduced as compared with a case where copper oxide is removed only by physical etching.
[0040]
In the present invention, the concentration of the reducing gas contained in the etching gas is determined so that the increase in the capacitance between wirings due to the etching of the inner walls of the via holes and the wiring grooves falls within a practically acceptable level. desirable. For example, in the case where a gas containing hydrogen (H ₂ ) is used as the reducing gas, if the hydrogen concentration is too high, the etching of the inner walls of the wiring grooves and the via holes and the change in the film quality of the interlayer insulating film due to plasma damage occur, and The capacity will increase. Therefore, in practical use, the hydrogen concentration is preferably 5 atom% or less, and more preferably 2 atom% or less. On the other hand, the presence of hydrogen in the etching gas causes a reduction effect to be recognized. However, if the hydrogen concentration is too low, reduction takes time and the throughput decreases. Therefore, the lower limit of the hydrogen concentration is preferably 0.5 atom% or more.
[0041]
After the high resistance layer 12 is removed, a barrier metal film 13 is formed on the inner surfaces of the via hole 10 and the wiring groove 11, and a copper layer 14 is buried in the barrier metal film 13 via the barrier metal film 13 to thereby form the via plug 15. Then, a copper wiring layer 16 is formed (FIG. 3B). The steps from the removal of the high resistance layer 12 to the formation of the barrier metal film 13 are preferably performed continuously. Specifically, it can be performed as follows.
[0042]
After the high resistance layer 12 is removed, a barrier metal film such as a TiN film or a TaN film is formed by a CVD method or a sputtering method while maintaining a vacuum in the same chamber. Subsequently, a copper layer is further formed thereon. Then, the copper layer and the barrier metal film are polished by a chemical mechanical polishing (hereinafter, referred to as CMP) method. As a result, the copper layer and the barrier metal film can be left only inside the via hole and the wiring groove.
[0043]
The copper layer may be buried by another method. For example, after forming a barrier metal film, a seed layer for electroplating is formed on the barrier metal film. Thereafter, copper may be embedded in the via holes and the wiring grooves by a plating method using an electrolytic solution based on copper sulfate (CuSO ₄ ).
[0044]
Through the above steps, the via plug 15 and the copper wiring layer 16 can be formed on the semiconductor substrate 2 having the copper wiring layer 1 (FIG. 3B). Here, the copper wiring layer 16 is electrically connected to the copper wiring layer 1 via the via plug 15.
[0045]
As one example, a porous MSQ film having a relative dielectric constant of 2.2 was formed by a PVD method via a stopper film on a silicon substrate on which a copper wiring layer was formed. Next, after a via hole and a wiring groove were formed in the porous MSQ film, the copper wiring layer exposed at the bottom of the via hole was subjected to a plasma treatment for removing a high resistance layer.
[0046]
Specifically, first, the silicon substrate on which the wiring groove was formed was placed in an etching chamber, and the inside of the chamber was evacuated to a predetermined degree of vacuum. Next, an etching gas in which a hydrogen gas was mixed into a helium gas was introduced into the chamber, and a predetermined high frequency was applied to the upper electrode and the lower electrode to perform a plasma treatment for 10 seconds.
[0047]
Subsequently, a barrier metal film was formed while maintaining a vacuum. Specifically, a TaN film (about 10 nm in thickness) and a Ta film (about 15 nm in thickness) were sequentially formed by a PVD method, and these were used as barrier metal films.
[0048]
After forming the barrier metal film, a seed layer for electroplating was formed on the barrier metal film while maintaining the vacuum. Specifically, a copper film (100 nm thick) was formed by a PVD method, and this was used as a seed layer for electroplating. Then, after forming a copper layer on the seed layer for electroplating by the electroplating method, the copper layer, the seed layer for electroplating and the barrier metal film were polished by the CMP method.
[0049]
In the above example, before and after the plasma processing step for removing the high-resistance layer, detailed observations were made on the shapes of the via holes and the wiring grooves. When the concentration of hydrogen mixed in the helium gas exceeds 2 atom%, an increase in the opening area of the via hole and the wiring groove and an increase in the capacitance between wirings due to a change in the film quality of the interlayer insulating film have come to be observed. When the plasma treatment was performed using only helium gas as Comparative Example 1, the high resistance layer could not be removed.
[0050]
As another example, a porous MSQ film having a Young's modulus of 9.8 GPa and a relative dielectric constant of 2.3 was formed on a silicon substrate on which a copper wiring layer was formed by a PVD method via a stopper film. . Next, after a via hole and a wiring groove were formed in the porous MSQ film, the copper wiring layer exposed at the bottom of the via hole was subjected to a plasma treatment for removing a high resistance layer.
[0051]
Specifically, first, the silicon substrate on which the wiring groove was formed was placed in an etching chamber, and the inside of the chamber was evacuated to a predetermined degree of vacuum. Next, an etching gas in which a hydrogen gas was mixed with a helium gas at a concentration of 1 atom% was introduced into the chamber, and then a plasma treatment was performed for 10 seconds by applying a predetermined high frequency to the upper electrode and the lower electrode.
[0052]
Subsequently, a barrier metal film was formed while maintaining a vacuum. Specifically, a TaN film (about 10 nm in thickness) and a Ta film (about 15 nm in thickness) were sequentially formed by a PVD method, and these were used as barrier metal films.
[0053]
After forming the barrier metal film, a seed layer for electroplating was formed on the barrier metal film while maintaining the vacuum. Specifically, a copper film (100 nm thick) was formed by a PVD method, and this was used as a seed layer for electroplating. Then, after forming a copper layer on the seed layer for electroplating by the electroplating method, the copper layer, the seed layer for electroplating and the barrier metal film were polished by the CMP method.
[0054]
Thereafter, a SiC cover film and a SiO ₂ interlayer insulating film were sequentially laminated, and after opening a contact, a Ti film, a TiN film, and an Al film were further laminated in this order to form an Al pad of 100 μm square.
[0055]
In the above example, the electrical characteristics of the Al pad were evaluated. FIG. 4 shows the change of the cumulative distribution function with respect to the wiring capacitance. In the example of the drawing, the wiring width and the wiring interval at the measurement location are both 0.16 μm. An Al pad manufactured without performing the plasma treatment for removing the high-resistance layer was used as Comparative Example 2 and the same evaluation was performed. Comparative Example 2 was manufactured in the same process as described above, except that a barrier metal film was formed without performing plasma processing after forming a wiring groove.
[0056]
As can be seen from FIG. 4, almost no increase in the capacitance between wirings was observed regardless of the presence or absence of the plasma treatment. This indicates that the shapes of the via holes and the wiring grooves hardly change even when the plasma processing is performed.
[0057]
Further, as Comparative Example 3, a sample in which a porous MSQ film having a Young's modulus of 3.7 GPa and a relative dielectric constant of 2.2 was formed by a PVD method was produced, and the same evaluation as in FIG. 4 was performed. Unlike the example of FIG. 3, the Young's modulus was lowered by changing the skeleton of the resin constituting the MSQ film. In addition, the same evaluation was performed using Al porous pads manufactured using the same porous MSQ film as in Comparative Example 3 and without performing the plasma treatment for removing the high-resistance layer, as Comparative Example 4. Note that Comparative Examples 3 and 4 were manufactured in the same steps as in the example of FIG. 4 except for the above.
[0058]
FIG. 5 shows the change of the cumulative distribution function with respect to the wiring capacitance in Comparative Example 3 and Comparative Example 4. As can be seen from FIG. 5, by performing the plasma treatment for removing the high-resistance layer, the inter-wiring capacitance was changed up to about 14%.
[0059]
Further, the cross-sectional shapes of these Al pads were observed in detail. In the case of the porous MSQ film having a Young's modulus of 9.8 GPa, there was almost no change in the cross-sectional shape even when the plasma treatment for removing the high-resistance layer was performed. On the other hand, in the porous MSQ film having a Young's modulus of 3.7 GPa, shrinkage of the MSQ film due to the plasma treatment was observed. The shrinkage was about 5% of the wiring interval.
[0060]
In the present embodiment, an example in which a copper wiring layer is formed has been described, but the present invention is not limited to this. For example, a wiring layer of a metal other than copper may be formed on the semiconductor substrate. Further, the present invention can be applied to the purpose of removing the oxidized high-resistance layer by plasma treatment.
[0061]
Further, in this embodiment mode, an example is described in which a resist pattern is transferred to a hard mask and then the interlayer insulating film is etched using the hard mask. However, the present invention is not limited to this. For example, a resist pattern may be directly transferred to an interlayer insulating film without providing a hard mask.
[0062]
【The invention's effect】
According to the present invention, by removing the high-resistance layer using a reducing gas, it is possible to prevent the inner walls of the via holes and the wiring grooves from being etched, and to suppress an increase in the capacitance between wirings. Further, it is possible to prevent the metal from adhering to the inner wall of the via hole or the wiring groove, thereby reducing the leak current.
[0063]
Further, according to the present invention, by using an interlayer insulating film having a Young's modulus of 7 GPa or more, damage due to plasma processing can be reduced.
[Brief description of the drawings]
FIGS. 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present embodiment.
FIGS. 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the present embodiment.
FIGS. 3A and 3B are cross-sectional views illustrating a manufacturing process of the semiconductor device in the present embodiment.
FIG. 4 is a diagram showing a change in a cumulative distribution function with respect to wiring capacitance when the Young's modulus is 9.8 GPa.
FIG. 5 is a diagram illustrating a change in a cumulative distribution function with respect to wiring capacitance when the Young's modulus is 3.7 GPa.
FIGS. 6A and 6B are cross-sectional views illustrating a process for manufacturing a conventional semiconductor device.
FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device.
[Explanation of symbols]
1,20 copper wiring layer, 2 semiconductor substrate, 3,22 stopper film, 4,13,24,29 barrier metal film, 5,14,25,30 copper layer, 6,23 interlayer insulating film, 7 hard mask, 8 Resist film, 9 opening, 10, 26 via hole, 11, 27 wiring groove, 15, 31 via plug, 21 silicon substrate.

Claims (8)

A semiconductor device having metal wiring,
A semiconductor device, wherein the interlayer insulating film on the metal wiring has a Young's modulus of 7 GPa or more and a relative dielectric constant of less than 3. 2. The semiconductor device according to claim 1, wherein said metal wiring is a copper wiring. The interlayer insulating film is selected from the group consisting of a porous SiO ₂ film, a SiOC film, a polyallyl ether derivative film, a fluorinated allylene film, a PSG film, a BPSG film, a USG film, a FSG film, a PE-TEOS film, and a SOG film. The semiconductor device according to claim 1, wherein the semiconductor device is any one of the films. A method for manufacturing a semiconductor device having metal wiring,
Forming a stopper film on the metal wiring,
Forming an interlayer insulating film having a Young's modulus of 7 GPa or more and a relative dielectric constant of less than 3 on the stopper film;
Forming an opening reaching the stopper film by etching the interlayer insulating film;
Forming a via hole by etching the stopper film exposed in the opening to expose the metal wiring;
Forming a wiring groove by etching the interlayer insulating film;
Performing a plasma treatment on the exposed surface of the metal wiring with a reducing gas. The method for manufacturing a semiconductor device according to claim 4, wherein the reducing gas includes at least one gas selected from the group consisting of hydrogen, ammonia, and hydrazine. The method for manufacturing a semiconductor device according to claim 4, wherein the reducing gas includes a hydrogen gas having a concentration of 5 atom% or less. The method according to claim 6, wherein the reducing gas includes a hydrogen gas having a concentration of 0.5 atom% to 2 atom%. The method for manufacturing a semiconductor device according to claim 5, wherein the reducing gas further includes at least one gas selected from the group consisting of nitrogen, helium, neon, argon, krypton, and xenon.

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