JP2008041783A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve interconnections in yield while keeping a wiring pattern of dual damascene structure good in shape. <P>SOLUTION: When a wiring groove is formed through a via-first method after a viahole is formed through a dual damascene method; an etch stopping film, an insulating film, and a via resist film are formed in this sequence (S102). Further, the insulating film is selectively etched using the via resist film as a mask to bore a viahole in the insulating film (S104). Thereafter, the via resist film is removed (S106). In succession, the etch stopping film is selectively etched using the insulating film as a mask to disclose lower wiring in the viahole (S108). Thereafter, the insulating film is selectively etched using the wiring resist film as a mask to form a wiring groove, and the wiring pattern of damascene structure is formed on the insulating film (S110). Thereafter, the wiring resist film is removed (S112). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with miniaturization and speeding up of semiconductor devices, copper (Cu) wiring having a low resistance has been used. The copper wiring is formed by a damascene method. In the damascene method, first, an interlayer insulating film is formed on a lower wiring. Next, a resist film having a predetermined pattern is formed on the interlayer insulating film, and the interlayer insulating film is selectively etched using the resist film as a mask to form recesses such as via holes and wiring grooves reaching the lower layer wiring. Thereafter, copper is embedded in the recess. Subsequently, the copper exposed to the outside of the recess is removed by CMP (Chemical Mechanical Polishing). By repeating this procedure, a multilayer wiring structure is formed.

  By the way, the damascene method includes a dual damascene method in which a via hole and a wiring groove are simultaneously formed, and a single damascene method in which a via hole and a wiring groove are separately formed. One of the dual damascene methods is a via first method in which a wiring pattern is formed after forming a via pattern in an insulating film for forming a copper wiring.

  Patent Document 1 (Japanese Patent Laid-Open No. 2004-186697, FIGS. 7D to 7F) and Patent Document 2 (Japanese Patent Laid-Open No. 11-186391) describe a procedure for forming a copper wiring by the via first method. In these documents, copper wiring is formed by the following procedure. First, using a via resist film having a via pattern for forming vias as a mask, the interlayer insulating film and the etching stopper film are selectively removed by etching to form a via hole reaching the lower layer wiring. Subsequently, the via resist film is removed. Next, using a wiring resist film having a wiring pattern for wiring formation as a mask, the interlayer insulating film is selectively removed by etching to form a wiring groove, thereby forming a wiring pattern having a dual damascene structure. Thereafter, the wiring resist film is removed, copper is embedded in the wiring pattern, and the copper outside the pattern is removed to form wiring.

  However, when the above procedures described in Patent Document 1 and Patent Document 2 are used, there are the following problems. The resist film used for forming the via hole and the wiring groove in the interlayer insulating film is removed by ashing such as oxygen plasma ashing. If oxygen plasma ashing is performed with the copper film surface of the lower layer wiring exposed, the copper film surface is oxidized and the contact resistance between the wirings increases. Therefore, if the etching stopper film is removed and the resist film is removed in a state where the lower layer wiring surface is exposed, ashing at the time of removing the resist film oxidizes the lower layer wiring and lowers the yield of vias. The reliability will be reduced.

  Patent Document 3 (Japanese Patent Laid-Open No. 2000-352827) describes a procedure for forming a copper wiring by a single damascene method. In this document, in order to prevent the influence of the above-described oxygen plasma ashing on the copper wiring, via holes are formed in the interlayer insulating film formed on the etching stopper film using the resist film as a mask, and the resist film is removed. A procedure for removing the etching stopper film is described later.

From the viewpoint of protecting the lower layer wiring, even when the copper wiring is formed by the dual damascene method, it is preferable to protect the lower layer wiring with an etching stopper film or the like until the resist film is removed. Patent Document 1 describes a procedure for forming a via hole and a wiring groove while leaving an etching stopper film formed immediately above a lower wiring, removing a resist film, and then removing the etching stopper film (FIG. 2A). -FIG. 2E). In this way, ashing of the resist film is performed in a state where the lower layer wiring is protected, so that the influence on the copper wiring due to the oxygen plasma ashing as described above can be prevented.
JP 2004-186697 A Japanese Patent Laid-Open No. 11-186391 JP 2000-352827 A

  However, according to the procedure described in Patent Document 1 (FIGS. 2A to 2E), when the etching stopper film is removed by etching, the interlayer insulating film and the like are also etched, resulting in the outline of the wiring pattern and the CD (critical dimension). Another problem arises that affects

According to the present invention,
Forming an etching stopper film on the lower conductive film formed on the semiconductor substrate;
Forming an insulating film on the etching stop film;
Forming a via resist film having a via pattern for forming vias connected to the lower conductive film on the insulating film;
Using the via resist film as a mask, selectively etching the insulating film to form a via hole in the insulating film;
Removing the via resist film;
Selectively etching the etch stop film using the insulating film as a mask to expose the lower conductive film in the via hole;
Forming a wiring resist film having a wiring pattern for forming a wiring groove connected to the via hole on the insulating film;
Using the wiring resist film as a mask, selectively etching the insulating film to form a wiring groove, and forming a dual damascene structure wiring pattern on the insulating film;
Removing the resist film for wiring;
A method for manufacturing a semiconductor device is provided.
That is, when providing via holes for vias for connecting the lower conductor and the upper conductor by the dual damascene method in the insulating layer between them using a resist layer selectively formed on this insulating layer as a mask, The resist layer is removed after the via hole is formed partway, and then the via hole is completed to expose a part of the surface of the lower conductor, and then a wiring groove is formed.

  With such a configuration, when the wiring is formed by the dual damascene via first method, the lower conductive film is covered with the etching stopper film when the via resist film is removed. The surface can be protected. On the other hand, since it is not necessary to remove the etching stopper film after the wiring pattern is formed, the shape of the wiring pattern can be kept good. Here, the lower conductive film can be a wiring or a via. The lower conductive film can be composed mainly of copper. When the lower conductive film is composed mainly of copper, the surface of the lower conductive film can be prevented from being oxidized when the via resist film is removed, and the yield of wiring can be improved. . In another example, the lower conductive film can be made of tungsten, polysilicon, or the like. Even in such a case, if the surface of the lower conductive film is exposed at the time of removing the via resist film, the lower conductive film may be damaged by the influence of plasma of plasma ashing. According to the present invention, such damage can be prevented and the yield of wiring can be improved.

  In the present invention, in the step of removing the via resist film, it is only necessary that the surface of the lower conductive film is covered with the etching stopper film. In the step of forming the via hole, the insulating film is etched so as to reach the etching stopper film. Further, the upper portion of the etching stopper film may be etched, or the insulating film may be etched so that a part of the insulating film remains on the surface of the lower conductive film. In the step of forming the via hole, if a part of the insulating film remains on the surface of the lower conductive film, the insulating film can be selectively etched in the step of exposing the lower conductive film, and then the etching stopper film is formed. It can be etched.

  According to the present invention, when the dual damascene structure is formed by the via first method, the wiring yield can be improved and the reliability of the semiconductor device can be improved while keeping the shape of the wiring pattern good.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a flowchart showing a manufacturing procedure of a semiconductor device according to the present embodiment.

  In the present embodiment, first, a lower layer wiring (lower layer conductive film) is formed on a semiconductor substrate (S100). In the present embodiment, the lower layer wiring can be composed mainly of copper. Subsequently, an etching stopper film and an interlayer insulating film (insulating film) are formed on the lower wiring (S102). Next, via holes are formed in the interlayer insulating film using the via resist film as a mask (S104). At this time, the etching stopper film remains on the lower wiring. Thereafter, the via resist film is removed by ashing (S106). Subsequently, the etching stopper film is removed by etching using the interlayer insulating film as a mask (S108). Thereby, the lower layer wiring is exposed. Next, a wiring resist film is formed on the interlayer insulating film, and a wiring groove is formed in the interlayer insulating film using the wiring resist film as a mask (S110). Thereby, a wiring pattern having a dual damascene structure is formed. Thereafter, the wiring resist film is removed (S112). Thereafter, the wiring pattern is filled with a conductive material to form upper layer wiring and vias (S114).

  In this way, when forming the wiring by the dual damascene via first method, when removing the via resist film, the lower layer wiring is covered with the etching stopper film, so that the lower layer wiring surface is protected. can do. In particular, when the lower layer wiring is composed mainly of copper, there arises a problem that the surface of the lower layer wiring is oxidized due to the influence of plasma ashing when the via resist film is removed and the wiring characteristics are deteriorated. However, according to the method of the present embodiment, oxidation of the lower layer wiring can be prevented. On the other hand, since it is not necessary to remove the etching stopper film after the wiring pattern is formed, the shape of the wiring pattern can be kept good.

2 to 4 are process cross-sectional views illustrating the manufacturing procedure of the semiconductor device according to the present embodiment.
First, a lower insulating film 102 and a protective insulating film 103 are formed on a semiconductor substrate (not shown), and a lower wiring 104 is formed in the protective insulating film 103 and the lower insulating film 102. The semiconductor substrate is, for example, a silicon substrate. The lower insulating film 102 can be composed of a low dielectric constant film similar to an interlayer insulating film 108 described later. The protective insulating film 103 can be formed using a material similar to that of the protective insulating film 110 described later. The lower layer wiring 104 can be formed of a copper film and a barrier metal film formed around the copper film, similarly to an upper layer wiring 126 described later. Subsequently, an etching stopper film 106 is formed on the entire surface of the protective insulating film 103. The etching stop film 106 can be made of, for example, SiCN.

  Next, an interlayer insulating film 108 is formed on the entire surface of the etching stopper film 106. The interlayer insulating film 108 can be formed of a low dielectric constant film having a relative dielectric constant of 3.3 or less, more preferably 2.9 or less, for example. The low dielectric constant film is, for example, a carbon-containing material such as SiOC (SiOCH), methylsilsesquioxane (MSQ), hydrogenated methylsilsesquioxane (MHSQ), organic polysiloxane, or a porous version of these films. Can be configured.

Thereafter, a protective insulating film 110 is formed on the entire surface of the interlayer insulating film 108. The protective insulating film 110 can be composed of, for example, SiO ₂ . The low dielectric constant film is generally weaker in chemical resistance and mechanical strength than the SiO ₂ film conventionally used as an insulating film between wirings. For this reason, when a low dielectric constant film material is used as the interlayer insulating film, the interlayer insulating film is also removed in the CMP process, which causes an increase in wiring resistance and variations. The protective insulating film 110 is provided for the purpose of protecting the interlayer insulating film in the CMP process. Therefore, the protective insulating film 110 is made of a material having a higher mechanical strength than the material constituting the underlying interlayer insulating film 108. Thus, the structure shown in FIG. 2A is obtained.

  Subsequently, a via resist film 112 having a via pattern for forming vias connected to the lower wiring 104 is formed on the protective insulating film 110 (FIG. 2B). Although not shown here, an antireflection film may be formed between the protective insulating film 110 and the via resist film 112. Next, using the via resist film 112 as a mask, the protective insulating film 110 and the interlayer insulating film 108 are selectively and selectively dry etched to form a via hole 116 in the protective insulating film 110 and the interlayer insulating film 108 (FIG. 2C). )). Here, the etching stopper film 106 is not etched.

  Thereafter, the via resist film 112 is removed by ashing such as oxygen plasma ashing (FIG. 3A). When the antireflection film is formed, the antireflection film is also removed. Further, after the ashing, the inside of the via hole 116 can be cleaned using a stripping solution or the like.

  Subsequently, using the protective insulating film 110 and the interlayer insulating film 108 as a hard mask, the etching stopper film 106 is dry-etched to expose the surface of the lower layer wiring 104 in the via hole 116 (FIG. 3B). At this time, for example, a fluorocarbon-based gas can be used as the etching gas. As a result, the via hole 116 reaches the lower layer wiring 104.

  In this embodiment, when the via resist film 112 is removed, the surface of the lower layer wiring 104 only needs to be covered and protected by the etching stopper film 106. In the step of forming the via hole 116 described with reference to FIG. 2C, the interlayer insulating film 108 may be etched so as to reach the etching stopper film 106, and the upper portion of the etching stopper film 106 is also etched. Alternatively, the interlayer insulating film 108 may be etched with a part of the interlayer insulating film 108 remaining. When the interlayer insulating film 108 remains, the remaining interlayer insulating film 108 can be selectively etched in the step of exposing the lower layer wiring 104 after the removal of the via resist film 112, and then the etching stopper film. 106 can be etched.

  Next, a first wiring resist film 118 is formed on the protective insulating film 110, and the via hole 116 is also filled with the first wiring resist film 118. The first wiring resist film 118 can be made of, for example, an organic polymer such as a novolac type phenol resin. The first wiring resist film 118 can be a film having an antireflection function. Although not shown, when the resist material that fills the via hole 116 does not have an antireflection function, a resist film having an antireflection function may be separately provided over the protective insulating film 110. Thereafter, a second wiring resist film 120 having a wiring pattern for forming a wiring groove connected to the via hole 116 is formed on the first wiring resist film 118 (FIG. 3C).

  Subsequently, using the second wiring resist film 120 as a mask, the first wiring resist film 118, the protective insulating film 110, and the interlayer insulating film 108 are selectively etched to form a wiring groove 124 (FIG. 4). (A)). When the interlayer insulating film 108 is composed of a low dielectric constant film, the low dielectric constant film is exposed at the bottom of the wiring trench 124. Thereby, a wiring pattern having a dual damascene structure is formed. Note that when the wiring trench 124 is formed, the surface of the lower layer wiring 104 is protected because the first wiring resist film 118 is filled in the via hole 116.

  Next, the second wiring resist film 120 and the first wiring resist film 118 are removed by ashing such as oxygen plasma ashing (FIG. 4B). Also at this time, since the first wiring resist film 118 is filled in the via hole 116, the surface of the lower wiring 104 is protected until the first wiring resist film 118 filled in the via hole 116 is removed. It will be in the state. Thereby, the oxidation of the surface of the lower layer wiring 104 can be suppressed. Further, after the ashing, the inside of the wiring groove 124 and the via hole 116 can be cleaned using a stripping solution or the like.

  Thereafter, a wiring material is embedded in a wiring pattern having a dual damascene structure constituted by the wiring trench 124 and the via hole 116. Specifically, for example, a barrier metal film is formed in the wiring pattern by sputtering or atomic layer deposition (ALD). The barrier metal film can be, for example, Ta / TaN, Ti, TiN, TiSiN, Ta, TaN, or TaSiN. Subsequently, the wiring pattern is filled with a copper film. The copper film can be formed by, for example, a plating method. Further, the copper film may be configured to include a metal other than copper, such as Ag. Next, the copper film and the barrier metal film exposed outside the wiring pattern are removed by a CMP method. Thereby, the upper layer wiring and the via 126 are formed (FIG. 4C). Further, after that, a third etching stop film 111 is formed on the protective insulating film 110 (FIG. 4D). The third etching stopper film 111 can be made of the same material as the etching stopper film 106. By repeating the above steps, the semiconductor device 100 having a multilayer wiring structure is formed.

FIG. 5 is a process cross-sectional view illustrating another example of the manufacturing procedure of the semiconductor device 100.
In the above, the interlayer insulating film 108 is shown as a single layer, but the interlayer insulating film 108 can have a laminated structure of various insulating films. For example, the interlayer insulating film 108 can be a laminated film of a low dielectric constant film, an etching stopper film, and a low dielectric constant film. FIG. 5 is a diagram showing such a configuration.

  On the etching stopper film 106, a first interlayer insulating film 108a, a second etching stopper film 128, and a second interlayer insulating film 108b are stacked in this order. The first interlayer insulating film 108a and the second interlayer insulating film 108b can be formed of a material similar to that of the interlayer insulating film 108. The second etching stop film 128 functions as a stop film for controlling the etching rate when forming the wiring groove 124. The material forming the second etching stopper film 128 is not particularly limited, but may be formed of a material having an etching selectivity with respect to the second interlayer insulating film 108b. For example, the second etching stop film 128 can be made of the same material as the etching stop film 106.

  Such a configuration can be formed by the same procedure as described with reference to FIGS. After the first interlayer insulating film 108a, the second etching blocking film 128, and the second interlayer insulating film 108b are formed in this order on the etching stop film 106, protective insulation is performed using the via resist film 112 as a mask. The via hole 116 is formed by selectively etching the film 110, the second interlayer insulating film 108b, the second etching stop film 128, and the first interlayer insulating film 108a. Here, the etching stopper film 106 is not etched. Subsequently, after the via resist film 112 is removed by ashing, the etching stopper film 106 in the via hole 116 is removed to expose the surface of the lower layer wiring 104. Next, a first wiring resist film 118 and a second wiring resist film 120 are formed (FIG. 5A).

  Thereafter, using the second wiring resist film 120 as a mask, the first wiring resist film 118, the protective insulating film 110, the second interlayer insulating film 108b, and the second etching stop film 128 are selectively etched. Thus, the wiring trench 124 is formed. At this time, etching is performed through the second etching stopper film 128, and the surface of the first interlayer insulating film 108a is exposed at the bottom of the wiring trench 124 (FIG. 5B).

  Thereafter, the second wiring resist film 120 and the first wiring resist film 118 are removed by ashing such as oxygen plasma ashing to form upper layer wirings and vias 126 in the wiring grooves 124 (FIG. 5C). ).

  In this embodiment, when the wiring is formed by the dual damascene via first method, the lower layer wiring 104 is covered with the etching stopper film 106 when the via resist film 112 is removed. 104 surface can be protected. On the other hand, since it is not necessary to remove the etching stopper film 106 after forming the wiring pattern, the shape of the wiring pattern can be kept good. In particular, as described in this embodiment, when the etching stopper film 106 is removed with the surface of the interlayer insulating film 108 (or the first interlayer insulating film 108a) exposed at the bottom of the wiring trench 124, the etching stopper film 106 is removed. When etching is performed, the interlayer insulating film 108 (or the first interlayer insulating film 108a) may also be etched, and the wiring pattern shape may be deformed. However, in this embodiment, it is not necessary to remove the etching stopper film 106 after the wiring trench 124 is formed, so that the wiring pattern can be kept good.

  The present invention has been described based on the embodiments and examples. It is to be understood by those skilled in the art that the embodiments and examples are merely examples, and various modifications are possible and that such modifications are within the scope of the present invention.

  In the above embodiment, the example in which the lower layer wiring 104 is composed mainly of copper has been described. However, the lower layer wiring 104 can also be composed of tungsten, polysilicon, or the like. Even in such a case, if the surface of the lower layer wiring 104 is exposed when the via resist film 112 is removed, the lower layer wiring 104 may be damaged by the influence of plasma of plasma ashing. According to the present invention, such damage can be prevented and the yield of wiring can be improved.

  Furthermore, although the lower layer wiring 104 is shown as an example in the above embodiment, the present invention can also be applied to the case where a dual damascene structure wiring is formed on a via. That is, the present invention can be applied when the lower layer wiring 104 is a via.

  Further, in the above embodiment, the structure in which the protective insulating film 103 and the protective insulating film 110 are formed over the lower insulating film 102 and the interlayer insulating film 108 (or the second interlayer insulating film 108b), respectively, is shown. However, in the case where the lower insulating film 102 and the interlayer insulating film 108 are made of a material having CMP resistance, the semiconductor device 100 can be configured not to include the protective insulating film 103 and the protective insulating film 110.

It is a flowchart which shows the manufacture procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention. It is process sectional drawing which shows the other example of the manufacturing procedure of the semiconductor device in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Lower layer insulating film 103 Protective insulating film 104 Lower layer wiring 106 Etching blocking film 108 Interlayer insulating film 108a First interlayer insulating film 108b Second interlayer insulating film 110 Protective insulating film 111 Third etching blocking film 112 For via Resist film 116 Via hole 118 First wiring resist film 120 Second wiring resist film 124 Wiring groove 126 Upper wiring and via 128 Second etching blocking film 128

Claims (8)

Forming an etching stopper film on the lower conductive film formed on the semiconductor substrate;
Forming an insulating film on the etching stop film;
Forming a via resist film having a via pattern for forming vias connected to the lower conductive film on the insulating film;
Using the via resist film as a mask, selectively etching the insulating film to form a via hole in the insulating film;
Removing the via resist film;
Selectively etching the etch stop film using the insulating film as a mask to expose the lower conductive film in the via hole;
Forming a wiring resist film having a wiring pattern for forming a wiring groove connected to the via hole on the insulating film;
Using the wiring resist film as a mask, selectively etching the insulating film to form a wiring groove, and forming a dual damascene structure wiring pattern on the insulating film;
Removing the resist film for wiring;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein, in the step of removing the via resist film, the via resist film is removed by ashing. In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device in which the via hole is filled with a resist material in the step of forming the wiring resist film. In the manufacturing method of the semiconductor device in any one of Claim 1 to 3,
The step of forming the insulating film includes the step of forming a low dielectric constant film,
A method of manufacturing a semiconductor device, wherein, in the step of forming the wiring pattern, the low dielectric constant film is exposed at a bottom of the wiring groove. In the manufacturing method of the semiconductor device in any one of Claim 1 to 3,
The step of forming the insulating film includes a step of forming a first insulating film, a step of forming a second etching stopper film on the first insulating film, and a step of forming a second etching stopper film on the second etching stopper film. Forming a second insulating film,
In the step of forming the wiring pattern, the second insulating film and the second etching stop film are selectively etched using the wiring resist film as a mask to form the first insulating film at the bottom of the wiring groove. A method of manufacturing a semiconductor device in which a film is exposed. Providing a via hole for a via connecting the lower conductor and the upper conductor in the insulating layer between the lower conductor and the upper conductor using a resist layer selectively formed on the insulating layer as a mask; In a method for manufacturing a semiconductor device having
The via hole is formed by a dual damascene method, and after the via hole is formed partway, the resist layer is removed, and then the via hole is completed to expose a part of the surface of the lower conductor. And a method for manufacturing a semiconductor device, wherein a wiring trench is further formed thereafter. In the manufacturing method of the semiconductor device according to claim 6,
The insulating layer has an etching stopper film covering the lower conductor and an insulating film thereover, and the etching stopper film is selectively removed after removing the resist layer to complete the via hole Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 6,
The insulating layer covers a first etching blocking film covering the lower conductor, a first insulating film covering the blocking film, a second etching blocking film covering the insulating film, and the blocking film. A second insulating film, wherein the first etching stopper film is selectively removed after removing the resist layer, and the wiring trench penetrates the second insulating film and the second etching stopper film. A method of manufacturing a semiconductor device terminated in the middle of the first insulating film.

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