1353036 九、發明說明： 【發明所屬之技術領域】 本發明係有關於銅内連線半導體製程領域，特別是有關於一 種改良之銅雙鑲嵌(copperdual damascene)製程，特別是使用到金 屬遮罩層(metalhardmask)之雙鑲嵌製程，可以在介層洞與下層導 線的對不準情形發生時，避免由於糊蓋層而同時在下層導線旁 產生姓刻凹穴(recess)缺陷。 【先前技術】 如熟習該項技藝者所知，鑲嵌内連線技術已經是目前半導體 工業絲形成積體電路中銅導線的主流技術。簡言之，鑲嵌内連 線結構的製作方法’是先在介電材料薄膜上敍刻出電路圖案，然 後再將銅金屬填入這個圖案凹槽中，而依在介電材料薄膜上蝕刻 電路圖案的方式來區分，雙鑲嵌技術又可再細分為溝渠優先 _ (benchArst)製程、介層洞優先(via-first)、部分介層洞優先 (partial-via-fkst)以及自行對準(self_aUgned)等不同種類的製程。 "月參閱第1圖至第5圖’其纟會示的是習知技藝的部分介層洞 優先(partial-via-fkst)雙鑲嵌製程之剖面示意圖。首先，如第1圖所 示，基材1上具有一底層或低介電常數介電層1〇。在低介電常數 介電層10中形成有下層銅導線12，並且覆蓋有一蓋層Μ，通常 是摻雜氮的碳⑽(SiCN)。接著依序在蓋層14上形成低介電常數 介電層I6、石夕氧蓋層18、金屬遮罩層2〇以及底部抗反射層(b〇tt〇m 7 ’在底部抗反射層22上形 ’定義出鑲嵌導線之溝渠圖 anti_refleetiveeoating，BARC)22 〇 然後 成光阻圖案30,其具有一溝渠開口 & 案(trench pattern) 〇 如第2圖所示，接著進行一乾餘刻製程經由光阻圖案如的 、編口 32蝴金屬遮罩層20直到魏蓋層！8，藉此在金屬遮 罩層如中定義形成-溝渠凹口 ％前述的乾钮刻步驟一般停止在 夕氧蓋層18中接著，去除剩下的光阻圖案如以及底部抗反射 層22，暴露出剩下的金屬遮罩層2〇。 如第3圖所示’於基材丨上另沈積—底部抗反射層％，使底 :抗反射層38填滿溝渠凹口 36，並覆蓋在金屬遮罩層 20上。接 著’再於底部抗反射層38上形成—光阻圖案⑽，其具有一介層洞 開口 42 ’其位置恰好在溝渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影技術形成。接著，利用光阻圖案4〇作為触刻 遮罩’進行乾餘刻製程，經由介層洞開σ 42_底部抗反射層 38、矽氧蓋層18以及低介電常數介電層16,藉此在低介電常數介 電層16上半部形成部分介層洞via)46。 如第4圖所示，接著，利用氧氣電漿等方式去除剩下的光阻 圖案40以及底部抗反射層38，並且暴露出已定義有溝渠凹口 36 的金屬遮罩層20。 1353036 行-==示遮罩層2。作為_硬遮罩，進 18以及低八· 屬群層2G覆_的魏蓋層 形lit層16,直到暴露 =:以及部分介層洞46圖案轉移至低介電常數介 層_口66成雙鑲細❹，其包括—溝渠開口 ％以及-介 「21!圖所示，接著再_—爛製程，此步驟通常又稱為 曰除步騍(Liner ]1_讀」或「LRM步驟」，經由介層洞 =^，將暴露㈣蓋層M絲，藉以暴露出下相導線a。 接下來，就可以繼續進行上層銅導線的製作，如阻障層的沈積、 ^屬的f鍍等挪，不私外魏。前朗來錯歸Μ _ 厂私通常是採用含氫靴錢氣體電漿，例如ch2f2或者chf3 電漿。 然而，隨著積體電路中的關鍵線寬越來越小，雙鑲嵌開口 5〇 的介層测π 66與下層銅導線u發生對轉的航也可能會越 來越嚴重，如第7圖以及第8 _示’但是，當發生對不準的情 况’會造成最後it行蓋層Μ的侧時，一併侵钱到下層銅導線U 旁邊的低介電常數介電層1Q，碱不必要的凹穴8G，造成後續阻 =層並不易填人凹穴8〇,因而影響到積體電路的電性表現以及可 靠度。此外，使用含氫的氟烷類氣體電漿，例如CH2F2或者chF3 9 1353036 •電浆，來去除蓋層14驗刻製程往往同時會造成難以清除殘留物 •(有可能是電漿氣體與金屬遮罩層反應之有機金屬衍生物）。 在相關的先前技藝中，美國專利第6905968號披露了一種雙 鑲嵌製程以及選擇性蝕刻介電層的方法步驟(pr〇cess f〇r SELECTIVELYETCmNGDIELECTRICLA聰)，其主要是利用 NF3電漿或者CF4/N2電漿來侧疊設在TE〇s魏層或者氣推雜 φ石夕玻璃(FSG)上的碳氫摻雜(C，H-d〇ped)低介電常數石夕氧介電層 (k=2·5〜3) ’藉由νϊ?3電聚或者電漿對於下層TE〇s石夕氧層 •或者氟摻雜石夕玻璃的高钱刻選擇比，可以避免在上、下層介電/ .之間使用介電常數較高的餘刻停止層(通常為氮化梦）。然而，上述 .專麟於經由介層酬口所暴露出來的蓋層，則健教導以CH2F2 或CHF3電毅來去除’因此沒辦法解決殘留物的問題。 由上可知’在積體電路製造技術領域中確實需要一種改良之 •形成雙鑲嵌結構的方法，以改善這種由於對不準所導致的凹穴問 題以及去除蓋層14的侧製程所造成殘留物的現象。 【發明内容】 本發明之主要目的即在提供—種改良之雙鑲嵌製程方法可 以有效地驗上述習知鄕憎發生的問題。 • 根據本發明之較佳實施例’本發明提供-種鑲嵌製程，首先 10 k 1353036 • ^供基材’其具有_底層介電層、_形成在該底層介電層中之 ，下層導電層’以及一覆蓋住該下層導電層及該底層介電層的蓋 層，於該蓋層上沈積一介電層，於該介電層中蝕刻出一開口，暴 露出部分的該蓋’接著進行一襯墊層蝕除(L_製程，利用一四氟 化碳(CFO/三氟化氮(NF·3)氣體電漿，選擇性地蝕除經由該開口暴露 出來的該蓋層’以暴露出部分的該下料電層以及該底層介電 層，形成一介層洞開口，其中於該介層洞開口之底部，該下層導 φ 電層及該底層介電層之間的落差僅小於150埃。 根據本發明之較佳實施例，本發明提供一種雙鑲嵌製程，首 先提供一基材，其具有一底層介電層、一形成在該底層介電層中 之下層導電層’以及-覆蓋住該下層導電層及該底層介電層的蓋 層，再於該蓋層上沈積一介電層；再於該介電層上沈積一石夕氧層， 接著再於該矽氧層上形成一金屬硬遮罩，接著，於該金屬硬遮罩 及該矽氧層中蝕刻出一溝渠凹口，然後，經由該溝渠凹口，於該 • 矽氧層中以及該介電層中蝕刻出一部分介層洞開口，再將該溝渠 凹口以及該部分介層洞開口以蝕刻方式轉移至該介電層中，藉此 於該介電層形成一雙鑲嵌開口，包括一溝渠開口以及一介層洞開 口，其中該介層洞開口暴露出部分的該蓋層，最後，利用一四氟 化碳(CF4)/二氟化氮(nj?3)氣體電漿經由該介層洞開口钱除暴露出 來的該蓋層，以暴露出部分的該下層導電層以及該底層介電層。 • 本發明提供一種雙鑲嵌製程，首先提供一基材，其具有一底 11 1353036 .層介電層、一形成在該底層介電層中之下層導電I’以及一覆蓋 -住該下層導電層及該底層介電層的蓋層。接著於該蓋層上沈積一 介電層，再於該介電層上沈積一魏層，再於該石夕氧層上形成一 金屬硬遮罩’接著於該金屬硬遮罩中形成一溝渠凹口，然後，經 由該溝渠凹口，钱刻該石夕氧層與該介電層，形成一介層洞開口， 使其暴露出料的該蓋層，最後，進行一襯塾層錯(lrm)製程， 利用-不含氫的氟絲航合—含氮氣體電漿，選雜地錄經 #由該介層洞開口暴露出來的該蓋層，以暴露出部分的該下層導電 層以及該底層介電層。 本伽提供-種鑲嵌鱗線結構，包含有—紐，其具有一 底層介電層，-下層導，形成在該底層介電射一蓋層， •覆蓋在該下料電層及域層介電層上，—介，於該蓋層曰上， -介層洞開口’形成於該介電層與該蓋層中，其與 •並未對準(misaligned)，因而暴露出部分的該下層導電“該底; .介電層，-金屬阻障層，覆蓋於該介層洞開口之内壁上並且覆蓋 該暴露出來_下層導電層蘭介電層，以及―銅金屬層， 在該金屬阻障層上，並填滿該介層洞開口。 —為了使貴審查委員能更進-步了解本發明之特徵及技術内 谷，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與輔助說明用，並非用來對本發明加以限制者。 12 1353036 【實施方式】 . π參閱第9 ®至第17圖’其％示的是本發明較佳實施例雙鑲 欣製程之剖面示意圖’其令仍沿用相同的符號來代表相同或類似 的元件或區域。需強調的是，本發明可以應用在溝渠優先 (trench-first)、介層洞優先(via彻)、部分介層洞優先㈣&丨仏彻) 等鑲嵌製程中，並不僅限於圖式中所揭露者。 φ 如第9圖所示，基材1同樣提供有-底層或低介電常數介電 層10。在低介電常數介電層10中形成有下層銅導線12，並且覆 •蓋有-蓋層Μ。根據本發明之較佳實施例，蓋層14係以換雜乳的 碳化石夕(SiCN)為其成分，厚度約為3〇〇至8〇〇埃(angstr〇m)，較佳 約為500埃左右。但蓋層丨4亦可以是其它的材料，例如，氮化矽 (SiN)、氮氧化石夕(Si〇N)、碳化石夕(SiC)、碳氧化石夕(Sic〇)等。 接著，依序在蓋層14上形成低介電常數介電層16、1^〇8矽 籲氧蓋層118、金屬遮罩層2〇以及底部抗反射層22。根據本發明之 較佳實施例，金屬遮罩層20以氮化鈦(TiN)為其成分，但不限於 此，亦可以使用氮化鈕(TaN)等其它金屬。金屬遮罩層2〇的厚度 約介於250至450埃之間，較佳介於3〇〇至35〇埃之間。 根據本發明之較佳實施例，低介電常數介電層1〇、16可以是 具有有機矽酸鹽玻璃(organosilicate glass，OSG)等成分，這類有機 矽酸鹽玻璃係在二氧化矽或氧化矽中摻入碳或氫原子，使其具有 13 1353036 約介於2至3之間的低介電常數值。適合作為低介電常數介電層 10、16成分，例如應用材料(Applied Materials)公司的Black Diamond™系列或者Novellus公司的CORAL™等等。根據本發明 之較佳實施例，低介電常數介電層16的厚度約介於2500至4500 埃之間，較佳介於3000至3500埃之間。 根據本發明之較佳實施例，TEOS矽氧蓋層118可利用電漿加 強化學氣相沈積(plasma-enhanced chemical vapor deposition， _ PECVD)技術所沈積而成’具有較低碳含量，其中使用到四乙基氧 矽烷(tetraethylorthosilicate，TEOS)作為前驅物以及氧氣，且採用比 較高的氧氣對TEOS比值(O/TEOS ratio)。 « 根據本發明之較佳實施例，具有較低碳含量的TEOS矽氧蓋 層118其沈積可以利用以下的製程條件完成··壓力介於3至8托 耳’較佳約為5托耳；製程溫度在1〇〇至450°C之間，較佳在350 鲁 至之間；高頻無線電波功率(high-frequency RF power)約為 200至350瓦特，較佳在250至300瓦特之間，而在280瓦特最佳， 且持續提供約25秒左右；低頻無線電波功率(l〇w-frequency RF power)約為30至70瓦特，較佳在40至60瓦特之間，而在50瓦 特最佳；TEOS前驅物流量約為〇.2gm至5gm ;載氣使用氦氣，而 流量介於7500至9500 seem ’較佳為8500至9000 seem ;氧氣流 * 量介於 5000 至 10000 seem，較佳為 8000 seem。 ^53036 如第10圖所示，接下來在底部抗反射層22上形成一光阻圖 一 〇其具有一溝渠開口 32,定義出鑲嵌導線之溝渠圖案。 接著，如第11圖所示，進行一乾姓刻製程，經由光阻圖案3〇 的溝渠開口 32蝕刻金屬遮罩層20直到TE0S矽氧蓋層U8，藉此 形成一溝渠凹口 36 ^前述乾蝕刻停止在TEOS矽氧蓋層118中。 接著，利用氧氣電漿等方式去除剩下的光阻圖案3〇以及底部抗反 射層22。 如第12圖所示，然後於基材〗上沈積另一底部抗反射層兇， 且使底。卩抗反射層38填滿溝渠凹口 36。接著，再於底部抗反射層 38上形成一光阻圖案40’其具有一介層洞開口 42，其位置恰好在 溝渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影 技術形成。 如第13圖所示’接著利用光阻圖案40作為蝕刻硬遮罩，進 行一乾姓刻製程’經由介層洞開口 42依序向下蝕刻底部抗反射層 38、TEOSi夕氧蓋層118以及低介電常數介電層16，藉此在低介 電常數介電層16上半部形成部分介層洞46。 接著’如第14圖所示，利用氧氣電漿等方式去除剩下的光阻 圖案40以及底部抗反射層38。另外，亦可以使用h2/N2或 電漿來去除光阻圖案4〇以及底部抗反射層38。 15 1353036 行-2 15圖所示’再利用金屬遮罩層20作輕刻硬遮罩，進 ^刻製程，向下侧未被金屬遮罩層2〇覆蓋到的则石夕 ^8以及低介電常數介電層16，並經由部分介層祕繼續 電常數_ 16，直到暴_分_ μ，藉此將先 溝3“及料介相*轉輕齡電常數介電 θ ，形缝鑲嵌開口 5G，其包域關口 56錢介層洞開 口 66 〇 如第16圖所示’接著再利用一餘刻製程，經由介層洞開口 • 66 ’選擇性地將暴露出的蓋層14去除，藉以暴露出下層銅導線 12 ’但不會傷害到下層銅導線12旁邊的低介f f數介電層ι〇，因 此’不會形成不必要的凹穴。 根據本發明之較佳實施例，前述用來去除蓋層14的蝕刻製程 • 是採用不含氫的氟烷氣體，例如四氟化碳(CFO，以及一含氮氣體， 例如三氟化氮(NF3) ’所形成的混合氣體電激，其流量比例較佳約 為3:1，舉例來說，四氟化碳的流量可以是15〇sccm，三氟化氮約 為50 seem。根據本發明之較佳實施例’利用四氟化碳(eh)/二氣 化氮(NF3)所形成的電漿來去除蓋層14可以提供高的選擇比，使得 暴露出的蓋層14可以很快的被去除，而不會明顯餘刻在蓋芦μ ' 下方的低介電常數介電層10，如此一來’即可以解決介層祠開口 ， 66與下層銅導線12對不準的問題。 1353036 此外，經過實驗驗證發現，若單單使用四氟化碳電聚，而不 使用二氟化氛來侧暴露出的蓋層14，雖然可以解決殘留物的問 題，但是其選擇比差’因此，健會有_凹穴形成在下層銅導 線12旁邊。由此可知，要避免飯刻凹穴產生，仍需配合三氣化氣 的使用。二氟化氮可以在银刻到低介電常數介電層1〇時，同時於 低介電常數介電層10表面上形成-薄的保護膜，因而能夠降低其 触刻速率。 根據本發明之其它較佳實施例，去除蓋層14的蝕刻氣體亦可 .以使用包括四氣化碳氧化氮、四氟化碳/二氧化氮、四氟化碳/ 氮氣等。但是四氟化碳/氨氣的組合則較不建議使用，這是因為氨 • 氣巾含有氫原子’可能在侧過程會產生不必要且難以清除的殘 留物。 • 接下來，繼續進行上層銅導線的製作，如阻障層的沈積、銅 金屬的電錄、化學機械研磨等步驟，形成如第17圖所示之雙鎮嵌 導線、.’。構1GG其包括覆蓋在溝渠開σ 以及介層;明口 66表面 的阻障層82、喪入在溝渠開口 56中的上層銅導線％以及嵌入在 介層洞開口 66的介層插塞96。最後，再於雙鑲嵌導線結構卿 以及低介電常數介電層表面上沈積一蓋層1〇4，例如推雜氮 ,的碳化石夕、碳化石夕、或氮化石夕等。其中’阻障層可以是欽、氮化 ，欽、担、氣化叙，或以上組合。 17 1353036 . 第18圖繪示的是第17圖中雙鑲嵌導線結構100的介層插塞 %與下層銅導線丨2之間界面的放大剖面示意圖。如s 圖所示， 本發月特適合應用在當介層洞開口 66與下層銅導線12發生對 =準的情況’而造成介層插塞96其有-部份必鮮在低介電常數 介電層10的表面上。因此，本發明在結構上的特徵是經由介層洞 66蝕刻掉暴露出的蓋層14後，由於使用高選擇比的四氣化碳/三 φ 氟化氮電漿，故不會明顯蝕刻低介電常數介電層10，僅有非常少 的低介電常數介電層10會被錄，形成一低於下層銅導線12上 表面的輕微下陷區域110,但是此輕微下陷區域11〇與下層銅導線 -12上表面之間的落差d可被控制在小於15〇埃内，落差d甚至可 控制在50埃内，因此不會影響到後續阻障層的沈積。實際的sem 照片’如第19圖所示。 以上所述僅林發明之較佳實施例，凡依本㈣申請專利範 • 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖繪示的是習知技藝的部分介層洞優先 (partial-via-first)雙鑲嵌製程之剖面示意圖。 第7圖及第8圖繪示的是介層洞與下層金屬導線對不準的情形。 ，第9圖至第17圖繪示的是本發明較佳實施例雙鎮嵌製程之剖面示 . 意圖。 ’ 1353036 第18圖繪示的是第17圖中雙鑲嵌導線結構100的介層插塞96與 下層銅導線12之間界面的放大剖面示意圖。 第19圖是本發明較佳實施例之SEM照片。 【主要元件符號說明】1353036 IX. Description of the Invention: Technical Field of the Invention The present invention relates to the field of copper interconnect semiconductor manufacturing, and more particularly to an improved copper dual damascene process, particularly to a metal mask layer. (metalhardmask) The dual damascene process can avoid the occurrence of a defect in the lower side of the underlying conductor due to the misalignment of the via hole and the underlying conductor. [Prior Art] As is well known to those skilled in the art, the damascene interconnect technology has been the mainstream technology for forming copper wires in semiconductor integrated circuits. In short, the method of fabricating the interconnect structure is to first pattern the circuit on the dielectric material film, then fill the copper metal into the pattern recess, and etch the circuit on the dielectric material film. The way the pattern is distinguished, the dual damascene technique can be subdivided into a trench-first (benchArst) process, a via-first, a partial-via-fkst, and a self-alignment (self_aUgned). ) and other different types of processes. "Monthly Referring to Figs. 1 to 5, the following is a schematic cross-sectional view of a partial-via-fkst dual damascene process of the prior art. First, as shown in Fig. 1, the substrate 1 has an underlying or low-k dielectric layer 1〇. A lower copper wire 12 is formed in the low dielectric constant dielectric layer 10 and covered with a cap layer, typically nitrogen-doped carbon (10) (SiCN). Then, a low-k dielectric layer I6, a rock mask layer 18, a metal mask layer 2, and a bottom anti-reflection layer (b〇tt〇m 7 ' in the bottom anti-reflection layer 22) are sequentially formed on the cap layer 14. The upper shape defines a trench pattern of the inlaid wire anti_refleetiveeoating, BARC 22 and then forms a photoresist pattern 30 having a trench pattern and a trench pattern, as shown in FIG. 2, followed by a dry-end process via The photoresist pattern, such as the braided surface 32, is covered with a metal mask layer 20 until the Wei cover layer! 8, thereby defining the formation-ditch recess in the metal mask layer, as described above. The dry buttoning step described above generally stops in the oxide cap layer 18, and the remaining photoresist pattern, such as the bottom anti-reflective layer 22, is removed. The remaining metal mask layer 2 暴露 is exposed. As shown in Fig. 3, the other portion of the bottom anti-reflective layer is deposited on the substrate, so that the bottom: anti-reflective layer 38 fills the trench recess 36 and covers the metal mask layer 20. Next, a photoresist pattern (10) is formed on the bottom anti-reflective layer 38, which has a via opening 42' which is positioned just above the trench recess 36. The via opening 42 described above is formed using conventional lithography techniques. Then, the photoresist pattern 4 is used as a etch mask to perform a dry-cut process, and the σ 42_ bottom anti-reflection layer 38, the germanium oxide cap layer 18, and the low-k dielectric layer 16 are opened through the via hole. A partial via 46 is formed in the upper half of the low-k dielectric layer 16. As shown in Fig. 4, the remaining photoresist pattern 40 and the bottom anti-reflective layer 38 are then removed by means of oxygen plasma or the like, and the metal mask layer 20 in which the trench recess 36 has been defined is exposed. 1353036 Line -== shows mask layer 2. As a _hard mask, enter the 18 and the lower octal layer 2G over the _ of the Wei cover layered lit layer 16 until the exposure =: and part of the via hole 46 pattern is transferred to the low dielectric constant layer _ mouth 66 Double inlays, including - ditch opening % and - "21! Figure, followed by _ - rotten process, this step is often referred to as the "Liner 1_Read" or "LRM step" Through the via hole = ^, the (four) capping M wire will be exposed to expose the lower phase wire a. Next, the fabrication of the upper copper wire, such as the deposition of the barrier layer, the f plating of the genus, etc., can be continued. Move, not private Wei. The former lang is wrongly blamed _ Factory is usually using hydrogen-based boots gas plasma, such as ch2f2 or chf3 plasma. However, with the key line width in the integrated circuit is getting smaller and smaller The double-inlaid opening 5〇 layer measurement π 66 and the lower layer copper wire u may also become more and more serious, such as Figure 7 and the eighth _ show 'but, when the occurrence of the misalignment' Will cause the last side of the cover layer to smash, and invade the low dielectric constant dielectric layer 1Q next to the lower copper wire U, the alkali unnecessary hole 8G , causing the subsequent resistance = layer is not easy to fill the pocket 8 〇, thus affecting the electrical performance and reliability of the integrated circuit. In addition, the use of hydrogen-containing halothane gas plasma, such as CH2F2 or chF3 9 1353036 • electricity Slurry, to remove the cap layer 14 inspection process often causes difficulty in removing residues • (may be an organometallic derivative of the plasma gas reacting with the metal mask layer). In related prior art, US Patent No. 6905968 No. discloses a dual damascene process and a method step of selectively etching a dielectric layer (pr〇cess f〇r SELECTIVELYETCmNGDIELECTRICLA), which mainly uses NF3 plasma or CF4/N2 plasma to be stacked on top of TE〇s Wei Hydrocarbon doping (C, Hd〇ped) low dielectric constant on the layer or gas-pushing φ Shixi glass (FSG) (k=2·5~3) 'by νϊ?3 The electropolymerization or plasma can be used to avoid the high dielectric constant between the upper and lower layers of the dielectric layer for the lower TE〇s stone oxide layer or the fluorine doped stone glass. Stop layer (usually a dream of nitriding). However, the above-mentioned. The exposed cap layer is taught to be removed by CH2F2 or CHF3. Therefore, there is no way to solve the problem of residue. It can be seen from the above that there is indeed a need for improvement in the field of integrated circuit manufacturing technology. The method is to improve the phenomenon of the residue caused by the inaccuracy caused by the misalignment and the side process of removing the cap layer 14. SUMMARY OF THE INVENTION The main object of the present invention is to provide an improved dual damascene The process method can effectively solve the problems occurring in the above-mentioned conventional problems. • According to a preferred embodiment of the present invention, the present invention provides an inlay process, first 10 k 1353036 • ^ for a substrate having a _ underlying dielectric layer Forming a lower conductive layer ′ in the underlying dielectric layer and a cap layer covering the underlying conductive layer and the underlying dielectric layer, and depositing a dielectric layer on the cap layer Etching an opening, exposing a portion of the lid' followed by a liner etch (L_process, using a carbon tetrafluoride (CFO/nitrogen trifluoride (NF·3) gas plasma, selective Ground erosion through the opening Exposing the cap layer 'to expose a portion of the underlying electrical layer and the underlying dielectric layer to form a via opening, wherein the lower conductive layer and the underlying layer are at the bottom of the via opening The drop between the electrical layers is only less than 150 angstroms. According to a preferred embodiment of the present invention, the present invention provides a dual damascene process, first providing a substrate having an underlying dielectric layer, a lower conductive layer formed in the underlying dielectric layer, and covering the a lower conductive layer and a cap layer of the underlying dielectric layer, and then depositing a dielectric layer on the cap layer; depositing a rock oxide layer on the dielectric layer, and then forming a metal hard layer on the germanium oxide layer a mask, and then etching a trench recess in the metal hard mask and the germanium oxide layer, and then etching a portion of the via in the germanium oxide layer and the dielectric layer through the trench recess a trench opening, and the trench recess and the portion of the via opening are etched into the dielectric layer, thereby forming a dual damascene opening in the dielectric layer, including a trench opening and a via opening. Wherein the via opening exposes a portion of the cap layer, and finally, the silicon tetrafluorocarbon (CF4)/nitrodifluoride (nj?3) gas plasma is exposed through the via hole opening a cap layer to expose a portion of the underlying conductive layer and the The underlying dielectric layer. The present invention provides a dual damascene process, first providing a substrate having a bottom 11 1353036. A dielectric layer, a lower layer of conductive I' formed in the underlying dielectric layer, and a covering-holding the lower conductive layer And a cap layer of the underlying dielectric layer. And depositing a dielectric layer on the cap layer, depositing a Wei layer on the dielectric layer, and forming a metal hard mask on the Xiyang oxygen layer, and then forming a trench in the metal hard mask. a recess, and then, through the trench recess, the engraved layer and the dielectric layer form a via opening to expose the capping layer, and finally, a lining fault (lrm a process, using a hydrogen-free fluoridation-nitrogen-containing plasma, selecting the cover layer exposed by the via opening to expose a portion of the underlying conductive layer and the The underlying dielectric layer. The gamma provides a mosaic scale structure comprising a button, a bottom dielectric layer, a lower layer conductor formed on the underlying dielectric layer, and a cover layer covering the lower layer and the domain layer On the electrical layer, on the cap layer, a via opening is formed in the dielectric layer and the cap layer, which is misaligned, thereby exposing a portion of the lower layer Conductive "the bottom; a dielectric layer, a metal barrier layer overlying the inner wall of the via opening and covering the exposed lower layer conductive layer blue dielectric layer, and a "copper metal layer" The barrier layer is filled with the via opening. - In order to enable the reviewing committee to further understand the features and technical valleys of the present invention, please refer to the following detailed description and drawings relating to the present invention. The drawings are for reference and auxiliary explanation only, and are not intended to limit the invention. 12 1353036 [Embodiment] π Referring to Figures 9 to 17 '% shows the preferred embodiment of the present invention A schematic cross-section of the process, which still uses the same symbols to represent the same or Component or region. It should be emphasized that the present invention can be applied to a damascene-first, via-first, and a via-first (four) & Not limited to those disclosed in the drawings. φ As shown in Fig. 9, the substrate 1 is also provided with a bottom layer or a low-k dielectric layer 10. A lower copper conductor is formed in the low-k dielectric layer 10. 12, and covered with a cover layer. According to a preferred embodiment of the present invention, the cover layer 14 is made of carbonized stone (SiCN) of the milk-changing milk, and has a thickness of about 3 〇〇 to 8 〇〇. Angstrom (angstrom), preferably about 500 angstroms, but the cap layer 丨4 may also be other materials, such as tantalum nitride (SiN), arsenic oxynitride (Si〇N), carbonized stone eve ( SiC), carbon oxycarbide, etc. Next, a low-k dielectric layer 16, a capping layer 118, a metal mask layer 2, and a metal mask layer are formed on the cap layer 14 in this order. The bottom anti-reflection layer 22. According to a preferred embodiment of the present invention, the metal mask layer 20 is made of titanium nitride (TiN), but is not limited thereto, and a nitride button (TaN) or the like may also be used. The metal mask layer 2 has a thickness of between about 250 and 450 angstroms, preferably between about 3 angstroms and about 35 angstroms. According to a preferred embodiment of the invention, the low-k dielectric layer 1 〇, 16 may be an organic silicate glass (OSG) component, such an organic bismuth silicate glass is doped with carbon or hydrogen atoms in cerium oxide or cerium oxide to have a 13 1353036 A low dielectric constant value between 2 and 3. Suitable as a low dielectric constant dielectric layer 10, 16 component, such as Applied Materials' Black DiamondTM series or Novellus' CORALTM, and the like. In accordance with a preferred embodiment of the present invention, the low-k dielectric layer 16 has a thickness between about 2,500 and 4,500 angstroms, preferably between 3,000 and 3,500 angstroms. According to a preferred embodiment of the present invention, the TEOS oxide cap layer 118 can be deposited by plasma-enhanced chemical vapor deposition (_PECVD) technology to have a lower carbon content, wherein Tetraethylorthosilicate (TEOS) is used as a precursor and oxygen, and a relatively high oxygen to OOS ratio (O/TEOS ratio) is used. « According to a preferred embodiment of the present invention, the deposition of the TEOS oxime cap layer 118 having a lower carbon content can be accomplished using the following process conditions: • The pressure is between 3 and 8 Torres, preferably about 5 Torr; The process temperature is between 1 〇〇 and 450 ° C, preferably between 350 Torr; the high-frequency RF power is between 200 and 350 watts, preferably between 250 and 300 watts. , at 280 watts, and lasts for about 25 seconds; low frequency radio power (l〇w-frequency RF power) is about 30 to 70 watts, preferably between 40 and 60 watts, and at 50 watts. Best; TEOS precursor flow rate is about 2.2gm to 5gm; carrier gas uses helium, and flow rate is between 7500 and 9500 seem' is preferably 8500 to 9000 seem; oxygen flow* is between 5000 and 10000 seem, compared Good for 8000 seem. ^53036 As shown in Fig. 10, a photoresist pattern is formed on the bottom anti-reflective layer 22, which has a trench opening 32 defining a trench pattern of the damascene. Next, as shown in FIG. 11, a dry etching process is performed to etch the metal mask layer 20 through the trench opening 32 of the photoresist pattern 3 to the TE0S oxide cap layer U8, thereby forming a trench recess 36. The etch stops in the TEOS oxime cap layer 118. Next, the remaining photoresist pattern 3 and the bottom anti-reflection layer 22 are removed by means of oxygen plasma or the like. As shown in Fig. 12, another bottom anti-reflective layer is then deposited on the substrate to make the bottom. The anti-reflective layer 38 fills the trench recess 36. Next, a photoresist pattern 40' is formed on the bottom anti-reflective layer 38, which has a via opening 42, which is located just above the trench recess 36. The via opening 42 described above is formed using conventional lithography techniques. As shown in FIG. 13, 'the photoresist pattern 40 is then used as an etched hard mask, and a dry etching process is performed." The bottom anti-reflective layer 38, the TEOSi oxide cap layer 118, and the lower portion are sequentially etched down via the via opening 42. The dielectric layer 16 is dielectric constant, thereby forming a portion of the via 46 in the upper half of the low-k dielectric layer 16. Next, as shown in Fig. 14, the remaining photoresist pattern 40 and the bottom anti-reflection layer 38 are removed by means of oxygen plasma or the like. Alternatively, h2/N2 or plasma may be used to remove the photoresist pattern 4 and the bottom anti-reflective layer 38. 15 1353036 Line-2 15 Figure 'Reuse the metal mask layer 20 for light-cut hard mask, enter the engraving process, the lower side is not covered by the metal mask layer 2〇, then Shi Xi ^8 and low Dielectric constant dielectric layer 16, and through the partial layer secrets continue electrical constant _ 16, until the storm _ minute _ μ, thereby the first groove 3 "and the material phase * to the light age electrical constant dielectric θ, shape seam Inlaid opening 5G, with a pocket opening 56, a dielectric opening 66, as shown in Fig. 16, 'and then using a etch process to selectively remove the exposed cap layer 14 through the via opening 66' Thereby, the underlying copper wire 12' is exposed but does not damage the low dielectric layer ι 旁边 next to the underlying copper wire 12, so 'unnecessary pockets are not formed. According to a preferred embodiment of the invention, The etching process for removing the cap layer 14 is a mixed gas gas formed by using a hydrogen-free halothane gas such as carbon tetrafluoride (CFO, and a nitrogen-containing gas such as nitrogen trifluoride (NF3). Excited, the flow ratio is preferably about 3:1. For example, the flow rate of carbon tetrafluoride can be 15 〇sccm, and the trifluoride About 50 seem. According to a preferred embodiment of the present invention, the use of a plasma formed of carbon tetrafluoride (eh) / nitrogen dioxide (NF3) to remove the cap layer 14 can provide a high selectivity ratio, such that it is exposed. The cap layer 14 can be quickly removed without significantly engraving the low-k dielectric layer 10 under the cover, so that the interlayer opening, 66 and the underlying copper wire can be solved. 12 pairs of inaccuracies. 1353036 In addition, it has been experimentally verified that if the carbon tetrachloride is used alone, instead of using the difluorinated atmosphere to expose the cover layer 14 sideways, although the problem of residue can be solved, The choice ratio is poor. Therefore, the pocket is formed next to the lower copper wire 12. It can be seen that to avoid the generation of the pocket, it is still necessary to cooperate with the use of the three gas. Nitrogen fluoride can be used in silver. When the low-k dielectric layer is engraved, a thin protective film is formed on the surface of the low-k dielectric layer 10, thereby reducing the etch rate. According to other preferred embodiments of the present invention, The etching gas for removing the cap layer 14 can also be used to include four gasification. Nitric oxide, carbon tetrafluoride / nitrogen dioxide, carbon tetrafluoride / nitrogen, etc. But the combination of carbon tetrafluoride / ammonia is less recommended, because ammonia • air towel contains hydrogen atoms 'may be on the side The process produces residues that are unnecessary and difficult to remove. • Next, proceed with the fabrication of the upper copper wire, such as the deposition of the barrier layer, the electro-recording of copper metal, chemical mechanical polishing, etc., as shown in Figure 17. The double-inlaid wire, the '1' structure includes the cover layer σ and the interlayer; the barrier layer 82 on the surface of the open mouth 66, the upper layer of the copper wire that is buried in the trench opening 56, and the embedded layer in the via hole a via plug 96 of the opening 66. Finally, a cap layer 1 〇 4 is deposited on the surface of the dual damascene conductor structure and the low-k dielectric layer, such as a carbon-immobilized carbon stone, a carbonized stone, Or nitrite eve. The barrier layer can be Qin, Nitriding, Qin, Dan, Qihua, or a combination of the above. 17 1353036 . Figure 18 is a schematic enlarged cross-sectional view showing the interface between the dielectric plug % of the dual damascene conductor structure 100 and the lower copper conductor 2 in Fig. 17. As shown in the s diagram, this month is particularly suitable for applications where the via hole opening 66 and the underlying copper wire 12 are in the opposite state, and the via plug 96 has a portion that must be fresh in the low dielectric constant. On the surface of the dielectric layer 10. Therefore, the structural feature of the present invention is that after the exposed cap layer 14 is etched through the via hole 66, it is not significantly etched low due to the use of a high selectivity ratio of four gasified carbon/tri-φ fluorinated nitrogen plasma. With the dielectric constant dielectric layer 10, only a very small low-k dielectric layer 10 is recorded, forming a slightly depressed region 110 lower than the upper surface of the lower copper conductor 12, but this slightly depressed region 11〇 and the lower layer The drop d between the upper surfaces of the copper wires 12 can be controlled to be less than 15 angstroms, and the drop d can be controlled even within 50 angstroms, thus not affecting the deposition of the subsequent barrier layer. The actual sem photo is shown in Figure 19. The above-mentioned preferred embodiments of the invention are only applicable to the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 6 are schematic cross-sectional views showing a partial-via-first dual damascene process of the prior art. Fig. 7 and Fig. 8 show the case where the via hole and the underlying metal wire are misaligned. 9 to 17 are cross-sectional views showing a double-town embedded process of a preferred embodiment of the present invention. Figure 1353036 is an enlarged cross-sectional view showing the interface between the via plug 96 and the underlying copper trace 12 of the dual damascene conductor structure 100 of Fig. 17. Figure 19 is a SEM photograph of a preferred embodiment of the present invention. [Main component symbol description]
1 基材 12 下層銅導線 16 低介電常數介電層 20 金屬遮罩層 30 光阻圖案 36 溝渠凹口 40 光阻圖案 46 部分介層洞 56 溝渠開口 80 凹穴 86 上層銅導線 100 雙鎮嵌導線結構 110 輕微下陷區域 10 低介電常數介電層 14 蓋層 18 矽氧蓋層 22 底部抗反射層 32 溝渠開口 38 底部抗反射層 42 介層洞開口 50 雙鑲嵌開口 66 介層洞開口 82 阻障層 96 介層插塞 104 蓋層 118 TEOS矽氧蓋層 191 Substrate 12 Lower copper wire 16 Low-k dielectric layer 20 Metal mask layer 30 Resistive pattern 36 Ditch recess 40 Photoresist pattern 46 Partial via hole 56 Ditch opening 80 Pocket 86 Upper copper wire 100 Double town Embedded conductor structure 110 Slightly depressed area 10 Low-k dielectric layer 14 Cover layer 18 Oxygen cap layer 22 Bottom anti-reflection layer 32 Ditch opening 38 Bottom anti-reflection layer 42 Via opening 50 Double damascene opening 66 Interlayer opening 82 barrier layer 96 via plug 104 cap layer 118 TEOS oxide cap layer 19