200830461 九、發明說明： ^ 【發明所屬之技術領域】 本發明係有關於銅内連線半導體製程領域，特別是有關於一 種改良之銅雙鑲嵌(copper dual damascene)製程，特別是使用到金 屬遮罩層(metalhardmask)之雙鑲嵌製程，可以在介層洞與下層導 線的對不準情形發生時，避免由於蝕刻蓋層而同時在下声導線旁 產生敍刻凹穴(recess)缺陷。 【先前技術】 如熟習該項技藝者所知，鑲嵌内連線技術已經是目前半導體 工業用來形成積體電路中銅導線的主流技術。簡言之，鑲嵌内連 線結構的製作方法，是綠介電材料_上_出電路圖案，然 後再將銅金屬填入這個圖案凹槽中，而依在介電材料薄膜上蝕刻 電路圖案的方式來區分，雙鑲嵌技術又可再細分為溝渠優先 (teich-first)製程、介層洞優先(via_flrst)、部分介層洞優先 (partial_via_flrst)以及自行對準(selMigned)等不同種類的製程。 請參閱第1圖至第5圖，其緣示的是習知技藝的部分介層洞 優先(partial-via-first)雙鑲嵌製程之剖面示意圖。首先，如第}圖所 不，基材1上具有-底層或低介電常數介錢1G。在低介電常數 ”電層10中形成有下層銅導線12，並且覆蓋有一蓋層14，通常 是摻雜氮的碳化石夕(SiCN)。接著依序在蓋層14上形成低介電常數 ;ι電層16、石夕氧蓋層18、金屬遮罩層2〇以及底部抗反射層(b〇tt〇m 7 200830461 ，邊-⑽ating，BARC)22。然後，在底部抗反射層22上形 成光阻圖案30,其具有一溝渠開口 32,定義出镶散導線之溝渠圖 案(trench pattern) 〇 如第2圖所tf ’接著進行—乾敍刻製程，經由光阻圖案3〇的 溝渠開口 32蚀刻金屬遮罩層2〇直到石夕氧蓋層18，藉此在金屬遮 罩層T中定義形成一溝渠凹口 36。前述的乾侧步驟一般停止在 料盍層18中。接著’去除剩下的光阻圖案3q以及底部抗反射 層22 ’暴露出剩下的金屬遮罩層2〇。 如第3圖所不，於基材i上另沈積一底部抗反射層％ ,使底 舰反射層38填滿溝渠凹口 36，並覆蓋在金屬遮罩層2()上。接 著，再於底部抗反射層38上形成一光阻圖案4〇,其具有一介層洞 開口 42’其位置恰好在溝渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影技娜成。接著，利用光阻赌4()作為侧 遮罩’進仃乾侧製程，經由介層洞開口 42蚀刻底部抗反射層 38、矽氧蓋層18以及低介電常數介電層16，藉此在低介電常數介 電層16上半部形成部分介層洞(partial via)46。 如第4 _示’接著’ _氧氣電料方紅_下的光阻 圖案40以及底部抗反射層38，並且暴露出已定義有溝渠凹口弘 • 的金屬遮罩層20。 8 200830461 —T第5圖所示，接著利用金屬遮罩層2〇作為钱刻硬遮罩，進 打-乾蝴餘’向下侧未被金屬鮮層Μ覆朗⑽氧蓋層 18 乂及低電系數介電層16，並同時經由部分介層洞繼續蝕 刻低介電常數介電層’朗暴露$部分的蓋層Μ，藉此將先前 形成的溝渠凹口 36以及部分介制46 _轉移至低介電常數介』 電層16巾’形成雙鑲嵌開口 5〇，其包括一溝渠開口兄以及—介 層洞開口 66。 ^ 如第6圖所示’接著再糊製程，此步驟通常又稱為 「襯墊層蝕除步驟(LinerRemoval)」或「L騰步驟」，經由介層洞 開口 66 ’將暴露出的蓋層14去除，藉以暴露出下層銅導線η。 接下來’就可以繼續進行上層銅導線的製作，如阻障層的沈積、 銅金屬的電鍍等步驟，不再另外贅述，述用來絲蓋層m的敍 刻製程通常是採用含氫的氟炫類氣體賴，例如CH2F2或者咖 電漿。 3200830461 IX. INSTRUCTIONS: ^ Technical Field of the Invention The present invention relates to the field of copper interconnect semiconductor manufacturing, and more particularly to an improved copper dual damascene process, particularly to metal masking. The double damascene process of the metal hard mask can avoid the occurrence of a recess defect near the lower acoustic conductor due to the etching of the cap layer when the misalignment of the via hole and the underlying conductor occurs. [Prior Art] As is well known to those skilled in the art, the damascene interconnect technology has been the mainstream technology used by the semiconductor industry to form copper wires in integrated circuits. In short, the method of fabricating the interconnected interconnect structure is a green dielectric material_up_out circuit pattern, and then copper metal is filled into the pattern recess, and the circuit pattern is etched on the dielectric material film. By way of distinction, the dual damascene technique can be further subdivided into different types of processes such as teich-first process, via-first (via_flrst), partial via-first (partial_via_flrst), and self-aligned (selMigned). Referring to Figures 1 through 5, there is a schematic cross-sectional view of a partial-via-first dual damascene process of the prior art. First, as shown in the figure, the substrate 1 has a bottom layer or a low dielectric constant of 1 G. An underlying copper wire 12 is formed in the low dielectric constant electrical layer 10 and is covered with a cap layer 14, typically a nitrogen-doped carbon carbide (SiCN). A low dielectric constant is then formed on the cap layer 14 in sequence. ; the electric layer 16, the stone oxide layer 18, the metal mask layer 2, and the bottom anti-reflection layer (b〇tt〇m 7 200830461, edge-(10) ating, BARC) 22. Then, on the bottom anti-reflection layer 22 Forming a photoresist pattern 30 having a trench opening 32 defining a trench pattern of the inlaid conductive line, such as tf in FIG. 2, followed by a dry-etching process, through the trench opening of the photoresist pattern 3 32 etching the metal mask layer 2 〇 until the rock oxide layer 18, thereby defining a trench recess 36 in the metal mask layer T. The aforementioned dry side step generally stops in the stack layer 18. Then 'removal The remaining photoresist pattern 3q and the bottom anti-reflective layer 22' expose the remaining metal mask layer 2〇. As shown in Fig. 3, a bottom anti-reflection layer is deposited on the substrate i to make the bottom ship The reflective layer 38 fills the trench recess 36 and overlies the metal mask layer 2(). A photoresist pattern 4 is formed on the shot layer 38, and has a via opening 42' positioned just above the trench recess 36. The via opening 42 is formed using conventional micro-images. Then, using the photoresist gambling 4 () as the side mask 'in the dry side process, the bottom anti-reflective layer 38, the tantalum cap layer 18 and the low-k dielectric layer 16 are etched through the via opening 42 A partial via 46 is formed in the upper half of the low-k dielectric layer 16. The photoresist pattern 40 and the bottom anti-reflective layer 38 are as shown in the fourth _ ''then' _ oxygen battery square red _ And expose a metal mask layer 20 that has been defined with a ditches. 8 200830461 —T Figure 5 is shown in Figure 5, and then the metal mask layer 2 is used as a hard mask for the money. 'The lower side is not covered with a thin layer of metal (10) oxygen cap layer 18 乂 and the low-electricity dielectric layer 16 while continuing to etch the low-k dielectric layer through a portion of the via hole. Layering, thereby transferring the previously formed trench recess 36 and part of the dielectric 46_ to a low dielectric constant dielectric layer Forming a dual damascene opening 5〇, which includes a trench opening brother and a via opening 66. ^ As shown in Fig. 6 'and then pasting the paste, this step is also commonly referred to as the "liner removal step" (LinerRemoval) Or "LTeng step", the exposed cap layer 14 is removed via the via opening 66' to expose the underlying copper wire η. Next, we can continue the fabrication of the upper copper wire, such as the deposition of the barrier layer, the plating of the copper metal, etc., and no further description is made. The description process for the silk cap layer m is usually the fluorine containing hydrogen. Hyun-like gas, such as CH2F2 or coffee plasma. 3
然而’隨著積體電路中的關鍵線寬越來越小，雙鑲嵌開口 ％ 的介層洞開口 66與下層銅導線n發生對不準的情況也可能會越 來越嚴重’如第7圖以及第8圖卿，但是，當發輯不準的情 況，會造成最後進行蓋層14 _刻時，一併侵侧下層銅導線Η =邊的低介電常數介電層1G，形成不必要的凹穴⑽，造成後續阻 =層並不㈣人凹穴⑽，因而影_積體電路的電性表現以及可 靠度。此外，使用含氫的說烧類氣體電聚，例如CH2F2或者CHF 200830461 ， 電漿，來去除蓋層14的蝕刻製程往往同時會造成難以清除殘留物 •(有可能是電漿氣體與金屬遮罩層反應之有機金屬衍生物）。 在相關的先前技藝中，美國專利第6905968號彼露了一種雙 鑲肷製程以及選擇性蚀刻介電層的方法步驟(pR〇CES s f〇r SELECTIVELY ETCiHNG DIELECTRIC LAYERS)，其主要是利用 電漿或者CF4/N2電絲侧疊設在TE〇s %氧減者氣摻雜 石夕玻璃(FSG)上的碳氫摻雜(C，H_d〇ped)低介電常數石夕氧介電層 (k-2·5〜3) ’藉由NF3電漿或者電漿對於下層TE〇s石夕氧層 或者敦摻_玻璃的高侧選擇比，可以避免在上、下層介電層 之間使用介電常數較高的侧停止層(通常為氮化⑨）。然而，上述 專利對於經由介層洞開口所暴露出來的蓋層，則仍絲導以CH2F2 或CHF3電聚來去除，因此沒辦法解決殘留物的問題。 由上可知在積體電路製造技術領域中確實需要〆種改良之 v七成雙鑲〜、、，構的方法，以改善這種由於對不準所導致的凹穴問 題以及去除蓋層14的綱製程所造錢留物的現象。 【發明内容】 本么月之主要目的即在提供—種改良之雙鑲嵌製程方法，可 以有效地解決上述習知技藝中所發生的問題。 • 根據本U之域實施例，本發明提供-種舰製程，首先 200830461 ki、基材其具有一底層介電層、一形成在該底層介電層中之 下層導電層’以及-覆蓋住該下層導電層及該底層介電層的蓋 層’於該蓋層上沈積—介騎，於該介電層巾侧出_開口，暴 路出部分的該蓋，接著進行一襯墊層蝕除(LRM)製程，利用一四氟 化碳(cf4)/三氟化氮(NF3)氣體電漿，選擇性地姓除經由該開口暴露 出來的該蓋層，以暴露㈣分賴τ層導錢以及該底層介電 層，形成一介層洞開口，其中於該介層洞開口之底部，該下層導 電層及該底層介電層之間的落差僅小於15〇埃。 根據本發明之較佳實施例，本發明提供一種雙鑲嵌製程，首 先k供一基材，其具有一底層介電層、一形成在該底層介電層中 之下層導電層，以及一覆蓋住該下層導電層及該底層介電層的蓋 層，再於该蓋層上沈積一介電層；再於該介電層上沈積一石夕氧層， 接著再於該矽氧層上形成一金屬硬遮罩，接著，於該金屬硬遮罩 及該矽氧層中蝕刻出一溝渠凹口，然後，經由該溝渠凹口，於該 石夕氧層中以及該介電層中|虫刻出一部分介層洞開口，再將該溝渠 凹口以及該部分介層洞開口以蝕刻方式轉移至該介電層中，藉此 於該介電層形成一雙鑲嵌開口，包括一溝渠開口以及一介層洞開 口，其中該介層洞開口暴露出部分的該蓋層，最後，利用一四氟 化碳(CF4)/三氟化氮(NF3)氣體電漿經由該介層洞開口蝕除暴露出 來的該蓋層，以暴露出部分的該下層導電層以及該底層介電層。 本發明提供一種雙鑲嵌製程，首先提供一基材，其具有一底 11 200830461 ’ 層介電層、一形成在該底層介電層中之下層導電層，以及一覆蓋 .住該下層導電層及該底層介電層的蓋層。接著於該蓋層上沈積二 介電層’再於該介電層上沈積-石夕氧層，再於該石夕氧層上形成一 金屬硬遮罩’接著於該金屬硬遮罩中形成一溝渠凹口，然後，經 由該溝渠凹口，蝕刻該矽氧層與該介電層，形成一介層洞開口， 使其暴露出部分的該蓋層，最後，進行—____， 利用-不含氫的氟烧氣體混合-含氮氣體電聚，選擇性祕除經 由該介層洞開π暴露出來的該蓋層，以暴露出部分的該下層導電 層以及該底層介電層。 本發明提供一種鑲嵌内連線結構，包含有一基材，其具有一 底層介電層，一下層導電層，形成在該底層介電層中，一蓋層， 復蓋在5亥下層導電層及邊底層介電層上，一介電層，於該蓋層上， 一介層洞開口，形成於該介電層與該蓋層中，其與該下層導電層 並未對準(misaligned)，因而暴露出部分的該下層導電層及該底層 、 ’丨電層，一金屬阻障層，覆蓋於該介層洞開口之内壁上並且覆蓋 該暴露出來的該下層導電層及該底層介電層，以及一銅金屬層， 在。亥金屬阻J1竿層上’並填滿該介層洞開口。 為了使貴審查委員能更進一步了解本發明之特徵及技術内 容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 ， 供參考與輔助說明用，並非用來對本發明加以限制者。 12 200830461 【實施方式】 峨I::-9 =弟Γ圖’其緣示的是本發明較佳實施例雙鑲 的元、件戈、中仍沿用相同的符縣代表相同或類似 的几件或H域。《_是，本發财心 =)中介層洞優先(― 丰銀肷中，並不僅限於圖式中所揭露者。 士第9騎不，基材i服提供有—底層或低介電常數介電 層1〇。魏介電常數介電層财形成有下層銅導線u，並且覆 盖有-蓋層14。根據本發明之較佳實施例，蓋層14係以推雜氮的 碳化哪CN)為其成分，厚度約為3〇〇至綱埃(angstr〇m)，較佳 約為500埃左右。但蓋層14亦可以是其它的材料，例如，氮化石夕 ⑸N)、氛氧切(S趣）、碳切(SiQ、碳氧切賦⑺等。 〜接著，依序在蓋層14上形成低介電常數介電層16、顶^矽 氧蓋層11S、金屬遮罩層2〇以及底部抗反射層22。根據本發明之 較佳實_ ’金屬料層2(U議化鈦(TiN)·成分，但不限於 此，亦可以使用氮化组(TaN)等其它金屬。金屬遮罩層2〇的厚度 約介於250至450埃之間，較佳介於3〇〇至35〇埃之間。 根據本發明之較佳實施例，低介電常數介電層1〇、16可以是 具有有機矽酸鹽玻螭(organosilicateglass，〇SG)等成分，這類有機 矽酸鹽玻璃係在二氧化矽或氧化矽中摻入碳或氫原子，使其具有 13 200830461 約介於2至3之間的低介電常數值。適合作為低介電常數介電層 川、16成分，例如應用材料(Applied Materials)公司的Black Diamond™系列或者Novellus公司的CORAL™等等。根據本發明 之較佳實施例，低介電常數介電層16的厚度約介於2500至4500 埃之間，較佳介於3000至3500埃之間。 根據本發明之較佳實施例，TEOS矽氧蓋層118可利用電漿加 強化學氣相沈積(plasma-enhanced chemical vapor deposition， PECVD)技術所沈積而成，具有較低碳含量，其中使用到四乙基氧 矽烧(tetraethylorthosilicate，TEOS)作為前驅物以及氧氣，且採用比 較高的氧氣對TEOS比值(02/TEOS ratio)。 根據本發明之較佳實施例，具有較低碳含量的TE〇s矽氧蓋 層118其沈積可以利用以下的製程條件完成：壓力介於3至8托 耳，較佳約為5托耳；製程溫度在100至45(TC之間，較佳在350 至4⑻C之間；高頻無線電波功率(high-frequency RF power)約為 200至350瓦特，較佳在250至300瓦特之間，而在280瓦特最佳， 且持績k供約25秒左右，低頻無線電波功率 power)約為30至70瓦特，較佳在40至60瓦特之間，而在50瓦 特敢佳，TEOS前驅物流量約為〇.2gm至5gm ;載氣使用氦氣，而 流量介於7500至9500 seem，較佳為8500至9000 seem ;氧氣流 量介於 5000 至 loooo sccm，較佳為 8〇〇〇 sccm。 200830461 如第ίο圖所示，接下來在底部抗反射層22上形成一光阻圖 案％其具有一溝渠開口 32，疋義出錶嵌導線之溝渠圖案。 接著，如第11圖所示，進行一乾蝕刻製程，經由光阻圖案3〇 的溝渠開口 32蝕刻金屬遮罩層20直到TEOS矽氧蓋層118，藉此 形成一溝渠凹口 36。前述乾蝕刻停止在TEOS矽氧蓋層118中。 接著，利用氧軋電漿等方式去除剩下的光阻圖案3〇以及底部抗反 射層22。 如第12圖所示，然後於基材丨上沈積另一底部抗反射層刈， 且使底部抗反射層38填滿溝渠凹口 36。接著，再於底部抗反射層 38上形成一光阻圖案40,其具有一介層洞開口 42，其位置恰好在 溝渠凹口 36的正上方。上述的介層洞開口 42係利用習知的微影 技術形成。 如第13圖所示，接著利用光阻圖案40作為蝕刻硬遮罩，進 行一乾蝕刻製程，經由介層洞開口 42依序向下蝕刻底部抗反射層 38、TEOS矽氧蓋層118以及低介電常數介電層16，藉此在低介 電常數介電層16上半部形成部分介層洞46。 接著，如第14圖所示，利用氧氣電漿等方式去除剩下的光阻 圖案40以及底部抗反射層38。另外，亦可以使用H2/N2或H2/He 電漿來去除光阻圖案40以及底部抗反射層％。 15 200830461 如第15圖所示’再利用金屬遮罩層2〇作為蝕刻硬遮罩，進 行一乾蝕刻製程’向下蝕刻未被金屬遮罩層2〇覆蓋到的TE〇s矽 氧蓋層II8以及低介電常數介電们6,並經由部分介層洞46繼續 敍刻低介電常數介電層I6，直到暴露出部分的蓋層14，藉此將先 前形成的溝渠凹口 36以及部分介相46 _至低介電常數介電 層16中，形成雙鑲嵌開口 50，其包括溝渠開口 ％以及介層洞開 口 66。 如第16圖所示，接著再利用一蝕刻製程，經由介層洞開口 66运擇性地將暴露出的蓋層μ去除，藉以暴露出下層銅導線 12，但不會傷害到下層銅導線12旁邊的低介電常數介電層1〇，因 此’不會形成不必要的凹穴。 根據本發明之較佳實施例，前述用來去除蓋層14的蝕刻製程 疋採用不含氫的氟烷氣體，例如四默化碳(CFO,以及一含氮氣體， 例如二氟化氮(NF3)，所形成的混合氣體電漿，其流量比例較佳約 為3:1 ’舉例來說，四氟化碳的流量可以是150sccm，三氟化氮約 為50 sccm。根據本發明之較佳實施例，利用四氟化碳(CF4)/三氣 化氮(NF3)所形成的電漿來去除蓋層14可以提供高的選擇比，使得 暴路出的蓋層14可以很快的被去除，而不會明顯蝕刻在蓋層14 下方的低介電常數介電層10，如此一來，即可以解決介層洞開口 66與下層鋼導線12對不準的問題。 16 200830461 此外，經過實驗驗證發現，若單單使用四氟化碳電漿，而不 使用二氟化氮來蚀刻暴露出的蓋層14，雖然可以解決殘留物的問 通，但疋其遥擇比差，因此，仍然會有触刻凹穴形成在下層銅導 線12旁邊。由此可知，要避免蚀刻凹穴產生，仍需配合三氟化氮 的使用。三氟化氮可以在蝕刻到低介電常數介電層1〇時，同時於 低介電常數介電層10表面上形成一薄的保護膜，因而能夠降低其 姓刻速率。 根據本發明之其它較佳實施例，去除蓋層14的餘刻氣體亦可 以使用包括四氣化碳/一氧化氮、四氟化碳/二氧化氮、四氟化碳/ 氮氣等。但是四氟化碳/氨氣的組合則較不建議使用，這是因為氨 氣中含有虱原子’可能在餘刻過程會產生不必要且難以清除的殘 留物。 接下來，繼續進行上層銅導線的製作，如阻障層的沈積、銅 金屬的電鍍、化學機械研磨等步驟，形成如第17圖所示之雙鑲嵌 導線結構100,其包括覆蓋在溝渠開口 56以及介層洞開口 66表面 的阻障層82、嵌入在溝渠開口 56中的上層銅導線86以及嵌入在 介層洞開口 66的介層插塞96。最後，再於雙鑲嵌導線結構100 以及低介電常數介電層16表面上沈積一蓋層1〇4，例如，摻雜氮 的碳化矽、碳化矽、或氮化矽等。其中，阻障層可以是鈦、氮化 鈦、组、氮化组，或以上組合。 17 200830461 第18圖繪示的是第π圖中雙鑲嵌導線結構丨⑻的介層插塞 96與下層銅導線12之間界面的放大剖面示意圖。如第18圖所示， 本發明特別適合應用在當介層洞開口 66與下層銅導線12發生對 不準的匱况，而造成介層插塞96其有一部份必須落在低介電常數 介電層10的表面上。因此，本發明在結構上的特徵是經由介層洞 66蝕刻掉暴露出的蓋層14後，由於使用高選擇比的四氟化碳/三 氟化氮電漿，故不會明顯蝕刻低介電常數介電層1〇，僅有非常少 的低介電常數介電層10會被蝕除，形成一低於下層銅導線12上 表面的輕微下陷區域110,但是此輕微下陷區域11〇與下層銅導線 12上表面之間的落差d可被控制在小於15〇埃内，落差d甚至可 控制在50埃内，因此不會影響到後續阻障層的沈積。實際的SEM 照片’如第19圖所示。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖繪示的是習知技藝的部分介層洞優先 (partial-via-first)雙鑲嵌製程之剖面示意圖。 第7圖及第8 ®纟會tf的是介層贿下層金屬導線對不準的情形。 第9圖至第Π ®纟t示的是本發明較佳實補雙賴製程之刹面示 意圖。 18 200830461 第18圖緣示的是第17圖中雙鑲嵌導線結構100的介層插塞96與 下層銅導線12之間界面的放大剖面示意圖。 第19圖是本發明較佳實施例之SEM照片。 【主要元件符號說明】 1 基材 10 低介電常數介電層 12 下層銅導線 14 蓋層 16 低介電常數介電層 18 矽氧蓋層 20 金屬遮罩層 22 底部抗反射層 30 光阻圖案 32 溝渠開口 36 溝渠凹口 38 底部抗反射層 40 光阻圖案 42 介層洞開口 46 部分介層洞 50 雙鑲嵌開口 56 溝渠開口 66 介層洞開口 80 凹六 82 阻障層 86 上層銅導線 96 介層插塞 100 雙鑲嵌導線結構 104 蓋層 110 輕微下陷區域 118 TEOS矽氧蓋層 19However, as the critical line width in the integrated circuit becomes smaller and smaller, the case where the double-inserted opening % of the via hole opening 66 and the underlying copper wire n are inaccurate may also become more and more serious [as shown in Fig. 7] And the 8th figure, but when the issue is not accurate, it will cause the final cover layer 14 _ engraved, and invade the lower layer of copper wire Η = side of the low dielectric constant dielectric layer 1G, forming unnecessary The recess (10) causes subsequent resistance = layer not (four) human recess (10), thus the electrical performance and reliability of the shadow-integrated circuit. In addition, the use of hydrogen-containing gas-fired gas, such as CH2F2 or CHF 200830461, plasma, to remove the cap layer 14 etching process often causes difficulty in removing residues. (It may be plasma gas and metal mask Layer reaction of organometallic derivatives). In the related prior art, U.S. Patent No. 6,905,968 discloses a dual inlaid process and a method step of selectively etching a dielectric layer (pR〇CES sf〇r SELECTIVELY ETCiHNG DIELECTRIC LAYERS), which mainly utilizes plasma or Hydrocarbon doped (C, H_d〇ped) low dielectric constant Shihe oxygen dielectric layer on the CF4/N2 wire side stacked on TE〇s % oxygen reduced gas doped Shishi glass (FSG) -2·5~3) 'Using NF3 plasma or plasma for the high side selection ratio of the lower TE〇s stone oxide layer or the doped glass, it is possible to avoid the use of dielectric between the upper and lower dielectric layers. A higher constant side stop layer (usually nitride 9). However, in the above-mentioned patent, for the cap layer exposed through the opening of the via hole, the wire guide is still removed by electropolymerization of CH2F2 or CHF3, so that the problem of the residue cannot be solved. It can be seen from the above that in the field of integrated circuit manufacturing technology, there is a need for a modified v-seven-inlaid-and-in-frame method to improve the problem of the cavity caused by misalignment and the removal of the cap layer 14. The phenomenon of making money and retaining things in the course of the process. SUMMARY OF THE INVENTION The main purpose of this month is to provide an improved dual damascene process method that can effectively solve the problems occurring in the above-mentioned conventional techniques. According to an embodiment of the present invention, the present invention provides a seeding process, first of all, 200830461 ki, a substrate having an underlying dielectric layer, a lower conductive layer formed in the underlying dielectric layer, and - covering the The lower conductive layer and the cap layer of the underlying dielectric layer are deposited on the cap layer, and the opening is opened on the side of the dielectric layer, and the cover is violently exited, and then a liner layer is removed. (LRM) process, using a tetrafluorocarbon (cf4) / nitrogen trifluoride (NF3) gas plasma, selectively surnamed except the exposed layer exposed through the opening to expose (four) to the τ layer And the underlying dielectric layer forms a via opening, wherein a gap between the underlying conductive layer and the underlying dielectric layer is less than 15 Å at the bottom of the via opening. According to a preferred embodiment of the present invention, the present invention provides a dual damascene process, first for a substrate having an underlying dielectric layer, a lower conductive layer formed in the underlying dielectric layer, and a cover layer Depositing a lower dielectric layer and a cap layer of the underlying dielectric layer, and depositing a dielectric layer on the cap layer; depositing a layer of a luminescent layer on the dielectric layer, and then forming a metal on the germanium oxide layer a hard mask, and then etching a trench recess in the metal hard mask and the germanium oxide layer, and then, through the trench recess, in the rock oxide layer and in the dielectric layer a portion of the via hole is opened, and the trench recess and the portion of the via opening are etched into the dielectric layer, thereby forming a dual damascene opening in the dielectric layer, including a trench opening and a via a hole opening, wherein the opening of the via hole exposes a portion of the cap layer, and finally, a silicon tetrafluorocarbon (CF4)/nitrogen trifluoride (NF3) gas plasma is used to etch away the exposed hole through the via hole opening. The cap layer to expose a portion of the underlying conductive layer and the Dielectric layer. The present invention provides a dual damascene process, first providing a substrate having a bottom 11 200830461 'layer dielectric layer, a lower conductive layer formed in the underlying dielectric layer, and a covering and holding the lower conductive layer and a cap layer of the underlying dielectric layer. Depositing a dielectric layer on the cap layer and depositing a rock oxide layer on the dielectric layer, and then forming a metal hard mask on the silicon oxide layer, and then forming in the metal hard mask. a trench recess, and then etching the germanium oxide layer and the dielectric layer via the trench recess to form a via opening to expose a portion of the cap layer, and finally, performing -____, utilization - not The fluoro-fired gas mixture of hydrogen - the gas-containing gas is electropolymerized, selectively removing the cap layer exposed through the via hole to expose a portion of the underlying conductive layer and the underlying dielectric layer. The present invention provides a damascene interconnect structure comprising a substrate having an underlying dielectric layer, a lower conductive layer formed in the underlying dielectric layer, a cap layer overlying the 5 gal conductive layer and On the underlying dielectric layer, a dielectric layer is formed on the cap layer, and a via opening is formed in the dielectric layer and the cap layer, which is not misaligned with the underlying conductive layer. Exposing a portion of the underlying conductive layer and the underlayer, the 'tantalum layer, a metal barrier layer overlying the inner wall of the via opening and covering the exposed lower conductive layer and the underlying dielectric layer, And a copper metal layer, in. The metal barrier is on the J1 layer and fills the via opening. In order to provide a further understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for the purpose of illustration and description only and are not intended to limit the invention. 12 200830461 [Embodiment] 峨I::-9 = Γ Γ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Or H domain. "_Yes, this is a fortune =) Intermediary hole priority ("Feng Yin Yuzhong, not limited to those disclosed in the figure. Shi Ji 9 is not, the substrate i service is provided with - bottom or low dielectric constant The dielectric layer 1 〇. The Wei dielectric constant dielectric layer is formed with an underlying copper wire u and covered with a cap layer 14. According to a preferred embodiment of the invention, the cap layer 14 is carbonized by a nitrogen-inducing CN. It is a component having a thickness of about 3 angstroms to angstroms, preferably about 500 angstroms. However, the cap layer 14 may also be other materials, for example, nitride (5) N), oxygen cut (S fun), carbon cut (SiQ, carbon oxygen cut (7), etc. - then, sequentially formed on the cap layer 14 a low-k dielectric layer 16, a top oxide cap layer 11S, a metal mask layer 2〇, and a bottom anti-reflective layer 22. According to the present invention, the metal layer 2 (UN titanium (TiN) The composition, but not limited thereto, may also use other metals such as a nitrided layer (TaN). The metal mask layer 2 has a thickness of about 250 to 450 angstroms, preferably 3 to 35 angstroms. According to a preferred embodiment of the present invention, the low-k dielectric layers 1 and 16 may be composed of an organosilicate glass (〇SG), such an organic tantalate glass. The carbon dioxide or hydrogen atom is doped into the cerium oxide or cerium oxide to have a low dielectric constant value of about 2 to 3 in the range of 13 200830461. It is suitable as a low dielectric constant dielectric layer, 16 components, for example, application. Material (Applied Materials)'s Black DiamondTM series or Novellus's CORALTM, etc. According to a preferred embodiment of the present invention The low dielectric constant dielectric layer 16 has a thickness of between about 2,500 and 4,500 angstroms, preferably between about 3,000 and 3,500 angstroms. According to a preferred embodiment of the invention, the TEOS oxime cap layer 118 can utilize a plasma. Enhanced by plasma-enhanced chemical vapor deposition (PECVD) technology, with lower carbon content, using tetraethylorthosilicate (TEOS) as precursor and oxygen, and comparison High oxygen to TEOS ratio (02/TEOS ratio). According to a preferred embodiment of the invention, the TE〇s oxide cap layer 118 having a lower carbon content can be deposited using the following process conditions: a pressure of 3 Up to 8 Torr, preferably about 5 Torr; process temperature between 100 and 45 (TC, preferably between 350 and 4 (8) C; high-frequency RF power of about 200 to 350 Watt, preferably between 250 and 300 watts, and best at 280 watts, with a performance k for about 25 seconds, low frequency radio power power) of about 30 to 70 watts, preferably 40 to 60 watts. Between, while at 50 watts, the TEOS precursor flow is about 2. 2gm to 5gm; the carrier gas uses helium, and the flow rate is between 7500 and 9500 seem, preferably 8500 to 9000 seem; the oxygen flow is between 5000 and loooo sccm, preferably 8 〇〇〇 sccm. 200830461 As shown in Fig. 00, a photoresist pattern is formed on the bottom anti-reflective layer 22, which has a trench opening 32, which is a trench pattern of the embedded conductor. Next, as shown in Fig. 11, a dry etching process is performed to etch the metal mask layer 20 through the trench opening 32 of the photoresist pattern 3 to the TEOS oxide cap layer 118, thereby forming a trench recess 36. The aforementioned dry etching is stopped in the TEOS oxide cap layer 118. Next, the remaining photoresist pattern 3 and the bottom anti-reflection layer 22 are removed by means of oxygen rolling plasma or the like. As shown in Fig. 12, another bottom anti-reflective layer 刈 is then deposited on the substrate 刈, and the bottom anti-reflective layer 38 fills the trench recess 36. Next, a photoresist pattern 40 is formed on the bottom anti-reflective layer 38, which has a via opening 42 positioned just above the trench recess 36. The via opening 42 described above is formed using conventional lithography techniques. As shown in FIG. 13, the photoresist pattern 40 is then used as an etch hard mask, and a dry etching process is performed to sequentially etch the bottom anti-reflection layer 38, the TEOS oxide cap layer 118, and the low-level layer through the via opening 42. The dielectric layer 16 is electrically constant, whereby a portion of the via 46 is formed in the upper half of the low-k dielectric layer 16. Next, as shown in Fig. 14, the remaining photoresist pattern 40 and the bottom anti-reflection layer 38 are removed by means of oxygen plasma or the like. Alternatively, H2/N2 or H2/He plasma may be used to remove the photoresist pattern 40 and the bottom anti-reflective layer %. 15 200830461 As shown in Figure 15, 'Reuse the metal mask layer 2 as an etched hard mask, perform a dry etching process' to etch down the TE〇s oxide cap layer II8 that is not covered by the metal mask layer 2〇 And a low-k dielectric 6 and continuing to scribe the low-k dielectric layer I6 via the via 44 until a portion of the cap layer 14 is exposed, thereby forming the previously formed trench recess 36 and portions In the dielectric 46 _ to low dielectric constant dielectric layer 16, a dual damascene opening 50 is formed which includes a trench opening % and a via opening 66. As shown in FIG. 16, an exposed etching process is then used to selectively remove the exposed cap layer μ via the via opening 66, thereby exposing the underlying copper wire 12 without damaging the underlying copper wire 12 The low dielectric constant dielectric layer next to it is such that it does not form unnecessary pockets. According to a preferred embodiment of the present invention, the etching process for removing the cap layer 14 uses a fluorocarbon gas containing no hydrogen, such as tetracarbonized carbon (CFO, and a nitrogen-containing gas such as nitrogen difluoride (NF3). The mixed gas plasma is preferably formed to have a flow ratio of about 3:1 '. For example, the flow rate of the carbon tetrafluoride may be 150 sccm, and the nitrogen trifluoride may be about 50 sccm. In the embodiment, the use of a plasma formed by carbon tetrafluoride (CF4)/three vaporized nitrogen (NF3) to remove the cap layer 14 can provide a high selectivity ratio, so that the storm cover layer 14 can be quickly removed. The low-k dielectric layer 10 under the cap layer 14 is not obviously etched, so that the problem of misalignment between the via hole opening 66 and the underlying steel wire 12 can be solved. 16 200830461 It has been found that if the carbon tetrachloride plasma is used alone instead of using nitrogen difluoride to etch the exposed cap layer 14, although the problem of the residue can be solved, the remote selection ratio is poor, and therefore, A tentacles are formed beside the lower copper wire 12. It is known that corrosion is to be avoided. The formation of the recessed hole still needs to be combined with the use of nitrogen trifluoride. The nitrogen trifluoride can form a thin layer on the surface of the low-k dielectric layer 10 while etching to the low-k dielectric layer. The protective film can thus reduce its surname rate. According to other preferred embodiments of the present invention, the residual gas for removing the cap layer 14 can also be used including carbon tetrachloride/nitric oxide, carbon tetrafluoride/nitrogen dioxide. , carbon tetrafluoride / nitrogen, etc.. But the combination of carbon tetrafluoride / ammonia is less recommended, because ammonia contains helium atoms, which may produce unnecessary and difficult to remove residues in the remaining process. Next, the fabrication of the upper copper wire is continued, such as deposition of a barrier layer, electroplating of copper metal, chemical mechanical polishing, etc., to form a dual damascene wire structure 100 as shown in FIG. 17, which includes covering the trench opening And a barrier layer 82 on the surface of the via opening 66, an upper copper conductor 86 embedded in the trench opening 56, and a via plug 96 embedded in the via opening 66. Finally, the dual damascene conductor structure 100 and Low dielectric constant A cap layer 1 〇 4 is deposited on the surface of the layer 16, for example, nitrogen-doped lanthanum carbide, tantalum carbide, tantalum nitride, etc., wherein the barrier layer may be titanium, titanium nitride, group, nitride group, or The above combination is shown in Fig. 18 is an enlarged cross-sectional view showing the interface between the interlayer plug 96 and the lower copper conductor 12 of the double damascene conductor structure 8 (8) in the πth diagram. As shown in Fig. 18, the present invention It is particularly suitable for application when the via hole opening 66 and the underlying copper wire 12 are misaligned, and a portion of the via plug 96 must fall on the surface of the low-k dielectric layer 10. The structural feature of the present invention is that after the exposed cap layer 14 is etched through the via hole 66, the low dielectric is not significantly etched due to the use of a high selectivity ratio of carbon tetrafluoride/nitrogen trifluoride plasma. With a constant dielectric layer 1 仅有, only a very small low-k dielectric layer 10 is etched away to form a slightly depressed region 110 below the upper surface of the underlying copper wire 12, but this slightly depressed region 11 〇 and the lower layer The drop d between the upper surfaces of the copper wires 12 can be controlled within less than 15 angstroms, the drop d can even be controlled within 50 angstroms, so it does not affect the deposition of subsequent barrier layers. The actual SEM photo ' is shown in Figure 19. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 6 are schematic cross-sectional views showing a partial-via-first dual damascene process of the prior art. Figure 7 and the 8th 纟 纟 tf are the case where the underlying metal wire is inaccurate. Fig. 9 through Π ® 纟t show the schematic representation of the preferred embodiment of the present invention. 18 200830461 Figure 18 is an enlarged cross-sectional view showing the interface between the via plug 96 and the underlying copper trace 12 of the dual damascene conductor structure 100 of Fig. 17. Figure 19 is a SEM photograph of a preferred embodiment of the present invention. [Main component symbol description] 1 Substrate 10 Low-k dielectric layer 12 Lower copper wire 14 Cap layer 16 Low-k dielectric layer 18 Oxygen cap layer 20 Metal mask layer 22 Bottom anti-reflection layer 30 Photoresist Pattern 32 Ditch opening 36 Ditch recess 38 Bottom anti-reflective layer 40 Photoresist pattern 42 Via opening 46 Partial via 50 Double damascene opening 56 Ditch opening 66 Via opening 80 Concave six 82 Barrier layer 86 Upper copper wire 96 Interlayer Plug 100 Dual Inlaid Conductor Structure 104 Cap Layer 110 Slightly Sinked Area 118 TEOS Oxygen Cap Layer 19