US6472306B1 - Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer - Google Patents

Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer Download PDF

Info

Publication number
US6472306B1
US6472306B1 US09655097 US65509700A US6472306B1 US 6472306 B1 US6472306 B1 US 6472306B1 US 09655097 US09655097 US 09655097 US 65509700 A US65509700 A US 65509700A US 6472306 B1 US6472306 B1 US 6472306B1
Authority
US
Grant status
Grant
Patent type
Prior art keywords
layer
method
dielectric material
spin
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US09655097
Inventor
Shyh-Dar Lee
Chung-I Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Industrial Technology Research Institute
Original Assignee
Industrial Technology Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835Combinations of two or more different dielectric layers having a low dielectric constant
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material

Abstract

A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.

Description

BACKGROUND OF THE INVENTION

A high speed logic device with low RC delay back-end-of-line (BEOL) is preferred in present integrated circuit (IC) approaches. Copper (Cu) is chosen for its lower resistance and low dielectric constant (low-k) which minimizes capacitance in BEOL.

Dual damascene structures will be used in the next generation processes and devices. Integration of copper dual damascene structures and low-k material is the predominant trend for IC processes.

Currently, chemical vapor deposition (CVD) low-k material and spin-on-polymer (SOP) are candidates for such low-k materials. However there are many issues that need to be resolved for low-k integration in ultra large-scale integration (ULSI) processes.

SOP is likely an organic material and therefore its chemical structure is similar to photoresist material. So inorganic oxides have been used as hard masks (HM) in etching processes of SOP and the adhesion between HM and the underlying organic low-k material is very important.

U.S. Pat. No. 6,010,962 to Liu et al. describes a method for forming inlaid copper interconnects in an insulating layer without dishing after chemical-mechanical polishing of the excess copper. A lower insulating layer 110 and an upper insulating layer 130, separated by an intervening etch stop layer 120, are formed a substrate 100. The upper and lower insulating layers 110, 130 may be comprised materials formed by, for example, CVD, PECVD, PVD or low-k materials, FSG, HSQ, Flare and PAE2.

U.S. Pat. No. 6,004,883 to Yu et al. describes a method for forming a dual damascene opening and structure through a dielectric layer within a microelectronics fabrication without an etch stop layer. A lower dielectric layer consists of a first dielectric material which is not susceptible to etching within an oxygen containing plasma, such as silicon oxide, silicon nitride, and silicon oxynitride. First vias are formed within the first dielectric material. An upper dielectric layer is formed over the lower dielectric layer and consists of a second dielectric material which is susceptible to etching within an oxygen containing plasma of a ratio of at least 20:1 compared to the first dielectric material. The second dielectric material is then patterned and etched through a hard mask to form second vias coexistent with the first vias and together forming a dual damascene via opening.

U.S. Pat. No. 6,013,581 to Wu et al. describes a method for preventing poisoning of trenches and vias in a dual damascene process. A densification process, such as a plasma treatment, is performed on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densification process prevents poisoning of the trenches and vias caused by outgassing.

U.S. Pat. No. 5,817,572 to Chiang et al. describes a method for forming interconnections in semiconductor devices. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. A second patterned dielectric layer is formed over the first dielectric layer and has a second opening exposing at least a portion of the conductive material. The first dielectric layer may serve as an etch-stop layer in patterning the second dielectric layer or a separate etch-stop layer may be formed over the first dielectric layer and conductive material before formation of the second dielectric layer.

U.S. Pat. No. 6,007,733 to Jang et al. describes a method for forming a patterned layer within a microelectronics fabrication. An oxygen containing plasma etchable layer, which is also susceptible to etching within a fluorine containing plasma, is formed over a microelectronics substrate. A hard mask layer is then formed over the oxygen containing plasma etchable layer, and a patterned photoresist layer is in turn formed over the hard mask layer. The hard mask is patterned by a first anisotropic plasma etch method and the patterned photoresist layer is stripped from the patterned hard mask layer by a stripping method which does not attack the oxygen containing plasma etchable layer. A second plasma etch method is used to pattern the oxygen containing plasma etchable layer through the patterned hard mask layer. The second plasma etch method is the fluorine containing plasma etch method.

The article entitled “Pursuing the Perfect Low-k Dielectric,” Laura Peters, Semiconductor International, Sep. 1998, pp. 64-74, describes various potential low-k dielectric materials, including FSG and HSQ, to be used with copper interconnects.

The press release entitled “International Sematech Validates Manufacturing Capability of Applied Material's Low-k Solution for Copper Interconnects—Successful Results Achieved with Black Diamond for Production of Sub-0.18 Micron Chips,” Applied Materials, Feb. 28, 2000, describes a successful evaluation of Applied Materials, Inc.'s Black Diamond™ material (a family of low-k products deposited using the DLK chamber) for production of advanced interconnect structures in copper sub-0.18 micron devices.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a novel CVD low-k material, and a method of making same, that overcomes the disadvantages of the present low-k materials used with copper dual damascene structures.

Another object of the present invention is to provide a novel CVD low-k material, and a method of making same, whose dielectric constant remains stable despite further processing.

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the method of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:

FIGS. 1 and 2 schematically illustrate in cross-sectional representation the adhesion issue with contemporary dual damascene processes.

FIG. 3-6 schematically illustrate in cross-sectional representation the gap filling capability of spin-on-polymer issue with contemporary dual damascene processes.

FIG. 7 schematically illustrates in cross-sectional representation the CVD low-k dielectric hardness issue with contemporary dual damascene processes.

FIG. 8 schematically illustrates in cross-sectional representation the CVD low-k dielectric—photoresist interaction issue with contemporary dual damascene processes.

FIGS. 9-16 schematically illustrates in cross-sectional representation the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Unless otherwise specified, all structures, layers, etc. may be formed or accomplished by conventional methods known in the prior art.

Problems Known to the Inventors

The following is not to be considered prior art.

Adhesion Issue

For example, as shown in FIG. 1, silicon, or other, organic low-k dielectric layer 14 overlies substrate 10 with adhesion promoter layer 12 therebetween. Organic low-k dielectric layer 14 may be comprised of SOP. Hard mask (HM) 16 overlies SOP layer 14 and may consist of an inorganic oxide such as silicon oxide (SiO2).

However, as shown in FIG. 2, an enlargement of the area indicated as “FIG. 2” in FIG. 1 with an additional dielectric layer 50 formed over HM 16, the adhesion between inorganic oxide HM 16 and organic low-k dielectric layer 14 needs to improve. Gap 52 indicate delamination, or separation, of HM 16 from dielectric layer 14.

Gap Filling Capability of SOP

As shown in FIG. 3, patterned photoresist layer 18 is formed over the structure of FIG. 1.

As shown in FIG. 4, SiO2 hard mask layer 16 is etched through patterned photoresist layer 18 forming gaps 20 in hard mask layer 16.

As shown in FIG. 5, when photoresist layer 18 is stripped from patterned hard mask 16 by an oxygen plasma method, the oxygen plasma also etches into SOP layer 14 forming trenches 22 beneath hard mask layer gaps 20.

As shown in FIG. 6, when second SOP layer 24 is then formed over the structure, SOP layer 24 must have the necessary gap filling capability to fill trenches 22 in lower SOP layer 14 and gaps 20 in SiO2 hard mask layer 16. This limits the materials available that may constitute second SOP layer 24.

CVD Process Issues for Low-k Material

A. Hardness Issue

As shown in FIG. 7, substrate 10 has adhesion promoter layer 12 formed thereover with CVD low-k layer 14 formed over adhesion promoter layer 12. CVD low-k layer 14 has a hardness below 1 Gpa and is generally porous and soft. This can lead to package failure.

B. Interaction with Photoresist

As shown in FIG. 8, CVD low-k layer 14 has methyl groups in the side chains. Thus, a reaction between photoresist layer 18 and the exposed portions of CVD low-k layer 14 at 26

Present Invention

Formation of SOP Layer 106 and CVD low-k Layer 108 Over M1 Structure

Accordingly, as shown in FIG. 9, semiconductor structure 100 is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.

Semiconductor structure 100 includes exposed metal lines 102 preferably comprised of copper (Cu).

Sealing layer (i.e. barrier layer) 104 is formed over semiconductor structure 100 and metal lines 102. Sealing layer 104 is preferably comprised of silicon nitride (Si3N4).

Spin-on-polymer (SOP) layer 106 is then formed over sealing layer 104. SOP layer 106 is organic and may consist of SiLK™ material by Dow Chemical, FLARE™ material by Allied Signal or Honeywell, and an organic material including C, H, O element such as CH3—SiO2 of TOK series.

SOP layer 106 is preferably from about 1000 to 9000 Å thick, more preferably from about 3000 to 6000 Å thick, and most preferably about 3100 Å thick.

SOP layer 106 is formed as follows:

Including C, H, O element, the functional group of chemical structures are alcohol—ether—ketone—aldehyde—acid—ester and arylate (the conventional materials are such as FLARE (supplied by Honeywell), SiLK (supplied by Dow Chemical), and CH3—SiO2 of TOK series). Spin coater is generally used to develop this film. The solvent is always used as a carrier material. This mixture belongs to beta-stage material. Therefore, a baking process is required at: from about 50 to 280° C. for from about 10 to 90 seconds for multi-stage. Eventually, a curing process is then required at: from about 300 to 450° C. for from about 30 to 90 minutes. Further:

1) RI is from about 1.35 to 1.43;

2) carbon content by FTIR is from about 30 to 65%;

3) oxygen content is from about 10 to 30%;

4) hydrogen content is from about 30 to 65%;

5) silicon content is from about 1 to 10%;

6) hardness is from about 0.5 to 3 Gpa;

7) density is from about 1.5 to 1.8 g/cm3;

8) dielectric constant is from about 2.0 to 2.9;

9) stress is from about compressive 10E−8 to tensile 10E−8;

10) breakdown voltage is from about 2 to 9 MV/cm at 10−3A/cm2;

11) leakage current at 0.5 MV/cm is from about <10−10 to 10−12 A/cm2; and

12) extinction coefficient is from about 0 to 1.

Layer 108 is formed over SOP layer 106 by an inorganic chemical vapor deposition process (CVD) to create a CVD low-k material layer 108. The CVD low-k material layer 108 generally includes the elements Si, H, O and C. Because Si-O is a major component, this material is an inorganic material.

The chemical structure may be split into two groups. One group has a linear structure and includes materials such as Black Diamond™ (BD) supplied by AMAT, Coral™ supplied by Novellus, povA, carbon doped silicon oxide and Greendot™ supplied by Mattson. The other group has a ring structure and includes materials such as Aurora™ supplied by ASM J. A plasma enhanced chemical vapor deposition (PECVD) tool may be used to develop these films. A spin coater is also a good process tool for inorganic materials.

CVD low-k layer 108 is from about 1000 to 9000 Å thick, and is preferably from about 3000 to 6000 Å thick.

CVD low-k layer 108 is formed as follows:

1) RI is from about 1.30 to 1.67;

2) carbon content by FTIR is from about 5 to 50%;

3) oxygen content is from about 10 to 30%;

4) hydrogen content is from about 10 to 30%;

5) modulus is from about 40 to 70 Gpa;

6) hardness is from about 0.5 to 7 Gpa;

7) density is from about 1.5 to 1.8 g/cm3;

8) dielectric constant is from about 2.2 to 3.3;

9) film stress is from about 30 to 100 Mpa tensile;

10) breakdown voltage is from about 2 to 9 MV/cm at 10−3A/cm2; and

11) leakage current at 0.5 MV/cm is from about <10−10 to 10−12 A/cm2.

Anti-reflective layer (ARL) 110 is formed over CVD low-k layer 108, preferably by a PECVD process. ARL layer 110 may be comprised of silicon oxynitride (SiON), SiC, or TiN, and is preferably SiON.

SiON ARL layer 110 is from about 100 to 600 Å thick, and is preferably from about 250 to 320 Å thick.

Define via Pattern

As shown in FIG. 10, first photoresist (PR) layer 112 is formed and patterned over ARL layer 110 to define via pattern 114 exposing selected portions of ARL layer 110.

Etching CVD Low-k Layer 108 to Form via 116

As shown in FIG. 11, exposed ARL layer 110 within via pattern 114, and the corresponding portions of underlying CVD low-k layer 108, are etched down to SOP layer 106 to form CVD low-k layer via openings 116 exposing underlying portions 118 of SOP layer 106. Once this pattern is opened, first PR layer 112 shrinks, reducing its thickness.

C2F6/Ar (i.e. C2F6 in an Ar carrier gas) is the major etch process gas in the etching of CVD low-k layer 108. The ratio of C2F6/Ar is from about 0.1 to 0.5. The power includes TCP and BP power. The transformer coupled plasma (TCP) power is from about 800 to 1200 W. The bias plasma (BP) power is from about 500 to 1500 W. The process pressure is from about 8 to 12 mTorr.

SOP Layer 106 via 118 Formation

As shown in FIG. 12, first photoresist layer 112 is stripped from the structure.

Exposed portions 118 of SOP layer 106 are etched down to sealing layer 104 using patterned ARL layer 110/etched CVD low-k layer 108 as a mask to form SOP via openings 120.

Nitrogen (N2) and oxygen (O2) are the major process etch process gases in the etching of SOP layer 106. The ratio of N2/O2 is from about 5 to 12. The power includes TCP and BP power. The TCP power is from about 1000 to 1800 W. The BP power is from about 180 to 250 W.

CVD Low-k Layer 108 Trench 128 Formation

As shown in FIG. 13, second photoresist layer 122 is formed and patterned over the structure exposing selected portions 124 of ARL layer 110/CVD low-k layer 108 adjacent CVD low-k layer via openings 116, and at least a portion of via opening 116. For example, photoresist layer 122 is formed over the structure, filling via openings 116, 120. Photoresist layer 122 is selectively exposed, but not down to the sealing layer 104 over metal lines 102. The exposed portion of photoresist layer 122 is removed leaving at least a portion of SOP layer via openings 120 remain filled with second photoresist layer plugs 126.

As shown in FIG. 14, using second photoresist layer 122 as a mask, exposed portions 124 of ARL layer 110 and the corresponding portions of underlying CVD low-k layer 108 are etched down to the underlying portions of SOP layer 106 to form CVD low-k layer 108 trenches 128. During the etching of trenches 128, photoresist plugs 126 serve to protect sealing layer 104/metal line 102.

Lower SOP layer 106 via openings 120 and upper CVD low-k layer 108 trenches 128 together form dual damascene openings 130.

Second Photoresist Layer 122 Strip/In-situ Clean of Dual Damascene Openings 130

As shown in FIG. 15, remaining second photoresist layer 122, including photoresist plug 126, is stripped from the structure leaving dual damascene openings 130 open. It is noted that a large amount of O2 at 35 mTorr was used by TCP.

Dual damascene openings 130 are then in-situ cleaned to remove any remnants of first and/or second photoresist layers 112, 122.

It is noted that for FLARE and SiLK, the organic low-k material forming SOP low-k layer 106, a spin coater was used in ERSO; and for BD, Coral, and Aurora material, the CVD low-k material forming CVD low-k layer 108, a PECVD machine/tool was used. A low-k etcher was the etch tool used to etch SOP organic low-k layer 106; an oxide etcher was the etch tool used to etch CVD low-k layer 108; and a PR striper was the tool used to strip photoresist layers 112, 122.

Completion of Dual Damascene Structure

As shown in FIG. 16, the remaining portions of ARL layer 110 are removed. A layer of metal is then formed over the structure, filling dual damascene openings 130. The metal layer is then planarized to remove the excess of the metal from patterned CVD low-k layer 108 and form dual damascene structures 132. Dual damascene structures 132 are preferably formed of copper (Cu).

Advantages of the Present Invention

The advantages of the dual damascene patterning of the present invention include:

1) an etch stop layer is not required (dielectric constant of silicon oxide is about 4.1);

2) the via first and trench first can be performed to achieve the dual damascene structure;

3)the etch process easily achieves a good profile of via or trench;

4) the effective dielectric constant (k) will be reduced compared to the prior process structures (no etch stop layer is required);

5) the effective dielectric constant (k) is maintained;

6) a sacrificial layer is not needed;

7) the processing steps are relatively easy;

8) a silicon oxide hard mask is not required;

9) the adhesion between the CVD low-k layer 108 and the SOP layer 106 is improved; and

10) the total hardness is improved.

While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Claims (37)

We claim:
1. A method of forming a dual damascene opening, comprising the steps of:
providing a semiconductor structure having at least one exposed metal line;
forming a spin-on-polymer layer over said semiconductor structure and said metal line;
forming a CVD dielectric material layer upon said spin-on-polymer layer;
patterning said CVD dielectric material layer to form a CVD dielectric material layer via over said metal line;
patterning said spin-on-polymer layer to form a spin-on-polymer layer via opening continuous and contiguous with said CVD dielectric material layer via and exposing a portion of said metal line; and
patterning said CVD dielectric material layer adjacent said CVD dielectric material layer via to form a CVD dielectric material layer trench; said spin-on-polymer layer via opening and said CVD dielectric material layer trench forming a dual damascene opening.
2. The method of claim 1, wherein said SOP layer is formed using a spin coater with a baking step at from about 50 to 280° C. for from about 10 to 90 seconds followed by a curing step at from about 300 to 450° C. for from about 30 to 90 minutes.
3. The method of claim 1, wherein said CVD dielectric layer includes from about 5 to 50% by FTIR; from about 10 to 30% oxygen; and from about 10 to 30% hydrogen.
4. The method of claim 1, wherein said spin-on-polymer layer is from about 1000 to 9000 Å thick, and said CVD dielectric material layer is from about 1000 to 9000 Å thick.
5. The method of claim 1, wherein said spin-on-polymer layer 106 is from about 3000 to 6000 Å thick, and said CVD dielectric material layer 108 is from about 3000 to 6000 Å thick.
6. The method of claim 1, including the steps of:
forming a sealing layer over said semiconductor structure and said metal line; and
forming an anti-reflection layer over said CVD dielectric material layer.
7. The method of claim 1, wherein said spin-on-polymer layer is comprised of a material selected from the group comprising SiLK, FLARE, and CH3—SiO2.
8. The method of claim 1, wherein said spin-on-polymer layer is comprised of the elements C, H, O, and Si with at least an arylate series functional group.
9. The method of claim 1, wherein said CVD dielectric material layer is comprised of a material selected from the group comprising BD, silicon oxide, Coral™, povA, Greendot™, and carbon doped silicon oxide.
10. The method of claim 1, wherein said CVD dielectric material layer is comprised of silicon oxide.
11. The method of claim 1, wherein said SOP layer has the following characteristics:
1) RI is from about 1.35 to 1.43;
2) carbon content by FTIR is from about 30 to 65%;
3) oxygen content is from about 10 to 30%;
4) hydrogen content is from about 30 to 65%;
5) silicon content is from about 1 to 10%;
6) hardness is from about 0.5 to 3 Gpa;
7) density is from about 1.5 to 1.8 g/cm3;
8) dielectric constant is from about 2.0 to 2.9;
9) stress is from about compressive 10E−8 to tensile 10E−8;
10) breakdown voltage is from about 2 to 9 MV/cm at 10−3 A/cm2;
11) leakage current at 0.5 MV/cm is from about <10−10 to 10−12 A/cm2; and
12) extinction coefficient is from about 0 to 1.
12. The method of claim 1, wherein said CVD dielectric layer has the following characteristics:
1) RI is from about 1.30 to 1.67;
2) carbon content by FTIR is from about 5 to 50%;
3) oxygen content is from about 10 to 30%;
4) hydrogen content is from about 10 to 30%;
5) modulus is from about 40 to 70 Gpa;
6) hardness is from about 0.5 to 7 Gpa;
7) density is from about 1.5 to 1.8 g/cm3;
8) dielectric constant is from about 2.2 to 3.3;
9) film stress is from about 30 to 100 Mpa tensile;
10) breakdown voltage is from about 2 to 9 MV/cm at 10−3 A/cm2; and
11) leakage current at 0.5 MV/cm is from about <10−10 to 10−12 A/cm2.
13. A method of forming a dual damascene opening, comprising the steps of:
providing a semiconductor structure having at least one exposed metal line;
forming a sealing layer over said semiconductor structure and said metal line;
forming a spin-on-polymer layer over said sealing layer;
forming a CVD dielectric material layer upon said spin-on-polymer layer;
forming an anti-reflection layer over said CVD dielectric material layer;
patterning said anti-reflection layer and said CVD dielectric material layer to form a CVD dielectric material layer via over said metal line;
patterning said spin-on-polymer layer to form a spin-on-polymer layer via opening continuous and contiguous with said CVD dielectric material layer via and exposing a portion of said metal line; and
patterning said anti-reflection layer and said CVD dielectric material layer adjacent said CVD low-k material layer via to form a CVD dielectric material layer trench; said spin-on-polymer layer via opening and said CVD dielectric material layer trench forming a dual damascene opening.
14. The method of claim 13, wherein said SOP layer is formed using a spin coater with a baking step at from about 50 to 280° C. for from about 10 to 90 seconds followed by a curing step at from about 300 to 450° C. for from about 30 to 90 minutes.
15. The method of claim 13, wherein said CVD dielectric layer includes from about 5 to 50% by FTIR; from about 10 to 30% oxygen; and from about 10 to 30% hydrogen.
16. The method of claim 13, wherein said spin-on-polymer layer is from about 1000 to 9000 Å thick, and said CVD dielectric material layer is from about 1000 to 9000 Å thick.
17. The method of claim 13, wherein said spin-on-polymer layer is from about 3000 to 6000 Å thick, and said CVD dielectric material layer 108 is from about 3000 to 6000 Å thick.
18. The method of claim 13, wherein said spin-on-polymer layer is comprised of a material selected from the group comprising SiLK, FLARE, and CH3—SiO2.
19. The method of claim 13, wherein said spin-on-polymer layer is comprised of the elements C, H, O, and Si with at least an arylate series functional group.
20. The method of claim 13, wherein said CVD dielectric material layer is comprised of a material selected from the group comprising BD, silicon oxide, Coral™, povA, Greendot™, and carbon doped silicon oxide.
21. The method of claim 13, wherein said CVD dielectric material layer is comprised of silicon oxide.
22. The method of claim 13, wherein said sealing layer is comprised of silicon nitride.
23. The method of claim 13, wherein said anti-reflection layer is comprised of SiON.
24. A method of forming a dual damascene opening, comprising the steps of:
providing a semiconductor structure having at least one exposed metal line;
forming a silicon nitride layer over said semiconductor structure and said metal line;
forming a spin-on-polymer layer over said sealing layer;
forming a CVD dielectric material layer upon said spin-on-polymer layer;
forming an SiON layer over said CVD dielectric material layer;
patterning said SiON layer and said CVD dielectric material layer to form a CVD dielectric material layer via over said metal line;
patterning said spin-on-polymer layer to form a spin-on-polymer layer via opening continuous and contiguous with said CVD dielectric material layer via and exposing a portion of said metal line; and
patterning said SiON layer and said CVD dielectric material layer adjacent said CVD dielectric material layer via to form a CVD dielectric material layer trench; said spin-on-polymer layer via opening and said CVD dielectric material layer trench forming a dual damascene opening.
25. The method of claim 24, wherein said SOP layer is formed using a spin coater with a baking step at from about 50 to 280° C. for from about 10 to 90 seconds followed by a curing step at from about 300 to 450° C. for from about 30 to 90 minutes.
26. The method of claim 24, wherein said CVD dielectric layer includes from about 5 to 50% by FTIR; from about 10 to 30% oxygen; and from about 10 to 30% hydrogen.
27. The method of claim 24, wherein said spin-on-polymer layer is from about 1000 to 9000 Å thick, and said CVD dielectric material layer is from about 1000 to 9000 Å thick.
28. The method of claim 24, wherein said spin-on-polymer layer is from about 3000 to 6000 Å thick, and said CVD dielectric material layer is from about 3000 to 6000 Å thick.
29. The method of claim 24, wherein said spin-on-polymer layer is comprised of a material selected from the group comprising SiLK, FLARE, and CH3—SiO2.
30. The method of claim 24, wherein said spin-on-polymer layer is comprised of the elements C, H, O, and Si with at least an arylate series functional group.
31. The method of claim 24, wherein said CVD dielectric material layer is comprised of a material selected from the group comprising BD, silicon oxide, Coral™, povA, Greendot™, and carbon doped silicon oxide.
32. The method of claim 24, wherein said CVD dielectric material layer is comprised of silicon oxide.
33. The method of claim 24, wherein said SOP layer has the following characteristics:
1) RI is from about 1.35 to 1.43;
2) carbon content by FTIR is from about 30 to 65%;
3) oxygen content is from about 10 to 30%;
4) hydrogen content is from about 30 to 65%;
5) silicon content is from about 1 to 10%;
6) hardness is from about 0.5 to 3 Gpa;
7) density is from about 1.5 to 1.8 g/cm3;
8) dielectric constant is from about 2.0 to 2.9;
9) stress is from about compressive 10E−8 to tensile 10E−8;
10) breakdown voltage is from about 2 to 9 MV/cm at 103A/cm2;
11) leakage current at 0.5 MV/cm is from about <10−10 to 10−12 A/cm2; and
12) extinction coefficient is from about 0 to 1.
34. The method of claim 24, wherein said CVD dielectric layer has the following characteristics:
1) RI is from about 1.30 to 1.67;
2) carbon content by FTIR is from about 5 to 50%;
3) oxygen content is from about 10 to 30%;
4) hydrogen content is from about 10 to 30%;
5) modulus is from about 40 to 70 Gpa;
6) hardness is from about 0.5 to 7 Gpa;
7) density is from about 1.5 to 1.8 g/cm3;
8) dielectric constant is from about 2.2 to 3.3;
9) film stress is from about 30 to 100 Mpa tensile;
10) breakdown voltage is from about 2 to 9 MV/cm at 10−3 A/cm2; and
11) leakage current at 0.5 MV/cm is from about <10−10 to 10−2 A/cm2.
35. The method of claim 1, wherein said CVD dielectric material layer has a dielectric constant of from about 2.2 to 3.3.
36. The method of claim 13, wherein said CVD dielectric material layer has a dielectric constant of from about 2.2 to 3.3.
37. The method of claim 24, wherein said CVD dielectric material layer has a dielectric constant of from about 2.2 to 3.3.
US09655097 2000-09-05 2000-09-05 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer Active 2021-01-06 US6472306B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09655097 US6472306B1 (en) 2000-09-05 2000-09-05 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09655097 US6472306B1 (en) 2000-09-05 2000-09-05 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer

Publications (1)

Publication Number Publication Date
US6472306B1 true US6472306B1 (en) 2002-10-29

Family

ID=24627495

Family Applications (1)

Application Number Title Priority Date Filing Date
US09655097 Active 2021-01-06 US6472306B1 (en) 2000-09-05 2000-09-05 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer

Country Status (1)

Country Link
US (1) US6472306B1 (en)

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6541368B2 (en) * 2001-06-30 2003-04-01 Hynix Semiconductor Inc. Metal lines of semiconductor devices and methods for forming
US20030114013A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
WO2003054928A2 (en) * 2001-12-13 2003-07-03 International Business Machines Corporation Porous low-k dielectric interconnect structures
US6605545B2 (en) * 2001-06-01 2003-08-12 United Microelectronics Corp. Method for forming hybrid low-K film stack to avoid thermal stress effect
US6649512B1 (en) * 2002-06-07 2003-11-18 Silicon Integrated Systems Corp. Method for improving adhesion of a low k dielectric to a barrier layer
US6680262B2 (en) * 2001-10-25 2004-01-20 Intel Corporation Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface
US20040026783A1 (en) * 2002-08-12 2004-02-12 Grant Kloster Low-k dielectric film with good mechanical strength
US20040053504A1 (en) * 2002-09-16 2004-03-18 International Business Machines Corporation In-situ plasma etch for TERA hard mask materials
US20040094839A1 (en) * 2002-11-14 2004-05-20 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
US6762127B2 (en) * 2001-08-23 2004-07-13 Yves Pierre Boiteux Etch process for dielectric materials comprising oxidized organo silane materials
US20040241983A1 (en) * 2003-05-30 2004-12-02 Hynix Semiconductor Inc. Method for manufacturing metal line of semiconductor device
US20050062164A1 (en) * 2003-09-23 2005-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving time dependent dielectric breakdown lifetimes
US20050070093A1 (en) * 2003-09-29 2005-03-31 Barns Chris E. Sacrificial dielectric planarization layer
US20050093108A1 (en) * 2003-10-29 2005-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating layer having decreased dielectric constant and increased hardness
US20050101119A1 (en) * 2003-11-06 2005-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating layer having graded densification
US20050112858A1 (en) * 2003-11-21 2005-05-26 Nanya Technology Corporation Contact hole forming method
US20050156285A1 (en) * 2004-01-16 2005-07-21 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same
US20050170625A1 (en) * 2004-01-29 2005-08-04 Chartered Semiconductor Manufacturing Ltd. Novel method to control dual damascene trench etch profile and trench depth uniformity
US20050170633A1 (en) * 2004-02-03 2005-08-04 Nec Electronics Corporation Semiconductor device and method of manufacturing a semiconductor device
US6962869B1 (en) * 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment
US20050260806A1 (en) * 2004-05-19 2005-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. High performance strained channel mosfets by coupled stress effects
US20050272177A1 (en) * 2004-06-02 2005-12-08 Semiconductor Manufacturing International (Shanghai) Corporation Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices
US20060166491A1 (en) * 2005-01-21 2006-07-27 Kensaku Ida Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process
US20070132086A1 (en) * 2005-12-13 2007-06-14 Sairam Agraharam Integrated circuit devices including compliant material under bond pads and methods of fabrication
CN100334695C (en) * 2003-01-02 2007-08-29 上海华虹(集团)有限公司 Process for silicon low dielectric material curing in furnace
US20070200241A1 (en) * 2005-12-05 2007-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process without an etch stop layer
US20070205507A1 (en) * 2006-03-01 2007-09-06 Hui-Lin Chang Carbon and nitrogen based cap materials for metal hard mask scheme
US20070246776A1 (en) * 2006-04-20 2007-10-25 Synopsys, Inc. Stress engineering for cap layer induced stress
US20080079120A1 (en) * 2006-10-03 2008-04-03 Innovative Micro Technology Interconnect structure using through wafer vias and method of fabrication
US7365006B1 (en) * 2004-05-05 2008-04-29 Amkor Technology, Inc. Semiconductor package and substrate having multi-level vias fabrication method
US20080171434A1 (en) * 2007-01-16 2008-07-17 United Microelectronics Corp. Method of fabricating dual damascene structure
US7557031B2 (en) 2004-09-15 2009-07-07 Semiconductor Manufacturing International (Shanghai) Corporation Etch back with aluminum CMP for LCOS devices
CN100590810C (en) 2007-07-27 2010-02-17 中芯国际集成电路制造(上海)有限公司 Method for forming medium layer and method for manufacturing dual-damascene structure
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
CN101853807A (en) * 2009-03-27 2010-10-06 朗姆研究公司 Method for dielectric material removal between conductive lines
US7911037B1 (en) 2006-10-04 2011-03-22 Amkor Technology, Inc. Method and structure for creating embedded metal features
US7923385B2 (en) 2003-03-31 2011-04-12 Novellus Systems, Inc. Methods for producing low stress porous and CDO low-K dielectric materials using precursors with organic functional groups
US7972976B1 (en) 2005-01-31 2011-07-05 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials
US8316536B1 (en) 2002-05-01 2012-11-27 Amkor Technology, Inc. Multi-level circuit substrate fabrication method
US20140087559A1 (en) * 2012-09-27 2014-03-27 United Microelectronics Corp. Semiconductor structure and manufacturing method of the same
US8826531B1 (en) 2005-04-05 2014-09-09 Amkor Technology, Inc. Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
US8872329B1 (en) 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method
US20150270189A1 (en) * 2011-08-05 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K Dielectric Layer and Porogen
US9812386B1 (en) 2002-05-01 2017-11-07 Amkor Technology, Inc. Encapsulated semiconductor package

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817572A (en) 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
US6004883A (en) 1998-10-23 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene patterned conductor layer formation method without etch stop layer
US6007733A (en) 1998-05-29 1999-12-28 Taiwan Semiconductor Manufacturing Company Hard masking method for forming oxygen containing plasma etchable layer
US6010962A (en) 1999-02-12 2000-01-04 Taiwan Semiconductor Manufacturing Company Copper chemical-mechanical-polishing (CMP) dishing
US6013581A (en) 1998-07-28 2000-01-11 United Microelectronics Corp. Method for preventing poisoned vias and trenches
US6207555B1 (en) * 1999-03-17 2001-03-27 Electron Vision Corporation Electron beam process during dual damascene processing
US6211068B1 (en) * 1999-05-25 2001-04-03 United Microelectronics Corp. Dual damascene process for manufacturing interconnects
US6255232B1 (en) * 1999-02-11 2001-07-03 Taiwan Semiconductor Manufacturing Company Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer
US6333256B2 (en) * 1997-02-12 2001-12-25 Micron Technology, Inc. Semiconductor processing method of forming openings in a material
US6350682B1 (en) * 1998-01-23 2002-02-26 United Microelectronics Corp. Method of fabricating dual damascene structure using a hard mask

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817572A (en) 1992-06-29 1998-10-06 Intel Corporation Method for forming multileves interconnections for semiconductor fabrication
US6333256B2 (en) * 1997-02-12 2001-12-25 Micron Technology, Inc. Semiconductor processing method of forming openings in a material
US6350682B1 (en) * 1998-01-23 2002-02-26 United Microelectronics Corp. Method of fabricating dual damascene structure using a hard mask
US6007733A (en) 1998-05-29 1999-12-28 Taiwan Semiconductor Manufacturing Company Hard masking method for forming oxygen containing plasma etchable layer
US6013581A (en) 1998-07-28 2000-01-11 United Microelectronics Corp. Method for preventing poisoned vias and trenches
US6004883A (en) 1998-10-23 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene patterned conductor layer formation method without etch stop layer
US6255232B1 (en) * 1999-02-11 2001-07-03 Taiwan Semiconductor Manufacturing Company Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer
US6010962A (en) 1999-02-12 2000-01-04 Taiwan Semiconductor Manufacturing Company Copper chemical-mechanical-polishing (CMP) dishing
US6207555B1 (en) * 1999-03-17 2001-03-27 Electron Vision Corporation Electron beam process during dual damascene processing
US6211068B1 (en) * 1999-05-25 2001-04-03 United Microelectronics Corp. Dual damascene process for manufacturing interconnects

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"International Sematech Validates Manufacturing Capability of Applied Material's Low-K Solution for Copper Interconnects-Successful Results Achieved with Black Diamond for Production of Sub-0.18 Micron Chips", Applied Materials, Feb. 28, 2000.
"International Sematech Validates Manufacturing Capability of Applied Material's Low-K Solution for Copper Interconnects—Successful Results Achieved with Black Diamond for Production of Sub-0.18 Micron Chips", Applied Materials, Feb. 28, 2000.
L. Peters, "Pursuing the Perfect Low-K Dielectric," Semi-Conductor International, Sep. 1998, pp. 64-74.

Cited By (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6605545B2 (en) * 2001-06-01 2003-08-12 United Microelectronics Corp. Method for forming hybrid low-K film stack to avoid thermal stress effect
US6541368B2 (en) * 2001-06-30 2003-04-01 Hynix Semiconductor Inc. Metal lines of semiconductor devices and methods for forming
US6762127B2 (en) * 2001-08-23 2004-07-13 Yves Pierre Boiteux Etch process for dielectric materials comprising oxidized organo silane materials
US6680262B2 (en) * 2001-10-25 2004-01-20 Intel Corporation Method of making a semiconductor device by converting a hydrophobic surface of a dielectric layer to a hydrophilic surface
US6933586B2 (en) * 2001-12-13 2005-08-23 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
USRE45781E1 (en) 2001-12-13 2015-10-27 GlobalFoundries, Inc. Toughness, adhesion and smooth metal lines of porous low K dielectric interconnect structures
US20040018717A1 (en) * 2001-12-13 2004-01-29 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
WO2003054928A3 (en) * 2001-12-13 2005-02-24 Ibm Porous low-k dielectric interconnect structures
US6844257B2 (en) 2001-12-13 2005-01-18 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
WO2003054928A2 (en) * 2001-12-13 2003-07-03 International Business Machines Corporation Porous low-k dielectric interconnect structures
US20030114013A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
US6783862B2 (en) 2001-12-13 2004-08-31 International Business Machines Corporation Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
US8316536B1 (en) 2002-05-01 2012-11-27 Amkor Technology, Inc. Multi-level circuit substrate fabrication method
US8322030B1 (en) * 2002-05-01 2012-12-04 Amkor Technology, Inc. Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns
US9812386B1 (en) 2002-05-01 2017-11-07 Amkor Technology, Inc. Encapsulated semiconductor package
US6649512B1 (en) * 2002-06-07 2003-11-18 Silicon Integrated Systems Corp. Method for improving adhesion of a low k dielectric to a barrier layer
US6964919B2 (en) * 2002-08-12 2005-11-15 Intel Corporation Low-k dielectric film with good mechanical strength
US20060009031A1 (en) * 2002-08-12 2006-01-12 Grant Kloster Low-K dielectric film with good mechanical strength that varies in local porosity depending on location on substrate - therein
US20040026783A1 (en) * 2002-08-12 2004-02-12 Grant Kloster Low-k dielectric film with good mechanical strength
US7145245B2 (en) * 2002-08-12 2006-12-05 Intel Corporation Low-k dielectric film with good mechanical strength that varies in local porosity depending on location on substrate—therein
US6903023B2 (en) * 2002-09-16 2005-06-07 International Business Machines Corporation In-situ plasma etch for TERA hard mask materials
US20040053504A1 (en) * 2002-09-16 2004-03-18 International Business Machines Corporation In-situ plasma etch for TERA hard mask materials
US6962869B1 (en) * 2002-10-15 2005-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. SiOCH low k surface protection layer formation by CxHy gas plasma treatment
US20050023693A1 (en) * 2002-11-14 2005-02-03 Fitzsimmons John A. Reliable low-k interconnect structure with hybrid dielectric
US7135398B2 (en) * 2002-11-14 2006-11-14 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
US6917108B2 (en) 2002-11-14 2005-07-12 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
US20040094839A1 (en) * 2002-11-14 2004-05-20 International Business Machines Corporation Reliable low-k interconnect structure with hybrid dielectric
CN100334695C (en) * 2003-01-02 2007-08-29 上海华虹(集团)有限公司 Process for silicon low dielectric material curing in furnace
US7923385B2 (en) 2003-03-31 2011-04-12 Novellus Systems, Inc. Methods for producing low stress porous and CDO low-K dielectric materials using precursors with organic functional groups
US20040241983A1 (en) * 2003-05-30 2004-12-02 Hynix Semiconductor Inc. Method for manufacturing metal line of semiconductor device
US7176123B2 (en) * 2003-05-30 2007-02-13 Hynix Semiconductor Inc. Method for manufacturing metal line of semiconductor device
US20050062164A1 (en) * 2003-09-23 2005-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving time dependent dielectric breakdown lifetimes
US6908863B2 (en) * 2003-09-29 2005-06-21 Intel Corporation Sacrificial dielectric planarization layer
US20050070061A1 (en) * 2003-09-29 2005-03-31 Barns Chris E. Sacrificial dielectric planarization layer
US20050070093A1 (en) * 2003-09-29 2005-03-31 Barns Chris E. Sacrificial dielectric planarization layer
US7109557B2 (en) 2003-09-29 2006-09-19 Intel Corporation Sacrificial dielectric planarization layer
US20050093108A1 (en) * 2003-10-29 2005-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating layer having decreased dielectric constant and increased hardness
US7352053B2 (en) 2003-10-29 2008-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Insulating layer having decreased dielectric constant and increased hardness
US20050101119A1 (en) * 2003-11-06 2005-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating layer having graded densification
US6958524B2 (en) 2003-11-06 2005-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Insulating layer having graded densification
US20050112858A1 (en) * 2003-11-21 2005-05-26 Nanya Technology Corporation Contact hole forming method
US20060055004A1 (en) * 2004-01-16 2006-03-16 International Business Machines Corporation Low K and ultra low K SiCOH dielectric films and methods to form the same
US7282458B2 (en) * 2004-01-16 2007-10-16 International Business Machines Corporation Low K and ultra low K SiCOH dielectric films and methods to form the same
US20050156285A1 (en) * 2004-01-16 2005-07-21 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same
US7030468B2 (en) * 2004-01-16 2006-04-18 International Business Machines Corporation Low k and ultra low k SiCOH dielectric films and methods to form the same
US7247555B2 (en) 2004-01-29 2007-07-24 Chartered Semiconductor Manufacturing Ltd. Method to control dual damascene trench etch profile and trench depth uniformity
US20050170625A1 (en) * 2004-01-29 2005-08-04 Chartered Semiconductor Manufacturing Ltd. Novel method to control dual damascene trench etch profile and trench depth uniformity
US20070117405A1 (en) * 2004-02-03 2007-05-24 Nec Electronics Corporation Method of manufacturing a semiconductor device
US7180191B2 (en) * 2004-02-03 2007-02-20 Nec Electronics Corporation Semiconductor device and method of manufacturing a semiconductor device
US20050170633A1 (en) * 2004-02-03 2005-08-04 Nec Electronics Corporation Semiconductor device and method of manufacturing a semiconductor device
US7615498B2 (en) 2004-02-03 2009-11-10 Nec Electronics Corporation Method of manufacturing a semiconductor device
US7365006B1 (en) * 2004-05-05 2008-04-29 Amkor Technology, Inc. Semiconductor package and substrate having multi-level vias fabrication method
US7119404B2 (en) * 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
US20050260806A1 (en) * 2004-05-19 2005-11-24 Taiwan Semiconductor Manufacturing Co., Ltd. High performance strained channel mosfets by coupled stress effects
US9310643B2 (en) 2004-06-02 2016-04-12 Semiconductor Manufacturing International (Shanghai) Corporation Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices
US20050272177A1 (en) * 2004-06-02 2005-12-08 Semiconductor Manufacturing International (Shanghai) Corporation Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices
US7527993B2 (en) * 2004-06-02 2009-05-05 Semiconductor Manufacturing International (Shanghai) Corporation Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices
US20090200564A1 (en) * 2004-06-02 2009-08-13 Semiconductor Manufacturing International (Shanghai) Corporation Method and Structure for Fabricating Smooth Mirrors for Liquid Crystal on Silicon Devices
US7557031B2 (en) 2004-09-15 2009-07-07 Semiconductor Manufacturing International (Shanghai) Corporation Etch back with aluminum CMP for LCOS devices
US20060166491A1 (en) * 2005-01-21 2006-07-27 Kensaku Ida Dual damascene interconnection having low k layer and cap layer formed in a common PECVD process
US7972976B1 (en) 2005-01-31 2011-07-05 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials
US8826531B1 (en) 2005-04-05 2014-09-09 Amkor Technology, Inc. Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
US20070200241A1 (en) * 2005-12-05 2007-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process without an etch stop layer
US7629690B2 (en) * 2005-12-05 2009-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene process without an etch stop layer
US7535114B2 (en) * 2005-12-13 2009-05-19 Intel Corporation Integrated circuit devices including compliant material under bond pads and methods of fabrication
US20070132086A1 (en) * 2005-12-13 2007-06-14 Sairam Agraharam Integrated circuit devices including compliant material under bond pads and methods of fabrication
US20070205507A1 (en) * 2006-03-01 2007-09-06 Hui-Lin Chang Carbon and nitrogen based cap materials for metal hard mask scheme
US20100024978A1 (en) * 2006-04-20 2010-02-04 Synopsys, Inc. Stress engineering for cap layer induced stress
US20100029050A1 (en) * 2006-04-20 2010-02-04 Synopsys, Inc. Stress engineering for cap layer induced stress
US20070246776A1 (en) * 2006-04-20 2007-10-25 Synopsys, Inc. Stress engineering for cap layer induced stress
US20080079120A1 (en) * 2006-10-03 2008-04-03 Innovative Micro Technology Interconnect structure using through wafer vias and method of fabrication
US7675162B2 (en) 2006-10-03 2010-03-09 Innovative Micro Technology Interconnect structure using through wafer vias and method of fabrication
US7911037B1 (en) 2006-10-04 2011-03-22 Amkor Technology, Inc. Method and structure for creating embedded metal features
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
US8034712B2 (en) * 2007-01-16 2011-10-11 United Microelectronics Corp. Method of fabricating dual damascene structure
US7838415B2 (en) * 2007-01-16 2010-11-23 United Microelectronics Corp. Method of fabricating dual damascene structure
US20110021021A1 (en) * 2007-01-16 2011-01-27 United Microelectronics Corp. Method of fabricating dual damascene structure
US20080171434A1 (en) * 2007-01-16 2008-07-17 United Microelectronics Corp. Method of fabricating dual damascene structure
CN100590810C (en) 2007-07-27 2010-02-17 中芯国际集成电路制造(上海)有限公司 Method for forming medium layer and method for manufacturing dual-damascene structure
US9462704B1 (en) 2009-01-09 2016-10-04 Amkor Technology, Inc. Extended landing pad substrate package structure and method
US8872329B1 (en) 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method
CN101853807B (en) 2009-03-27 2014-03-12 朗姆研究公司 Method for dielectric material removal between conductive lines
CN101853807A (en) * 2009-03-27 2010-10-06 朗姆研究公司 Method for dielectric material removal between conductive lines
US9564383B2 (en) * 2011-08-05 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen
US20150270189A1 (en) * 2011-08-05 2015-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K Dielectric Layer and Porogen
US20140087559A1 (en) * 2012-09-27 2014-03-27 United Microelectronics Corp. Semiconductor structure and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US6245663B1 (en) IC interconnect structures and methods for making same
US6177329B1 (en) Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets
US6331479B1 (en) Method to prevent degradation of low dielectric constant material in copper damascene interconnects
US6074942A (en) Method for forming a dual damascene contact and interconnect
US6297554B1 (en) Dual damascene interconnect structure with reduced parasitic capacitance
US6184142B1 (en) Process for low k organic dielectric film etch
US6143670A (en) Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer
US6696222B2 (en) Dual damascene process using metal hard mask
US6309955B1 (en) Method for using a CVD organic barc as a hard mask during via etch
US6440863B1 (en) Plasma etch method for forming patterned oxygen containing plasma etchable layer
US6734090B2 (en) Method of making an edge seal for a semiconductor device
US20050106888A1 (en) Method of in-situ damage removal - post O2 dry process
Cote et al. Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits
US6054377A (en) Method for forming an inlaid via in a semiconductor device
US6249056B1 (en) Low resistance interconnect for a semiconductor device and method of fabricating the same
US6376366B1 (en) Partial hard mask open process for hard mask dual damascene etch
US6127258A (en) Method for forming a semiconductor device
US6251770B1 (en) Dual-damascene dielectric structures and methods for making the same
US6028363A (en) Vertical via/contact
US6140224A (en) Method of forming a tungsten plug
US6368979B1 (en) Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6797627B1 (en) Dry-wet-dry solvent-free process after stop layer etch in dual damascene process
US20050079706A1 (en) Dual damascene structure and method
US6599839B1 (en) Plasma etch process for nonhomogenous film
US6284657B1 (en) Non-metallic barrier formation for copper damascene type interconnects

Legal Events

Date Code Title Description
AS Assignment

Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, SHYH-DAR;CHANG, CHUNG-I;REEL/FRAME:011144/0297

Effective date: 20000816

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12