CN101937868B - Method for making through hole in integrated circuit - Google Patents
Method for making through hole in integrated circuit Download PDFInfo
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- CN101937868B CN101937868B CN 200910057520 CN200910057520A CN101937868B CN 101937868 B CN101937868 B CN 101937868B CN 200910057520 CN200910057520 CN 200910057520 CN 200910057520 A CN200910057520 A CN 200910057520A CN 101937868 B CN101937868 B CN 101937868B
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Abstract
The invention discloses a method for making a through hole in an integrated circuit. The method comprises the following steps of: making a metal layer, a metal coating, a first dielectric layer and a first dielectric anti-reflective layer from bottom to top in turn; making a second dielectric layer on the first dielectric anti-reflective layer; making a second anti-reflective layer on the second dielectric layer; coating photoresist on the second anti-reflective layer; making the through hole penetrating to the metal coating by lithography and etching processes; removing the photoresist and the second anti-reflective layer; depositing a filler of the through hole; performing back-etching on the filler and the second dielectric layer, so that the filler is still higher than the upper surface of the first anti-reflective layer after the second dielectric layer is removed; coating the photoresist; and making an upper structure. By using the method, the position of the filler of the through hole is higher than the first anti-reflective layer so as to avoid the residue of the photoresist in the through hole in a subsequent process and improve the process control of subsequent wiring groove etching.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, the manufacture method of through hole in especially a kind of integrated circuit.
Background technology
Road (Back-End-Of-Line behind semiconductor; BEOL) in the dual damascene process (dual-damascene) that metal connecting line is made; wherein a kind of technological process is that first etching through hole (via) is to the lower metal cover layer; in through hole, fill the material with good filling perforation more afterwards; such as Barc (bottom anti-reflection coating; bottom anti-reflection layer), so as after etching through hole above cover layer and the lower metal of hardware cloth wire casing time protection via bottoms.This process among Fig. 1, is metal level 1, metal cladding 2, dielectric layer 3 and anti-reflecting layer 4 as shown in Figures 1 to 4 from down to up successively; At described anti-reflecting layer 4 coating photoresists 5, as shown in Figure 2; Then make the through hole that the bottom is through to described metal cladding 2 by photoetching and etching technics, and remove photoresist, as shown in Figure 3; Deposit filler 6 is in through hole, as shown in Figure 4 again.
After deposit filler 6, return the filler of filling out quarter (etch-back).Consider from the uniformity of filler deposit and etching technics, generally to return to carve to this step and carry out over etching (over-etch), will make like this filler in the through hole be etched away a part, thereby cause the filler interface to be lower than the dielectric layer upper surface in hole, to guarantee not having filler residual on the surface of dielectric layer, as shown in Figure 5.In follow-up hardware cloth wire casing photoetching process, photoresist 7 need to be coated with again, as shown in Figure 6 on the structure that just now completed.Be subjected to graphics effect (pattern-effect) impact, the photoresist of Lian Kongzhong below the hardware cloth wire casing of some specific dimensions and figure is difficult to fully to be exposed or develops and remain in through hole, as shown in Figure 7, thus cause very large difficulty for the groove etched technology controlling and process of follow-up metal line.
Summary of the invention
Technical problem to be solved by this invention provides the manufacture method of through hole in a kind of integrated circuit, can eliminate the residual of photoresist in the through hole, to improve the technology controlling and process of follow-up wiring groove etching.
For solving the problems of the technologies described above, the technical scheme of the manufacture method of through hole is in the integrated circuit of the present invention, comprise the metal level of making successively from down to up, metal cladding, first medium layer and first medium anti-reflecting layer, on described first medium anti-reflecting layer, make afterwards the second medium layer, on described second medium layer, make the second anti-reflecting layer, then be coated with photoresist at described the second anti-reflecting layer, produce the through hole that is through to described metal cladding by photoetching and etching technics, then remove photoresist and described the second anti-reflecting layer, the filler of deposit through hole, again filler and described second medium layer are returned quarter, thickness and etching selection ratio by control filler and the deposit of second medium layer, so that after described second medium layer is removed, the height of described filler still is higher than the upper surface of the first anti-reflecting layer, be coated with again afterwards photoresist, make the more structure of last layer.
The present invention has been by having increased second medium layer and the second anti-reflecting layer, so that the filler position of through hole is higher than the first anti-reflecting layer, thereby avoided residual in through hole of photoresist in the subsequent technique, improved the technology controlling and process of follow-up wiring groove etching.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1～Fig. 7 is the schematic diagram of each step of through hole manufacture method in the existing integrated circuit;
Fig. 8 is the flow chart of the manufacture method of through hole in the integrated circuit of the present invention;
Fig. 9～Figure 15 is the schematic diagram of each step of manufacture method of through hole in the integrated circuit of the present invention.
Reference numeral is among the figure, 1. metal level; 2. metal cladding; 3. first medium layer; 4. the first anti-reflecting layer; 5. photoresist; 6. filler; 7. photoresist; 8. second medium layer; 9. the second anti-reflecting layer.
Embodiment
The invention discloses the manufacture method of through hole in a kind of integrated circuit, its flow process as shown in Figure 8, make successively first metal level 1 from down to up, metal cladding 2, first medium layer 3 and first medium anti-reflecting layer 4, on described first medium anti-reflecting layer 4, make afterwards second medium layer 8, on described second medium layer, make the second anti-reflecting layer 9, as shown in Figure 9, then as shown in figure 10 at described the second anti-reflecting layer coating photoresist 5, produce the through hole that is through to described metal cladding by photoetching and etching technics, as shown in figure 11, then remove photoresist 5 and described the second anti-reflecting layer 9, the filler 6 of deposit through hole, as shown in figure 12, again filler 6 and described second medium layer 8 are returned quarter, thickness and etching selection ratio by control filler 6 and 8 deposit of second medium layer, so that after described second medium layer 8 is removed, the height of described filler 6 still is higher than the upper surface of the first anti-reflecting layer 4, as shown in figure 13, be coated with again as shown in figure 14 afterwards photoresist 7, make the more structure of last layer, when afterwards photoresist 7 being removed, because the height of filler 6 is higher than the first anti-reflecting layer 4, so can residual photoresist 7 in the through hole.
When the present invention removes unnecessary filler second medium layer 8, by the control etching selection ratio, so that when etching is removed filler 6, the least possible exerts an influence to second medium layer 8, and when etching was removed second medium layer 8, the least possible exerted an influence to remaining filler 6.In deposit second medium layer 8, want so that the thickness of second medium layer 8 is suitable, be enough to so that when subsequently filler 6 being carried out etching, after the filler 6 of second medium layer 8 top was etched away fully, the height of filler 6 still remained on the level that is higher than the first anti-reflecting layer 4 in the through hole.
Described the first anti-reflecting layer material is SiON, and its depositing technics adopts PE-CVD (plasma enhanced CVD), AP-CVD (Films Prepared by APCVD) or LP-CVD (low-pressure chemical vapor phase deposition), and thickness range is
Described second medium layer is the dielectric that contains Si, and its depositing technics adopts PE-CVD, AP-CVD or LP-CVD, and thickness range is
Described second medium layer is Si0
2Or Si
3N
4
Described the second anti-reflecting layer is the organic material with photoetching anti-reflection function, and its thickness range is
Described the second anti-reflecting layer is Barc.
Described filler is for having good filling perforation performance and certain etch resistance, and with the organic material of general photoresist compatibility, its thickness range is
Described filler is Barc.
In sum, the present invention is by having increased second medium layer and the second anti-reflecting layer, so that the filler position of through hole is higher than the first anti-reflecting layer, thereby avoid residual in through hole of photoresist in the subsequent technique, improved the technology controlling and process of follow-up wiring groove etching.
Claims (8)
1. the manufacture method of through hole in the integrated circuit, it is characterized in that, comprise the metal level of making successively from down to up, metal cladding, first medium layer and first medium anti-reflecting layer, on described first medium anti-reflecting layer, make afterwards the second medium layer, on described second medium layer, make the second anti-reflecting layer, then be coated with photoresist at described the second anti-reflecting layer, produce the through hole that is through to described metal cladding by photoetching and etching technics, then remove photoresist and described the second anti-reflecting layer, the filler of deposit through hole, again filler and described second medium layer are returned quarter, thickness and etching selection ratio by control filler and the deposit of second medium layer, so that after described second medium layer is removed, the height of described filler still is higher than the upper surface of the first anti-reflecting layer, be coated with again afterwards photoresist, make the more structure of last layer.
2. the manufacture method of through hole in the integrated circuit according to claim 1 is characterized in that, described the first anti-reflecting layer material is SiON, and its depositing technics adopts PE-CVD, AP-CVD or LP-CVD, and thickness range is
3. the manufacture method of through hole in the integrated circuit according to claim 1 is characterized in that, described second medium layer is the dielectric that contains Si, and its depositing technics adopts PE-CVD, AP-CVD or LP-CVD, and thickness range is
4. the manufacture method of through hole in the integrated circuit according to claim 3 is characterized in that, described second medium layer is SiO
2Or Si
3N
4
5. the manufacture method of through hole in the integrated circuit according to claim 1 is characterized in that, described the second anti-reflecting layer is the organic material with photoetching anti-reflection function, and its thickness range is
6. the manufacture method of through hole in the integrated circuit according to claim 1 is characterized in that, described the second anti-reflecting layer is Barc.
7. the manufacture method of through hole in the integrated circuit according to claim 1, it is characterized in that, described filler is for having good filling perforation performance, and etch rate is less than the etch rate of second medium layer, and can with the organic material of general photoresist compatibility, its thickness range is
8. the manufacture method of through hole in the integrated circuit according to claim 1 is characterized in that, described filler is Barc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910057520 CN101937868B (en) | 2009-06-30 | 2009-06-30 | Method for making through hole in integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910057520 CN101937868B (en) | 2009-06-30 | 2009-06-30 | Method for making through hole in integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101937868A CN101937868A (en) | 2011-01-05 |
| CN101937868B true CN101937868B (en) | 2013-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910057520 Active CN101937868B (en) | 2009-06-30 | 2009-06-30 | Method for making through hole in integrated circuit |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071742A (en) * | 2020-09-18 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single inlay structure and dual inlay structure and their open hole forming method |
-
2009
- 2009-06-30 CN CN 200910057520 patent/CN101937868B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single inlay structure and dual inlay structure and their open hole forming method |
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| Publication number | Publication date |
|---|---|
| CN101937868A (en) | 2011-01-05 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |