CN104867867A - Method for forming side wall of APF (advanced patterning film) - Google Patents
Method for forming side wall of APF (advanced patterning film) Download PDFInfo
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- CN104867867A CN104867867A CN201510179795.1A CN201510179795A CN104867867A CN 104867867 A CN104867867 A CN 104867867A CN 201510179795 A CN201510179795 A CN 201510179795A CN 104867867 A CN104867867 A CN 104867867A
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- Prior art keywords
- layer
- side wall
- apf
- protective film
- groove structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- General Physics & Mathematics (AREA)
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- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for forming a side wall of an APF (advanced patterning film), which comprises the steps of sequentially forming a protective film layer and a sacrificial layer, then removing the sacrificial layer and the protective film layer at the top part and the bottom part of a trench structure, reserving the sacrificial layer and the protective film layer at the side wall of the trench structure, finally removing the sacrificial layer at the side wall of the trench structure and reserving the protective film layer, and forming the APF side wall with the protective film layer side wall in the end. According to the invention, the sacrificial layer is introduced to the protective film layer, thereby being capable of keeping the structure morphology of the side wall and acquiring stable line width, also being capable of avoiding an undercut phenomenon at the same time, and being conducive to carrying out the follow-up process. The method disclosed by the invention can carry out effective control on results through simple process adjustment, and does not cause obvious influences for the process complexity and the production cost at the same time.
Description
Technical field
The present invention relates to the manufacturing technology field of semiconductor integrated circuit, particularly relate to the formation method for side wall of a kind of APF.
Background technology
Along with developing rapidly of electronic information technology, the update of consumer electronics product is increased, promotes ic manufacturing technology fast development.Along with integrated circuit critical size constantly reduces, technical problem emerges in an endless stream.At IC interior, due to the existence of interlayer dielectric layer, between wire, inevitably there is parasitic capacitance.This distributed capacitance not only affects the speed of chip, also constitutes a threat to functional reliability.Continue the trend reduced at device size under, the impact of this electric capacity on device performance is more and more obvious.By reducing dielectric dielectric constant k value, effectively can reduce the distributed capacitance between interconnection line, shortening signal propagation delay (RC time delay), improve the speed of integrated circuit.Based on this consideration, dielectric is by traditional SiO
2gradually to advanced low-k materials and ultra-low dielectric constant material development, but after the technology generation entering below 20nm, existing ultra-low dielectric constant material still cannot meet technical need.Also the popular domain of research is become thus based on the interconnect scheme of air-gap.
It is adopt special material (decomposing under certain condition) sacrifice layer to complete whole technological process as interconnection layer medium that the main flow Integrated Solution of air-gap mainly contains two kinds: one, then applying specified conditions (as 400 DEG C of high temperature) to this sacrifice layer makes it decompose, become gaseous material to be released, finally form air-gap.Two is adopt conventional material (as SiO
2, Low-k) as interconnection layer sacrificial dielectric, after completing current layer metallization, etch away this sacrificial dielectric, the dielectric layer of deposition one deck filling capacity difference, forms metal connecting line air-gap.
In addition, also has the air-gap formation method that a class is non-mainstream, i.e. Cu-first (metal wire is preferential) Integrated Solution, the program first deposits one deck barrier layer and inculating crystal layer at silicon chip surface, graphical by APF (advanced graphical film), copper plating is carried out to patterned area, then removes photoresist and inculating crystal layer and barrier layer, finally deposit the poor dielectric layer of filling capacity, form air-gap.But, in order to protect metal connecting line and control effectively to live width, after APF is graphical, need the side wall protection layer forming APF.
Therefore, in order to obtain desirable APF side wall pattern and stable live width, the formation method for side wall that a kind of APF is provided is needed.
Summary of the invention
The object of the invention is to improve above-mentioned prior art; the formation method for side wall of a kind of APF is provided; by introducing one deck sacrifice layer in protective film; the structure and morphology of side wall can be kept and obtain stablizing live width; also can avoid undercutting (undercut) phenomenon simultaneously, be beneficial to subsequent technique and carry out.
For achieving the above object, the invention provides the formation method for side wall of a kind of APF, it comprises the following steps:
Step S01, one silicon chip substrate is provided, and in silicon chip substrate, form barrier layer (barrier layer), inculating crystal layer (seed layer) and APF (Advanced patterning film, advanced graphical film) layer successively;
Step S02, graphical described APF layer, forms groove structure in APF layer;
Step S03, forms protective film on described groove structure surface, and described protective film is covered in the top of groove structure, sidewall and bottom;
Step S04, forms sacrifice layer on described protective film surface;
Step S05, removes sacrifice layer and the protective film of described groove structure top and bottom;
Step S06, removes the sacrifice layer of described groove structure sidewall, forms the protective film side wall of APF.
Further, step S05 is the sacrifice layer and the protective layer that utilize the anisotropy of plasma etching to remove groove structure top and bottom.
Further, step S06 utilizes isotropic high selectivity to etch the sacrifice layer removing groove structure sidewall.
Further, after step S05 completes, protective film is left in the bottom of the sacrifice layer of groove structure sidewall, and the side wall formed after step S06 completes has wide bottom, to avoid undercut phenomenon.
Further, described protective film is selected from SiO
2, SiON, SiO
2/ SiON, SiO
2/ Si
3n
4, SiO
2/ Ta, adopt atom layer deposition process (ALD) to be formed, described sacrifice layer is selected from Si, SiO
2, adopt atom layer deposition process to be formed.
Further, step S05 adopts CF
4, CHF
3etch with the mist of Ar, three's flow is respectively 10 ~ 40sccm, 20 ~ 60sccm and 150 ~ 300sccm.
Further, described sacrifice layer is Si, then step S06 adopts XeF
2release process remove; Described sacrifice layer is SiO
2, then step S06 adopts the release process of HF to remove.
Further, the live width X larger than feature dimension of interest of the groove structure that step S02 is formed, the thickness of the protective film that step S03 is formed is X/2,
Further, described barrier layer is Ta/TaN composite membrane, and adopt physical vapour deposition (PVD) to be formed, described inculating crystal layer is Cu, and adopt physical vapour deposition (PVD) to be formed, described APF layer is hydrogeneous amorphous carbon film, and using plasma enhanced chemical vapor deposition is formed.
Further, the thickness on described barrier layer is
the thickness of described inculating crystal layer is
the thickness of described APF layer is
the thickness of described protective film is
the thickness of described sacrifice layer is
The formation method for side wall of APF provided by the invention; after APF layer forms groove structure; form layer protecting film layer and one deck sacrifice layer successively; remove sacrifice layer and the protective film of groove structure top and bottom subsequently; retain sacrifice layer and the protective film of groove structure sidewall; finally remove the sacrifice layer of groove structure sidewall and reservation protection rete, finally form the APF side wall with protective film sidewall.The present invention, by introducing one deck sacrifice layer in protective film, can keep the structure and morphology of side wall and obtain stable live width, also can avoid undercut phenomenon simultaneously, being conducive to subsequent technique and carrying out.The present invention can be control effectively to result by simple technique adjustment, does not cause obvious impact to process complexity, production cost simultaneously.
Accompanying drawing explanation
For can clearer understanding objects, features and advantages of the present invention, below with reference to accompanying drawing, preferred embodiment of the present invention be described in detail, wherein:
Fig. 1 is the schematic flow sheet of APF formation method for side wall of the present invention;
Fig. 2 to Fig. 7 is each step structural representation of APF formation method for side wall of the present invention.
Embodiment
Refer to Fig. 1, and consult Fig. 2 to Fig. 7 simultaneously, the formation method for side wall of the APF of the present embodiment is mainly applicable to the rear road air-gap formation process of below 28nm technology generations, also can be used for forming the metal voids structure of groove width between 20 ~ 45nm.The present embodiment forms side wall by the groove structure sidewall at APF material, and it comprises the following steps:
Step S01, as shown in Figure 2, provides a silicon chip substrate 100, and in silicon chip substrate 100, forms barrier layer 110, inculating crystal layer 120 and APF layer 130 successively.
Particularly, in the present embodiment, barrier layer 110 is preferably Ta/TaN composite membrane, and adopt physical vapour deposition (PVD) to be formed, thickness is
be preferably in the present embodiment
inculating crystal layer 120 is Cu, and adopt physical vapour deposition (PVD) to be formed, thickness is
be preferably in the present embodiment
aPF layer 130 using plasma enhanced chemical vapor deposition (PECVD) is formed, and this thin film Body components is hydrogeneous amorphous carbon film (a-CxHy), when dry etching to Si, SiO
2, Si
3n
4have comparatively high selectivity, the target thickness of the copper interconnecting line of thickness then needed for technique of APF layer is determined, should, slightly larger than copper interconnecting line thickness, be preferably
be preferably in the present embodiment
Step S02, as shown in Figure 3, graphical APF layer, forms groove structure 135 in APF layer 130 '.
Particularly, in the present embodiment, adopt semiconductor common process to carry out, comprise exposure, development, etching series of process step, in APF layer, form groove structure 135, to fill metal in subsequent technique.Consider that subsequent deposition protective film correspondingly can reduce the width of groove, the groove live width formed in this road patterning process is more bigger than feature dimension of interest
Step S03, as shown in Figure 4, form protective film 140 on groove structure 135 surface, protective film 140 is covered in the top of groove structure 135, sidewall and bottom equably.
Particularly, in the present embodiment, protective film 140 can be single rete or composite film, as SiO
2, SiON, SiO
2/ SiON, SiO
2/ Si
3n
4, SiO
2/ Ta, selects SiO in the present embodiment
2.This protective film deposit thickness is
be preferably
adopt atom layer deposition process (ALD) to be formed, underlayer temperature is 300 ~ 600 DEG C, and reaction power is 200 ~ 600W, and precursors selects BDEAS (two (diethylamino) silane), O
2.
Step S04, as shown in Figure 5, forms sacrifice layer 150 on protective film 140 surface.
Particularly, in the present embodiment, sacrificial layer material selects the type higher with protective film etching selection, so that follow-up removal.In the present embodiment, protective film 140 is SiO
2, sacrifice layer 150 is Si layer, and adopt the atom layer deposition process (ALD) of conformal to be formed, deposit thickness is
be preferably
precursors selects silane (SiH
4), underlayer temperature is 300 ~ 500 DEG C.This silicon atom layer is covered in the surface of protective film.
Step S05, as shown in Figure 6, removes sacrifice layer and the protective film of groove structure 135 top and bottom.
Particularly, in the present embodiment, preferably utilize the anisotropy removal groove structure top of plasma etching, the sacrifice layer of bottom and protective film, and the protective film of sidewall is substantially unaffected, only sacrifice layer part is subject to a small amount of bombardment.Reacting gas selects CF
4, flow is 10 ~ 40sccm, is preferably 20sccm; CHF
3flow is 20 ~ 60sccm, is preferably 40sccm; Ar flow is 150 ~ 300sccm, is preferably 200sccm; Process pressure is 60 ~ 100sccm, is preferably 80sccm; Radio-frequency power is 90 ~ 150W, is preferably 120W.Typical process conditions is adopted to be in the present embodiment: 80sccm/120W/CF
420sccm/CHF
340sccm/Ar 200sccm, this condition can meet anisotropic etching requirement, and sacrifice layer, the protective film etching selection to APF is higher.
Step S06, as shown in Figure 7, removes the sacrifice layer of groove structure 135 sidewall, forms the protective film side wall 140 ' of APF layer 130 '.
Particularly; after side wall has etched; sidewall section comprises protective film, sacrifice layer, and the present embodiment preferably utilizes isotropic high selectivity to etch (as release process) and removes the remaining sacrifice layer of groove structure sidewall, and protective film is substantially unaffected.In the present embodiment, select XeF
2carry out release process, Si sacrifice layer can be removed, and protective film SiO
2substantially unaffected.This technique can make side wall pattern keep uniformity; meanwhile, because protective film is left in the bottom of groove structure sidewall sacrifice layer after completing in step S05, remove sacrifice layer back side wall in this step and there is wide bottom; L-type side wall as shown in Figure 7, can prevent the undercut phenomenon of subsequent technique.So far namely the sidewall structure of APF is formed, and the groove of formation can be used for metallic copper and fills, to form copper interconnecting line.
In other embodiments, technological process is same as the previously described embodiments, and is adjusted accordingly by the material of protective film and sacrifice layer.Protective film is adjusted to SiON, and adopt atom layer deposition process (ALD) to be formed, deposit thickness is
be preferably
sacrifice layer is SiO
2layer, adopt atom layer deposition process (ALD) to be formed, deposit thickness is
be preferably
the etching removal technique of step S05 is same as the previously described embodiments.After side wall etching, release process can adopt gaseous state HF, by SiO
2sacrifice layer is removed.
In sum; the formation method for side wall of the graphical film APF of advanced person provided by the invention by introducing one deck sacrifice layer in protective film; the structure and morphology of side wall can be kept and obtain stable live width, also avoid undercut phenomenon simultaneously, being conducive to subsequent technique and carrying out.The present invention can be control effectively to result by simple technique adjustment, does not cause obvious impact to process complexity, production cost simultaneously.
Claims (10)
- The formation method for side wall of a 1.Ge APF, it is characterized in that, it comprises the following steps:Step S01, provides a silicon chip substrate, and in silicon chip substrate, form barrier layer, inculating crystal layer and APF layer successively;Step S02, graphical described APF layer, forms groove structure in APF layer;Step S03, forms protective film on described groove structure surface, and described protective film is covered in the top of groove structure, sidewall and bottom;Step S04, forms sacrifice layer on described protective film surface;Step S05, removes sacrifice layer and the protective film of described groove structure top and bottom;Step S06, removes the sacrifice layer of described groove structure sidewall, forms the protective film side wall of APF.
- 2. the formation method for side wall of APF according to claim 1, is characterized in that: step S05 is the sacrifice layer and the protective layer that utilize the anisotropy of plasma etching to remove groove structure top and bottom.
- 3. the formation method for side wall of APF according to claim 1, is characterized in that: step S06 utilizes isotropic high selectivity to etch the sacrifice layer removing groove structure sidewall.
- 4. the formation method for side wall of APF according to claim 1, is characterized in that: after step S05 completes, protective film is left in the bottom of the sacrifice layer of groove structure sidewall, and the side wall formed after step S06 completes has wide bottom.
- 5. the formation method for side wall of the APF according to any one of Claims 1-4, is characterized in that: described protective film is selected from SiO 2, SiON, SiO 2/ SiON, SiO 2/ Si 3n 4, SiO 2/ Ta, adopt atom layer deposition process to be formed, described sacrifice layer is selected from Si, SiO 2, adopt atom layer deposition process to be formed.
- 6. the formation method for side wall of APF according to claim 2, is characterized in that: step S05 adopts CF 4, CHF 3etch with the mist of Ar, three's flow is respectively 10 ~ 40sccm, 20 ~ 60sccm and 150 ~ 300sccm.
- 7. the formation method for side wall of APF according to claim 5, is characterized in that: described sacrifice layer is Si, then step S06 adopts XeF 2release process remove; Described sacrifice layer is SiO 2, then step S06 adopts the release process of HF to remove.
- 8. the formation method for side wall of the APF according to any one of Claims 1-4, is characterized in that: the live width X larger than feature dimension of interest of the groove structure that step S02 is formed, and the thickness of the protective film that step S03 is formed is X/2,
- 9. the formation method for side wall of the APF according to any one of Claims 1-4, it is characterized in that: described barrier layer is Ta/TaN composite membrane, employing physical vapour deposition (PVD) is formed, described inculating crystal layer is Cu, employing physical vapour deposition (PVD) is formed, described APF layer is hydrogeneous amorphous carbon film, and using plasma enhanced chemical vapor deposition is formed.
- 10. the formation method for side wall of the APF according to any one of Claims 1-4, is characterized in that: the thickness on described barrier layer is the thickness of described inculating crystal layer is the thickness of described APF layer is 1000 ~ the thickness of described protective film is the thickness of described sacrifice layer is
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510179795.1A CN104867867A (en) | 2015-04-16 | 2015-04-16 | Method for forming side wall of APF (advanced patterning film) |
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|---|---|---|---|
| CN201510179795.1A CN104867867A (en) | 2015-04-16 | 2015-04-16 | Method for forming side wall of APF (advanced patterning film) |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106548977A (en) * | 2016-10-26 | 2017-03-29 | 上海集成电路研发中心有限公司 | A kind of manufacture method of air-gap structure |
| CN109326518A (en) * | 2018-08-17 | 2019-02-12 | 上海华力微电子有限公司 | A method of forming the structure with high aspect ratio figure |
| CN109650326A (en) * | 2018-12-27 | 2019-04-19 | 杭州士兰集成电路有限公司 | MEMS device and its manufacturing method |
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| KR20070098347A (en) * | 2006-03-31 | 2007-10-05 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device having a spacer |
| CN103137554A (en) * | 2011-11-28 | 2013-06-05 | 格罗方德半导体公司 | Method of forming a semiconductor device by suing sacrificial gate electrodes and sacrificial self-aligned contact structures |
| CN104465508A (en) * | 2014-12-30 | 2015-03-25 | 上海集成电路研发中心有限公司 | Forming method for air gap |
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2015
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| KR20070098347A (en) * | 2006-03-31 | 2007-10-05 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device having a spacer |
| CN103137554A (en) * | 2011-11-28 | 2013-06-05 | 格罗方德半导体公司 | Method of forming a semiconductor device by suing sacrificial gate electrodes and sacrificial self-aligned contact structures |
| CN104465508A (en) * | 2014-12-30 | 2015-03-25 | 上海集成电路研发中心有限公司 | Forming method for air gap |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106548977A (en) * | 2016-10-26 | 2017-03-29 | 上海集成电路研发中心有限公司 | A kind of manufacture method of air-gap structure |
| CN106548977B (en) * | 2016-10-26 | 2020-06-09 | 上海集成电路研发中心有限公司 | Manufacturing method of air gap structure |
| CN109326518A (en) * | 2018-08-17 | 2019-02-12 | 上海华力微电子有限公司 | A method of forming the structure with high aspect ratio figure |
| CN109326518B (en) * | 2018-08-17 | 2020-11-03 | 上海华力微电子有限公司 | Method for forming structure with high aspect ratio graph |
| CN109650326A (en) * | 2018-12-27 | 2019-04-19 | 杭州士兰集成电路有限公司 | MEMS device and its manufacturing method |
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