CN107481969B - Through hole forming method - Google Patents
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- CN107481969B CN107481969B CN201710702565.8A CN201710702565A CN107481969B CN 107481969 B CN107481969 B CN 107481969B CN 201710702565 A CN201710702565 A CN 201710702565A CN 107481969 B CN107481969 B CN 107481969B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
The invention provides a method for forming a through hole, which comprises the following steps: providing a semiconductor substrate, and forming a dielectric layer; forming a first mask layer on the dielectric layer, wherein an opening is formed in the first mask layer; covering an etching protective layer on the first mask layer, wherein the etching protective layer covers the side wall of the opening; etching the dielectric layer by taking the first mask layer and the etching protection layer as masks to form a through hole corresponding to the opening in the dielectric layer; and removing the etching protection layer. The method provided by the invention optimizes the problem of abnormal appearance of the first mask layer in the forming process of the through hole, reduces the requirement on etching selection ratio and improves the process feasibility.
Description
Technical Field
The invention relates to a semiconductor preparation process, in particular to a method for forming a through hole.
Background
With the development of integrated circuit technology, the integration level of integrated circuits is increasing continuously, and the size of semiconductor devices is decreasing continuously, which requires more accurate and advanced technology level, especially higher lithography overlay accuracy.
For example, in a damascene process, the lithographic overlay accuracy needs to be strictly controlled to obtain the desired via pattern.
Fig. 1 to 3 are schematic structural diagrams in a damascene process during a process of forming a via hole, as shown in fig. 1 to 3, first, a semiconductor substrate is provided, and a lower dielectric layer 1, a dielectric layer 2 and a mask layer 3 having a first opening 4 are sequentially formed from bottom to top, wherein the first opening 4 forms a trench; then, forming a photoresist layer 5 with a through hole pattern 6 on the dielectric layer 2, wherein the position of the through hole pattern 6 corresponds to the position of the groove, and the size of the through hole pattern 6 is smaller than or equal to the size of the groove; next, the dielectric layer 2 is etched along the via pattern 6 using the photoresist layer 5 as a mask to form a via 7.
However, in the actual process of via hole preparation, the problem of deviation of pattern dimension control often occurs, and the obtained via hole has abnormal morphology. Fig. 4 and 5 are schematic structural diagrams of a through hole formed due to a pattern dimension control deviation in a damascene process, and as shown in fig. 4 and 5, compared with an ideal process flow, due to the pattern dimension control deviation, the dimension of the through hole pattern 6 is larger than that of the first opening 4, so that a part of the mask layer 3 is exposed through the through hole pattern 6, and the exposed mask layer 3 is easily consumed during etching, especially, the side wall position of the first opening 4 in the mask layer 3 is more easily consumed, thereby causing a trench profile abnormality, and further causing a profile abnormality of the formed through hole 7.
Similarly, fig. 6 and 7 are schematic structural diagrams of another through hole formed due to the lithography overlay deviation, as shown in fig. 6 and 7, the lithography overlay deviation causes the center of the through hole pattern 6 not to be aligned with the center of the first opening 4, so that during the etching process, a portion of the mask layer 3 is exposed to the outside to generate loss, which causes the trench profile to be abnormal, and further causes the profile of the formed through hole 7 to be abnormal.
If the morphology of the formed through hole is abnormal, the performance of the whole device is directly affected. Therefore, in the process of preparing the through hole, how to ensure the integrity of the mask layer above the dielectric layer is important to obtain the through hole with a better appearance.
Disclosure of Invention
The invention aims to provide a through hole forming method, which aims to solve the problem that the appearance of a formed through hole is abnormal due to the control deviation of the size of a graph and the photoetching overlay deviation.
In order to solve the above technical problem, the present invention provides a method for forming a through hole, comprising the steps of:
providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate;
forming a first mask layer on the dielectric layer, wherein first openings are formed in the first mask layer;
covering an etching protective layer on at least the side wall of the first opening;
and etching the dielectric layer by taking the first mask layer and the etching protection layer as masks to form a through hole corresponding to the first opening in the dielectric layer.
Optionally, the method for forming the first opening of the first mask layer includes:
sequentially forming a first anti-reflection layer and a patterned first photoresist layer on the first mask layer;
etching the first anti-reflection layer and the first mask layer by taking the patterned first photoresist layer as a mask so as to form the first opening in the first mask layer;
and removing the first anti-reflection layer and the first photoresist layer.
Optionally, the method for etching the dielectric layer to form the through hole includes:
covering a protective material layer on the first mask layer, wherein the protective material layer covers the side wall and the bottom of the first opening;
forming a second mask layer on the protective material layer, wherein a second opening is formed in the second mask layer, the position of the second opening corresponds to the position of the first opening, and in the direction perpendicular to the height direction, the size of the second opening is larger than or equal to that of the first opening;
performing a first etching process to form a groove which corresponds to the first opening and does not penetrate through the dielectric layer in the dielectric layer, removing the part of the protective material layer at the bottom of the first opening, and reserving the part of the protective material layer on the side wall of the first opening to form the etching protective layer;
removing the second mask layer to expose the etching protection layer;
and performing second etching by taking the first mask layer and the etching protection layer as masks, performing second etching on the dielectric layer in the groove, and removing the dielectric layer corresponding to the groove to form the through hole penetrating through the dielectric layer.
Preferably, the second mask layer includes:
a second anti-reflection layer;
a second photoresist layer coated on the second anti-reflection layer.
Optionally, the semiconductor substrate includes:
a substrate;
a lower dielectric layer formed on the substrate;
the metal interconnection line is formed in the lower dielectric layer;
and etching the barrier layer, wherein the barrier layer is formed on the lower dielectric layer and the metal interconnection line.
Optionally, the metal interconnection line is made of copper.
Optionally, the etching barrier layer is a nitrogen-containing silicon carbide layer.
Optionally, the dielectric layer is a low dielectric constant dielectric layer.
Optionally, the dielectric layer includes a fluorine-doped silicon oxide layer.
Optionally, the first mask layer includes a metal hard mask layer.
Optionally, the first mask layer includes a titanium nitride layer.
Preferably, the first mask layer further includes at least one of a buffer layer and a surface protection layer, the buffer layer is formed on the dielectric layer, the titanium nitride layer is formed on the buffer layer, and the surface protection layer is formed on the titanium nitride layer.
Further, in the etching process of etching the dielectric layer to form the through hole, the etching selection ratio of the etching protection layer to the dielectric layer is greater than or equal to 10: 1.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the through hole, before the through hole is etched, the etching protection layers are formed on the top and the side wall of the first mask layer, so that the first mask layer can be effectively protected in the through hole etching process, the loss of the first mask layer is reduced, the integrity of the first opening in the subsequent etching process is guaranteed, and further, when the through hole defined by the first opening in the first mask layer is utilized, the appearance of the formed through hole can be correspondingly guaranteed. Meanwhile, compared with the traditional through hole forming process, the method has the advantages that the requirement on the etching selection ratio of the dielectric layer to the hard mask layer is reduced, the difficulty of the etching process is greatly reduced, and the feasibility of the process is improved.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams in a process of fabricating a via in a damascene process;
FIGS. 4 and 5 are schematic structural diagrams of a via hole formed due to deviation of pattern dimension control in a damascene process;
FIGS. 6 and 7 are schematic structural diagrams of a via hole formed in a damascene process due to lithographic overlay deviation;
FIG. 8 is a flowchart illustrating a method for forming a via hole according to a first embodiment of the present invention;
fig. 9 to 13 are schematic structural diagrams illustrating a method for forming a via hole according to a first embodiment of the present invention during a manufacturing process thereof;
fig. 14 to 17 are schematic structural diagrams illustrating a method for forming a via hole according to a second embodiment of the present invention during a manufacturing process thereof.
Detailed Description
As described in the background, the difficulty of photolithography is increasing with the ever-decreasing feature sizes.
In the forming process of the through hole, firstly, the etching selection ratio of the material of the dielectric layer to the material of the hard mask layer cannot reach infinity, and secondly, the formed through hole is abnormal in appearance due to the problems of pattern size control deviation, photoetching alignment deviation and the like.
Therefore, the invention provides a method for forming a through hole, which comprises the following steps:
providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate;
forming a first mask layer on the dielectric layer, wherein a first opening is formed in the first mask layer;
covering an etching protective layer on at least the side wall of the first opening;
and etching the dielectric layer by taking the first mask layer and the etching protection layer as masks to form a through hole corresponding to the first opening in the dielectric layer.
According to the forming method of the through hole, the first mask layer is protected by the etching protection layer, the first mask layer is prevented from being damaged by etching, the appearance abnormality of the first opening in the first mask layer is avoided, and therefore the integrity of the formed through hole can be guaranteed.
The method for forming the through hole according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
FIG. 8 is a flow chart illustrating a method for forming a via hole according to a first embodiment of the present invention; fig. 9 to 13 are schematic structural diagrams illustrating a method for forming a via hole in a manufacturing process according to a first embodiment of the invention. An embodiment of the present invention will be described in detail below with reference to fig. 8 to 13.
First, step S101 is performed, and referring to fig. 9, a semiconductor substrate 100 is provided, and a dielectric layer 101 is formed thereon. Optionally, the material of the dielectric layer 101 includes a low dielectric constant material, such as a material having a dielectric constant less than 3.9 and not less than 2.55. Further, the material of the dielectric layer 101 may be a silicon dioxide-based material, such as carbon-doped silicon oxide or fluorine-doped silicon oxide, and in this embodiment, the material of the dielectric layer 101 is fluorine-doped silicon oxide. Alternatively, the dielectric layer 101 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like. Preferably, the silicon dioxide-based dielectric layer 101 with a low dielectric constant can be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which can further reduce the dielectric constant of the material.
Next, step S102 is executed, and with continued reference to fig. 9 and 10, a first mask layer 102 is formed on the dielectric layer, where a first opening 108 is formed in the first mask layer 102. Optionally, the first mask layer 102 material includes a non-metal hard mask material, such as silicon nitride and silicon oxide, and the first mask layer 102 material may also include a metal hard mask material, such as titanium nitride and tantalum nitride. Alternatively, the first mask layer 102 may be formed using Physical Vapor Deposition (PVD).
Specifically, the method for forming the first opening 108 of the first mask layer 102 includes:
the first step, spin-coating a first anti-reflection layer and a first photoresist layer on the first mask material layer in sequence;
a second step of performing an exposure and development process to pattern the first photoresist layer;
a third step of etching the first anti-reflection layer and the first mask material layer by using the first photoresist layer as a mask to form the opening 108;
in the fourth step, the first anti-reflection layer 103 and the first photoresist layer 104 may be removed by an ashing process.
Next, step S103 is executed, referring to fig. 10, 11 and 12, an etching protection layer 105 is covered on the first mask layer 102, and the etching protection layer 105 covers the sidewalls of the opening 108. The etching protection layer includes a film layer having an etching selection ratio of greater than 10:1 with respect to the dielectric layer, and the dielectric layer 101 is made of fluorine-doped silicon oxide in this embodiment, so that the etching protection layer 105 may be formed of silicon nitride.
As described above, since the etching selection ratio between the dielectric layer and the first mask layer is relatively close, for example, the etching selection ratio between the dielectric layer and the first mask layer is less than 10:1, when the dielectric layer is etched by directly using the first mask layer as a mask, the first mask layer is easily consumed, and the appearance of the through hole formed in the dielectric layer is abnormal. In this embodiment, the etching protection layer 106 with a large etching selection ratio is selected according to the material of the dielectric layer 101, so that the problem that the first mask layer is consumed in a large amount in the etching process is effectively solved.
The etching protection layer 106 may utilize a chemical vapor deposition process and a back etching process, specifically: a Chemical Vapor Deposition (CVD) may be selected to deposit an etching protection layer 105, and then the etching protection layer 105 is etched back by a dry method, so as to expose the bottom of the opening 108 of the first mask layer 102 and retain the portion of the etching protection layer 105 located on the side wall of the opening, so that the formed etching protection layer 106 covers the side wall of the opening 108 of the first mask layer 102, thereby protecting the first mask layer 102.
Next, step S104 is executed, referring to fig. 12 and 13, with the first mask 102 and the etching protection layer 106 as masks, the dielectric layer 101 is etched to form a through hole 107 corresponding to the opening 108 in the dielectric layer 101. Specifically, the Etching method may be Reactive Ion Etching (RIE) in dry Etching, for example, to ensure that the film has anisotropy and high selectivity. The etching protection layer can play a role in preventing the first mask layer from being etched transversely, so that the appearance of the through hole 107 is ensured.
Finally, step S105 is executed, and with continued reference to fig. 10 and fig. 11, the remaining etching protection layer 106 is removed, specifically, an etching method with better isotropy in dry etching may be selected for removal.
Example two
In this embodiment, the forming method of the through hole is applied to a damascene process, so as to further describe the forming method of the through hole provided by the present invention in detail. Fig. 14 to 17 are schematic structural diagrams of a method for forming a via hole in a second embodiment of the present invention during a manufacturing process thereof. An embodiment of the present invention will be described in detail below with reference to fig. 14 to 17.
First, step S201 is executed, and referring to fig. 14 in particular, a semiconductor substrate (not shown in the figure) is provided, wherein a lower dielectric layer 200, an etching stop layer 202 and a dielectric layer 203 are formed on the semiconductor substrate in sequence. And a metal interconnection line 201 can be buried in the lower dielectric layer 200 at the junction with the etching barrier layer 202. Specifically, the metal of the metal interconnection line 201 is, for example, copper, and the etch stop layer 202 is, for example, a nitrogen-containing silicon carbide (NDC) layer.
Further, the dielectric layer 203 is, for example, a porous SiOCH layer or a fluorine-doped silicon oxide layer. Optionally, the lower dielectric layer 200, the etch stop layer 202, and the dielectric layer 203 may be formed by a chemical vapor deposition process, which is not described in detail herein. Preferably, the metal interconnection line 201 may be formed using a physical vapor deposition method.
Next, step S202 is executed, and with reference to fig. 14, a first mask layer is formed on the dielectric layer 203, and a first opening 210 is formed in the first mask layer.
The first mask layer may have a single-layer structure or a multi-layer structure. For example, the first mask layer includes a metal hard mask layer 205, and in this embodiment, the first mask layer is a multilayer structure and further includes a buffer layer 204 and/or a surface protection layer 206. And, the buffer layer 204 is formed on the dielectric layer 203, the titanium nitride layer 205 is formed on the buffer layer 204, and the surface protection layer 206 is formed on the titanium nitride layer 205.
Specifically, the material of the metal hard mask layer 205 is, for example, Ta, Ti, TaN, or TiN. In this embodiment, the metal hard mask layer 205 is a titanium nitride layer; the buffer layer 204 is a Tetraethylorthosilicate (TEOS) layer and can be used as a stress buffer layer between the metal hard mask layer 205 and the dielectric layer 203 which are formed subsequently; the surface protection layer 206 is a silicon oxide layer, and can prevent the metal hard mask layer from being exposed to air to generate an oxidation reaction. The buffer layer 204, the metal hard mask layer 205, and the surface protection layer 206 may be formed by chemical vapor deposition. Preferably, the metal hard mask layer 205 may be formed by physical vapor deposition.
In this embodiment, a first opening 210 is formed in the first mask layer, and the forming method includes:
firstly, a first anti-reflection layer 207 and a first photoresist layer 208 are sequentially coated, and the first photoresist layer 208 is patterned to form a pattern corresponding to a first opening 210;
the formation of the anti-reflection layer can eliminate the reflection phenomenon of a light source, and avoid the condition that the exposure light source is easy to reflect on the surface of a semiconductor substrate due to the fact that the semiconductor substrate (comprising a metal layer and a dielectric layer) below the photoresist has a high reflection coefficient, so that the deformation or the size deviation of a photoresist graph is caused, and the graph of a mask plate is incorrectly transferred;
then, the patterned first photoresist layer 208 is used as a mask to etch the first anti-reflection layer 207 and the first mask layer, so as to form the first opening 210;
specifically, the first anti-reflection layer 207, the surface protection layer 206, the metal hard mask layer 205 and the buffer layer 204 may be etched by using a dry etching process, where the etching is stopped in the buffer layer 204.
Next, step S203 is executed, and referring to fig. 15, an etching protection layer 219 covers at least the sidewalls of the first opening 210 to protect the metal hard mask in the first mask layer. In this embodiment, the etching protection layer 219 not only covers the sidewall of the first opening 210, but also covers the top of the first mask layer.
Preferably, an etching protection layer 219 with a larger etching selection ratio to the dielectric layer is formed on the first mask layer, so as to prevent the metal hard mask layer in the first mask layer from being damaged by etching.
In this embodiment, the metal hard mask layer 205 is a titanium nitride layer, and the dielectric layer 203 is a fluorine-doped silicon oxide layer, so that the etching protection layer 219 is a silicon nitride layer having a larger etching selectivity with silicon oxide. The etching protection layer 219 may be formed by a chemical vapor deposition process, such as low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.
Next, step S204 is executed, and referring to fig. 15 to 17, the dielectric layer 203 is etched by using the first mask layer and the etching protection layer 219 as masks, so as to form a through hole 211 corresponding to the first opening 210 in the dielectric layer 203.
In this embodiment, the through hole 211 is formed by a two-step etching process, and the etching protection layer 219 is formed simultaneously by combining the two-step etching process, which specifically includes the steps of:
a first step of covering a protective material layer 209 on the first mask layer, wherein the protective material layer 209 covers the side wall and the bottom of the first opening 210;
a second step of forming a second mask layer on the protective material layer 209, wherein a second opening 212 is formed in the second mask layer, the position of the second opening 212 corresponds to the position of the first opening, and the size of the second opening 212 is greater than or equal to the size of the first opening 210 in the direction perpendicular to the height direction;
specifically, the second mask layer is, for example, a photoresist layer, in this embodiment, with a preferable scheme, the second mask layer includes a second anti-reflection layer 217 and a second photoresist layer 218, the second anti-reflection layer 217 is formed on the protection material layer 209, and the second photoresist layer 218 is formed on the second anti-reflection layer 217; and the second photoresist layer 218 is a patterned photoresist layer, the second opening 212 is formed in the second photoresist layer 218;
a third step of performing a first etching process to form a trench in the dielectric layer 203, the trench corresponding to the first opening 210 and not penetrating through the dielectric layer 203, and simultaneously removing a portion of the protective material layer 209 at the bottom of the first opening 210 and leaving a portion of the protective material layer 209 at the sidewall of the first opening 210 to form an etching protection layer 219;
in this embodiment, the portion of the protection material layer 209 above the first mask layer is also covered with the second mask layer, so that, in the first etching process, the portion of the protection material layer 209 above the first mask layer is retained and forms an etching protection layer 219 together with the protection material layer on the sidewall of the first opening 210.
Specifically, the etching method may be dry etching such as Reactive Ion Etching (RIE), which is a dry etching technique between sputter etching and plasma etching and has the advantages of anisotropic etching and high selectivity. The etching process may also cause the portion of the surface protection layer 206 exposed in the second opening to be etched away;
a fourth step of removing the second mask layer to expose the etching protection layer 219;
in this embodiment, the second anti-reflection layer 217 and the second photoresist layer 218 may be removed by ashing;
and fifthly, performing second etching by taking the first mask layer and the etching protection layer 219 as masks, performing second etching on the dielectric layer 203 in the groove, and removing the dielectric layer 203 in the groove to form the through hole 211 penetrating through the dielectric layer 203.
Specifically, the etching method can adopt deep reactive ion etching in a dry etching process, and the control on lateral etching is more excellent.
In summary, in the method for forming a through hole provided by the present invention, an etching protection layer with a high selectivity to a dielectric layer is deposited on the first mask layer, and further, in the through hole etching process, the integrity of the first mask layer is effectively protected, thereby optimizing the problem of abnormal trench morphology of the through hole due to pattern size control deviation and lithography overlay deviation. Furthermore, the difficulty brought by the reduction of the key size to the subsequent reliability test can be solved, and the potential risk of metal short circuit brought by the photoetching overlay deviation to the rear section is also solved, so that the Damascus structure is greatly improved.
In addition, in the aspect of the etching process, compared with the traditional etching process, the requirement on the etching selection ratio of the material of the dielectric layer to the material of the first mask layer is reduced, so that the difficulty of the etching process is greatly reduced, the process feasibility is better, the range of applicable machines is greatly enlarged, and favorable conditions are provided for mass production.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A method for forming a via hole, comprising:
providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate;
forming a first mask layer on the dielectric layer, wherein a first opening is formed in the first mask layer;
covering an etching protective layer on at least the side wall of the first opening;
etching the dielectric layer by taking the first mask layer and the etching protection layer as masks to form a through hole corresponding to the first opening in the dielectric layer; in the etching process of etching the dielectric layer to form the through hole, the etching selection ratio of the etching protection layer to the dielectric layer is greater than or equal to 10: 1;
the method for etching the dielectric layer to form the through hole comprises the following steps:
covering a protective material layer on the first mask layer, wherein the protective material layer covers the side wall and the bottom of the first opening;
forming a second mask layer on the protective material layer, wherein a second opening is formed in the second mask layer, the position of the second opening corresponds to the position of the first opening, and in the direction perpendicular to the height direction, the size of the second opening is larger than or equal to that of the first opening;
performing a first etching process to form a groove which corresponds to the first opening and does not penetrate through the dielectric layer in the dielectric layer, removing the part of the protective material layer at the bottom of the first opening, and reserving the part of the protective material layer on the side wall of the first opening to form the etching protective layer;
removing the second mask layer to expose the etching protection layer;
and performing second etching by taking the first mask layer and the etching protection layer as masks, performing second etching on the dielectric layer in the groove, and removing the dielectric layer corresponding to the groove to form the through hole penetrating through the dielectric layer.
2. The method for forming a via according to claim 1, wherein the method for forming the first opening of the first mask layer comprises:
sequentially forming a first anti-reflection layer and a patterned first photoresist layer on the first mask layer;
etching the first anti-reflection layer and the first mask layer by taking the patterned first photoresist layer as a mask so as to form the first opening in the first mask layer;
and removing the first anti-reflection layer and the first photoresist layer.
3. The method according to claim 1, wherein the second mask layer comprises:
a second anti-reflection layer;
and the second photoresist layer is coated on the second anti-reflection layer.
4. The method for forming a via according to claim 1, wherein the semiconductor substrate comprises:
a substrate;
a lower dielectric layer formed on the substrate;
the metal interconnection line is formed in the lower dielectric layer;
and etching the barrier layer, wherein the barrier layer is formed on the lower dielectric layer and the metal interconnection line.
5. The method for forming a via according to claim 4, wherein the metal interconnection line is made of copper.
6. The method according to claim 4, wherein the etch stop layer is a nitrogen-containing silicon carbide layer.
7. The method of claim 1, wherein the dielectric layer is a low-k dielectric layer.
8. The method of claim 7, wherein the dielectric layer comprises a fluorine doped silicon oxide layer.
9. The method of claim 1, wherein the first mask layer comprises a metal hard mask layer.
10. The method of claim 9, wherein the first mask layer comprises a titanium nitride layer.
11. The method for forming a via according to claim 10, wherein the first mask layer further comprises at least one of a buffer layer and a surface protection layer, the buffer layer is formed on the dielectric layer, the titanium nitride layer is formed on the buffer layer, and the surface protection layer is formed on the titanium nitride layer.
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| CN111162082B (en) * | 2020-01-02 | 2022-05-27 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111430361B (en) * | 2020-04-09 | 2023-07-25 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111430362B (en) * | 2020-04-09 | 2023-07-25 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111933581B (en) * | 2020-09-25 | 2020-12-22 | 南京晶驱集成电路有限公司 | Preparation method of semiconductor structure |
| CN116759384B (en) * | 2023-08-17 | 2023-11-03 | 长电集成电路(绍兴)有限公司 | Wiring layer, preparation method thereof and packaging structure |
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| CN103337476A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Method for reducing critical size of copper interconnection groove |
| CN106972003A (en) * | 2015-12-17 | 2017-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
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| CN103337476A (en) * | 2013-06-27 | 2013-10-02 | 上海华力微电子有限公司 | Method for reducing critical size of copper interconnection groove |
| CN106972003A (en) * | 2015-12-17 | 2017-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
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