KR100887019B1 - Mask having multi overlay mark - Google Patents

Mask having multi overlay mark Download PDF

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KR100887019B1
KR100887019B1 KR1020070056567A KR20070056567A KR100887019B1 KR 100887019 B1 KR100887019 B1 KR 100887019B1 KR 1020070056567 A KR1020070056567 A KR 1020070056567A KR 20070056567 A KR20070056567 A KR 20070056567A KR 100887019 B1 KR100887019 B1 KR 100887019B1
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mask
overlay marks
insulating film
contact holes
interlayer insulating
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KR1020070056567A
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Korean (ko)
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KR20080108690A (en
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문주형
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/66—Containers specially adapted for masks, mask blanks or pellicles; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다중 오버레이 마크를 갖는 마스크에 관한 것으로, 스크라이브 라인 내에서 동일 간격으로 서로 이격되게 형성되는 다수 개의 오버레이 마크를 마련하고, 상기 다중 오버레이 마크를 갖는 마스크를 이용하여 층간 절연막을 식각하여 다중 콘택 홀을 형성하며, 층간 절연막이 형성된 다중 콘택 홀 내에 갭필 금속층을 충진한 후 갭필 금속층을 연마하는 것을 특징으로 한다. 이때, 본 실시예에 따른 다중 오버레이 마크는 칩 영역 내의 콘택 홀과 동일한 디자인 룰이 적용되는 것을 특징으로 한다. 본 발명에 의하면, 다중의 오버레이 마크를 갖는 마스크로 절연막을 식각하여 다중 콘택 홀을 형성시킨 후 텅스텐 충진 및 CMP 공정을 진행함으로써, 실제 칩 내부의 콘택 홀과 동일한 디자인 룰이 적용되어 추후 보이드(void)와 디싱(dishing)에 의한 오버레이 마크의 변형을 최소화할 수 있다.The present invention relates to a mask having multiple overlay marks, comprising a plurality of overlay marks formed to be spaced apart from each other at equal intervals in a scribe line, and etching the interlayer insulating film using the mask having the multiple overlay marks to etch multiple contacts. The hole is formed, and the gap fill metal layer is filled into the contact hole in which the interlayer insulating film is formed, and then the gap fill metal layer is polished. In this case, the multiple overlay marks according to the present embodiment are characterized in that the same design rule as that of the contact hole in the chip area is applied. According to the present invention, by forming a plurality of contact holes by etching the insulating film with a mask having a plurality of overlay marks and proceeds tungsten filling and CMP process, the same design rules as the actual contact holes in the chip is applied to the void (void) ) And deformation of the overlay mark due to dishing can be minimized.

오버레이 마크, 콘택 홀 Overlay Marks, Contact Holes

Description

다중 오버레이 마크를 갖는 마스크{MASK HAVING MULTI OVERLAY MARK}Mask with multiple overlay marks {MASK HAVING MULTI OVERLAY MARK}

도 1a 내지 도 1d는 종래의 오버레이 마크를 갖는 마스크를 이용한 금속배선 제조 과정을 나타낸 공정 단면도,1A through 1D are cross-sectional views illustrating a process of manufacturing metal wiring using a mask having a conventional overlay mark;

도 2a 및 도 2b는 종래의 오버레이 마크를 갖는 마스크와 본 발명에 따른 다중 오버레이 마크를 갖는 마스크를 각각 비교 도시한 도면,2A and 2B show comparisons between a mask having a conventional overlay mark and a mask having multiple overlay marks according to the present invention, respectively;

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따라 다중 오버레이 마크를 갖는 마스크를 이용하여 금속배선을 제조하는 과정을 예시한 공정 단면도.3A to 3D are cross-sectional views illustrating a process of manufacturing metallization using a mask having multiple overlay marks in accordance with a preferred embodiment of the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

300 : 반도체 기판300: semiconductor substrate

302 : 층간 절연막302: interlayer insulating film

304 : 갭필 금속층304: gap fill metal layer

본 발명은 오버레이 마크 및 금속배선 제조 기술에 관한 것으로, 특히 보이드(void) 및 디싱(dishing)을 방지하는데 적합한 다중 오버레이 마크를 갖는 마스크에 관한 것이다.FIELD OF THE INVENTION The present invention relates to overlay marks and metal fabrication techniques, and more particularly to masks having multiple overlay marks suitable for preventing voids and dishing.

반도체 소자의 고집적화가 진행됨에 따라 소자의 크기를 축소시키는 것 이외에도 소자의 성능을 향상시키기 위한 연구가 진행되고 있다. 현재 대부분의 반도체장치의 배선 공정은 단일 배선만으로는 고집적 소자의 동작시 요구되는 신호를 신속하게 전달하는데 어려움이 있기 때문에 이를 극복하기 위하여 다층 배선구조를 채택하고 있다.As the integration of semiconductor devices increases, research has been conducted to improve device performance in addition to reducing the size of the device. Currently, the wiring process of most semiconductor devices employs a multi-layered wiring structure in order to overcome this problem because it is difficult to quickly transmit a signal required for the operation of the highly integrated device using only a single wiring.

또한, 반도체 소자의 다층 금속배선 제조 공정에서는, 트랜지스터와 금속배선 또는 금속배선 사이의 연결을 위해 텅스텐(W) 플러그 공정이 흔히 사용되며, 텅스텐 플러그 공정은 PMD 또는 IMD 층을 적층한 후 콘택 홀을 패터닝하고 텅스텐 증착과 CMP(Chemical Mechanical Polishing)를 통해 후속 금속배선과의 연결을 준비하는 일련의 과정으로 이루어진다.In addition, a tungsten (W) plug process is commonly used in a multi-layer metallization manufacturing process of a semiconductor device for connection between a transistor and a metallization or a metallization, and a tungsten plug process is formed by stacking PMD or IMD layers, Patterning and tungsten deposition and chemical mechanical polishing (CMP) are a series of steps to prepare for subsequent metallization.

도 1a 내지 도 1d는 이와 같은 금속배선 제조 과정을 예시한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a metal wire manufacturing process.

먼저, 도 1a에서와 같이, 하부 금속배선(도시 생략됨)이 형성된 반도체 기판(100)의 구조물에 층간 절연막(102)을 형성한 후, 도 1b와 같이 상기 층간 절연막(102)을 식각하여 콘택이나 비아 영역을 형성한다. 도 1b에서 도면부호 100' 및 102'는 식각 처리된 이후의 반도체 기판 및 층간 절연막을 각각 나타낸다.First, as shown in FIG. 1A, an interlayer insulating film 102 is formed on a structure of a semiconductor substrate 100 on which a lower metal wiring (not shown) is formed, and then the interlayer insulating film 102 is etched as shown in FIG. To form an in-via region. In FIG. 1B, reference numerals 100 ′ and 102 ′ denote the semiconductor substrate and the interlayer insulating film after etching.

이후, 상기 층간 절연막(102') 전면에 장벽 금속막으로서 TiN(도시 생략됨)을 증착한 다음, 장벽 금속막이 형성된 콘택이나 비아홀에 갭필 금속층(104)으로서 텅스텐(W)을 채워 넣는다.Thereafter, TiN (not shown) is deposited as a barrier metal film on the entire surface of the interlayer insulating film 102 ', and then tungsten (W) is filled as a gap fill metal layer 104 in a contact or via hole in which the barrier metal film is formed.

그런 다음, 도 1c에서와 같이, 장벽 금속막 표면이 드러날 때까지 갭필 금속층(104)을 전면 식각하여 콘택이나 비아를 형성한다.Then, as shown in FIG. 1C, the gapfill metal layer 104 is etched entirely until the barrier metal film surface is exposed to form contacts or vias.

그리고 도 1d에서는, CMP 공정을 진행 후 그 결과물 위에 상부 금속배선(도시 생략됨)을 형성한다.In FIG. 1D, the upper metal wiring (not shown) is formed on the resultant after the CMP process.

이때, 후속 리소그라피 공정을 위하여 오버레이 마크를 동시에 패터닝하게 되는데, 종래에 사용되던 오버레이 마크는 실제 칩 내부의 콘택 홀들과 달리 ㎛ 단위의 패턴이기 때문에 텅스텐 증착시 보이드가 생성되기 쉽고, 텅스텐 CMP 시에도 디싱 등에 의해 패턴 변형이 쉽게 일어난다. 즉, 도 1d에 도시한 바와 같이, 갭필 금속층인 텅스텐을 증착하고 나서 CMP 공정을 진행하는 경우, 패턴이 ㎛ 단위이기 때문에 단차가 발생할 수 있으며, 이러한 단차로 인해 콘택 홀과 패턴이 제대로 구분되지 못하여 정확한 오버레이 데이터를 수집할 수 없다는 문제가 제기되었다.At this time, the overlay mark is simultaneously patterned for the subsequent lithography process. Since the overlay mark used in the prior art is a pattern of μm unlike the actual contact holes inside the chip, voids are easily generated during tungsten deposition and dishing even during tungsten CMP. Pattern deformation easily occurs due to such a condition. That is, as shown in FIG. 1D, when the CMP process is performed after depositing tungsten, the gapfill metal layer, a step may occur because the pattern is in μm, and the step may not properly distinguish the contact hole from the pattern. The issue has been raised that it is not possible to collect accurate overlay data.

본 발명은 상술한 종래 기술의 문제를 해결하기 위한 것으로, 후속 금속배선의 리소그라피 공정에서의 정확한 오버레이 마크 인식을 가능하게 하는 다중 오버레이 마크를 갖는 마스크를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to provide a mask having multiple overlay marks which enables accurate overlay mark recognition in a subsequent lithography process of metallization.

삭제delete

본 발명의 목적을 달성하기 위한 일 관점에 따르면, 웨이퍼 상의 칩 영역을 한정하는 스크라이브 라인 내에서 동일 간격으로 서로 이격되게 형성되는 다수 개의 오버레이 마크를 포함하는 마스크를 제공한다.According to one aspect for achieving the object of the present invention, there is provided a mask including a plurality of overlay marks formed spaced apart from each other at equal intervals in a scribe line defining a chip region on a wafer.

본 발명의 목적을 달성하기 위한 다른 관점에 따르면, 다중 오버레이 마크를 갖는 마스크를 이용한 금속배선 제조 방법으로서, 반도체 기판의 구조물에 층간 절연막을 형성하는 단계와, 상기 마스크로 상기 층간 절연막을 식각하여 다중 콘택 홀을 형성하는 단계와, 상기 층간 절연막이 형성된 다중 콘택 홀 내에 갭필 금속층을 충진한 후 상기 갭필 금속층을 연마하는 단계를 포함하는 다중 오버레이 마크를 갖는 마스크를 이용한 금속배선 제조 방법을 제공한다.According to another aspect for achieving the object of the present invention, a method for manufacturing a metal wiring using a mask having multiple overlay marks, forming an interlayer insulating film on the structure of the semiconductor substrate, and etching the interlayer insulating film with the mask And forming a contact hole, and filling a gap fill metal layer in the multiple contact hole where the interlayer insulating film is formed, and then polishing the gap fill metal layer.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

먼저, 도 2a 및 도 2b는 종래의 오버레이 마크를 갖는 마스크와 본 발명에 따른 다중 오버레이 마크를 갖는 마스크를 각각 비교 도시한 도면이다.First, FIGS. 2A and 2B show comparisons between a mask having a conventional overlay mark and a mask having multiple overlay marks according to the present invention.

도 2b에서 알 수 있듯이, 본 실시예에 적용되는 다중 오버레이 마크(202b)는 기존의 오버레이 마크(202a)에 비해 디자인 룰이 축소되었으며, 이는 칩 영역 내의 콘택 홀과 동일한 디자인 룰, 예컨대 0.22㎛급의 디자인 룰이 적용되는 것을 특징으로 한다.As it can be seen in Figure 2b, the multiple overlay mark 202b applied to this embodiment has a reduced design rule compared to the existing overlay mark 202a, which is the same design rule as the contact hole in the chip area, for example, 0.22㎛ class Characterized in that the design rule is applied.

즉, 도 2b에 도시한 바와 같이, 본 실시예에 따른 오버레이 마크(202b)는, 웨이퍼 상의 칩 영역을 한정하는 스크라이브 라인 내에서 동일 간격으로 서로 이격되게 다수 개 형성되는 것을 특징으로 하며, 도 2a와 같은 단일의 1∼2㎛급 디자인 룰에 비해 다중의 0.22㎛급 디자인 룰이 적용될 수 있다.That is, as shown in Fig. 2b, the overlay mark 202b according to the present embodiment is characterized in that a plurality of spaced apart from each other at equal intervals in the scribe line defining the chip area on the wafer, Fig. 2a Multiple 0.22㎛ class design rules may be applied as compared to a single 1-2 μm class design rule.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따라 도 2b의 다중 오버레이 마크를 갖는 마스크를 이용하여 금속배선을 제조하는 과정을 예시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a process of manufacturing a metal wiring using a mask having multiple overlay marks of FIG. 2B according to a preferred embodiment of the present invention.

먼저, 도 3a에서와 같이, 하부 금속배선(도시 생략됨)이 형성된 반도체 기판(300)의 구조물에 층간 절연막(302)을 형성한 후, 도 3b와 같이 상기 다중 오버레이 마크(202b)를 갖는 마스크(200b)를 이용하여 상기 층간 절연막(302)을 식각하여 다중 콘택 홀 영역을 형성한다. 이때, 각각의 콘택 홀은 0.22㎛의 패턴 크기를 갖는 것을 특징으로 한다. 이와 같은 패턴 크기는 실제 칩 내부의 콘택 홀과 동일한 디자인 룰이 적용되는 것으로서, 종래의 1 내지 2㎛ 패턴 크기와는 명백한 차이가 있음을 알 수 있다.First, as shown in FIG. 3A, an interlayer insulating layer 302 is formed on a structure of a semiconductor substrate 300 on which a lower metal wiring (not shown) is formed, and then a mask having the multiple overlay marks 202b as shown in FIG. 3B. The interlayer insulating layer 302 is etched using 200b to form multiple contact hole regions. At this time, each contact hole is characterized by having a pattern size of 0.22㎛. This pattern size is applied to the same design rules as the actual contact hole inside the chip, it can be seen that there is a clear difference from the conventional 1 to 2㎛ pattern size.

또한, 도 3b에서 도면부호 300' 및 302'는 각각 다중 식각 처리된 이후의 반도체 기판 및 층간 절연막을 나타낸다.3B, reference numerals 300 ′ and 302 ′ denote semiconductor substrates and interlayer insulating films after multiple etching processes, respectively.

이후, 도 3c에서와 같이, 상기 다중 콘택 홀 영역이 형성된 층간 절연막(302') 전면에 갭필 금속층(304)으로서 텅스텐(W)을 충진한다.Thereafter, as shown in FIG. 3C, tungsten (W) is filled as a gap fill metal layer 304 on the entire surface of the interlayer insulating layer 302 ′ in which the multiple contact hole regions are formed.

그런 다음 도 3d에서는, CMP 공정을 진행하여 갭필 금속층(304)과 층간 절연막(302')의 일부를 제거한 후, 그 결과물 위에 상부 금속배선(도시 생략됨)을 형성한다. 도 3d에서 도면부호 302'' 및 304'는 CMP 공정에 의해 연마 처리된 이후의 층간 절연막 및 갭필 금속층을 각각 나타낸다.In FIG. 3D, a CMP process is performed to remove a portion of the gap fill metal layer 304 and the interlayer insulating layer 302 ′, and then an upper metal wiring (not shown) is formed on the resultant. In FIG. 3D, reference numerals 302 ″ and 304 ′ denote interlayer insulating films and gap fill metal layers, respectively, after polishing by the CMP process.

이상과 같이, 본 발명은 다중의 오버레이 마크를 갖는 마스크로 절연막을 식각하여 다중 콘택 홀을 형성시킨 후 텅스텐 충진 및 CMP 공정을 진행함으로써, 실 제 칩 내부의 콘택 홀과 동일한 디자인 룰이 적용되도록 구현한 것이다.As described above, the present invention is implemented by etching the insulating film with a mask having multiple overlay marks to form multiple contact holes and then performing tungsten filling and CMP processes to apply the same design rules as the actual contact holes inside the chip. It is.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주 내에서 당업자에 의해 여러 가지 변형이 가능함은 물론이다.Meanwhile, the present invention is not limited to the above-described embodiments, but various modifications are possible by those skilled in the art within the technical spirit and scope of the present invention described in the claims below.

본 발명에 의하면, 다중의 오버레이 마크를 갖는 마스크로 절연막을 식각하여 다중 콘택 홀을 형성시킨 후 텅스텐 충진 및 CMP 공정을 진행함으로써, 실제 칩 내부의 콘택 홀과 동일한 디자인 룰이 적용되어 추후 보이드와 디싱에 의한 오버레이 마크의 변형을 최소화할 수 있다.According to the present invention, by etching an insulating film with a mask having multiple overlay marks to form multiple contact holes, and then performing tungsten filling and CMP processes, the same design rules as those of the actual contact holes inside the chip are applied, and later voiding and dishing are performed. It is possible to minimize the deformation of the overlay mark by.

Claims (5)

웨이퍼 상의 칩 영역을 한정하는 스크라이브 라인 내에 형성되는 오버레이 마크를 포함하는 마스크로서,A mask comprising overlay marks formed in a scribe line defining a chip region on a wafer, the mask comprising: 상기 오버레이 마크는 층간 절연막을 식각하여 형성한 복수의 콘택 홀을 동일한 간격으로 이격되게 형성한, 디자인 룰이 축소된 다중 오버레이 마크를 포함하되,The overlay mark includes a plurality of overlay marks with reduced design rules formed by forming a plurality of contact holes formed by etching the interlayer insulating film spaced apart at equal intervals, 상기 복수의 콘택 홀은 각각 상기 칩 영역 내의 콘택 홀과 동일한 디자인 룰이 적용되는 것을 특징으로 하는 마스크.The plurality of contact holes are masks, characterized in that the same design rules as the contact holes in the chip region is applied. 삭제delete 삭제delete 삭제delete 삭제delete
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000042842A (en) * 1998-12-28 2000-07-15 김영환 Overlay mark of semiconductor device
KR20020045744A (en) * 2000-12-11 2002-06-20 박종섭 Overlay mark in semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000042842A (en) * 1998-12-28 2000-07-15 김영환 Overlay mark of semiconductor device
KR20020045744A (en) * 2000-12-11 2002-06-20 박종섭 Overlay mark in semiconductor device

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