CN107481969A - A kind of forming method of through hole - Google Patents
A kind of forming method of through hole Download PDFInfo
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- CN107481969A CN107481969A CN201710702565.8A CN201710702565A CN107481969A CN 107481969 A CN107481969 A CN 107481969A CN 201710702565 A CN201710702565 A CN 201710702565A CN 107481969 A CN107481969 A CN 107481969A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
The invention provides a kind of forming method of through hole, comprising：Semi-conductive substrate is provided, formed with a dielectric layer；One first mask layer is formed on the dielectric layer, is open in first mask layer formed with one；A moment erosion protective layer is covered on first mask layer, the etch-protecting layer covers the side wall of the opening；Using first mask layer and the etch-protecting layer as mask, the dielectric layer is etched to form the through hole of a corresponding opening in the dielectric layer；Remove the etch-protecting layer.Method provided by the invention, the problem of optimizing the first mask layer pattern exception in the forming process of through hole, while the requirement to etching selection ratio is reduced, improve technological feasibility.
Description
Technical field
The present invention relates to a kind of semiconductor preparing process, especially a kind of forming method of through hole.
Background technology
With the development of integrated circuit technique, the integrated level of integrated circuit constantly increases, and the size of semiconductor devices is not
Disconnected to reduce, this has required more accurate, advanced technical merit, especially to have there is higher photoetching alignment precision.
For example, in Damascus technics, photoetching alignment precision need to be strictly controlled to obtain required via hole image.
Fig. 1 to Fig. 3 is the structural representation in via process is prepared in a kind of Damascus technics, such as Fig. 1 to Fig. 3 institutes
Show, first, there is provided semi-conductive substrate, be sequentially formed with underlying dielectric layers 1, dielectric layer 2 from bottom to top and with the first opening 4
Mask layer 3, wherein first opening 4 formed a grooves；Then, a photoresist for carrying via hole image 6 is formed on dielectric layer 2
Layer 5, wherein, the position of groove described in the position correspondence of via hole image 6, and the size of via hole image 6 is less than or equal to groove
Size；Then, with photoresist layer 5 be mask along the etch media layer 2 of via hole image 6 to form through hole 7.
However, in the through hole preparation process of reality, the problem of dimension of picture control deviation can usually occur, and then make institute
The pattern of obtained through hole is abnormal.By dimension of picture control deviation is formed in a kind of Damascus technics of Fig. 4 and Fig. 5
The structural representation of through hole, as shown in Figure 4 and Figure 5, compared with preferable technological process, because dimension of picture control deviation causes
The size of via hole image 6 is more than the size of the first opening 4, so as to expose part mask layer 3 by via hole image 6 so that
During etching, the mask layer 3 exposed is easily consumed, and quilt is easier in the sidewall locations of the first opening 4 in mask layer 3 especially
Consumption, and then cause groove pattern abnormal, and further make the pattern of formed through hole 7 abnormal.
It is similar, Fig. 6 and Fig. 7 to be another by the structural representation of through hole formed during photoetching alignment deviation, such as
Shown in Fig. 6 and Fig. 7, photoetching alignment deviation causes the center of via hole image 6 to be not aligned with the center of the first opening 4 so that etching
During, part mask layer 3 causes groove pattern abnormal, and further make formed through hole 7 exposed to loss is produced outside
Pattern it is abnormal.
If the pattern of the through hole formed has abnormal, the performance of whole device can directly be impacted.Therefore,
During through hole is prepared, the integrality of the mask layer above dielectric layer how is ensured, it is outstanding to obtain the through hole of preferable pattern
To be important.
The content of the invention
It is an object of the invention to provide a kind of forming method of through hole, to optimize dimension of picture control deviation and photoetching set
Carve the problem of deviation causes formed through hole pattern exception.
In order to solve the above-mentioned technical problem, the invention provides a kind of forming method of through hole, comprise the steps of：
Semi-conductive substrate is provided, on the semiconductor substrate formed with a dielectric layer；
One first mask layer is formed on the dielectric layer, formed with the one one opening in first mask layer；
A moment erosion protective layer is at least covered in the side wall of the described first opening；
Using first mask layer and the etch-protecting layer as mask, the dielectric layer is etched with the dielectric layer
Form the through hole of corresponding first opening.
Optionally, the forming method of first opening of first mask layer includes：
One first anti-reflecting layer and patterned first photoresist layer are sequentially formed on the first mask layer；
Using patterned first photoresist layer as the first anti-reflecting layer described in mask etching and first mask layer, with
First opening is formed in first mask layer；
Remove first anti-reflecting layer and first photoresist layer.
Optionally, etch the dielectric layer is included with forming the method for the through hole：
A protected material bed of material, the side of protected material bed of material covering first opening are covered on first mask layer
Wall and bottom；
One second mask layer is formed on the protected material bed of material, is open in second mask layer formed with one second,
The position of first opening described in the position correspondence of second opening, and in short transverse, described second is open
Size be more than or equal to described first opening size；
First time etching technics is performed, to form corresponding first opening in the dielectric layer and not run through described
The groove of dielectric layer, meanwhile, remove the protected material bed of material described first opening bottom part, retain the protected material
The bed of material described first opening side wall part, to form the etch-protecting layer；
Second mask layer is removed, exposes the etch-protecting layer；
Second is performed using first mask layer and the etch-protecting layer as mask to etch, to Jie in the groove
Matter layer performs second and etched, and removes the dielectric layer corresponded in the groove, to form the institute through the dielectric layer
State through hole.
Preferably, second mask layer includes：
One layer of second anti-reflecting layer；
One layer coated on the second photoresist layer on second anti-reflecting layer.
Optionally, the Semiconductor substrate includes：
Substrate；
Underlying dielectric layers, formed on the substrate；
Metal interconnecting wires, formed in the underlying dielectric layers；
Etching barrier layer, formed on the underlying dielectric layers and the metal interconnecting wires.
Optionally, the material of the metal interconnecting wires is copper.
Optionally, the etching barrier layer is nitrogenous silicon carbide layer.
Optionally, the dielectric layer is low dielectric coefficient medium layer.
Optionally, the dielectric layer includes Fluorin doped silicon oxide layer.
Optionally, first mask layer includes metal hard mask layer.
Optionally, first mask layer includes titanium nitride layer.
Preferably, first mask layer also includes at least one of cushion and sealer, the cushion
Formed on the dielectric layer, the titanium nitride layer is formed on the cushion, and the sealer is formed in the nitrogen
Change on titanium layer.
Further, etching the dielectric layer to be formed in the etching process of the through hole, the etch-protecting layer and
The etching selection ratio of the dielectric layer is more than or equal to 10:1.
Compared with prior art, technical scheme has advantages below：
In the forming method of through hole provided by the present invention, before via etch, first top and side on the first mask layer
Etch-protecting layer is formed on wall, so as to during via etch, can effectively protect the first mask layer, reduces by the first mask
The loss of layer, the integrality of the first opening in follow-up etching technics is ensured, and then, in using first mask layer
During the through hole that the first opening defines, the pattern of formed through hole can be ensured accordingly.Meanwhile with the shape of conventional via
Compared into technique, reduce the requirement to dielectric layer and the etching selection ratio to hard mask layer, greatly reduce etching technics
Difficulty, improve the feasibility of technique.
Brief description of the drawings
Fig. 1 to Fig. 3 is the structural representation in via process is prepared in a kind of Damascus technics；
Fig. 4 and Fig. 5 is shown by a kind of structure of the through hole formed in Damascus technics due to dimension of picture control deviation
It is intended to；
Fig. 6 and Fig. 7 by a kind of Damascus technics due to the structural representation of through hole formed during photoetching alignment deviation
Figure；
Fig. 8 is the schematic flow sheet of the forming method of the through hole in the embodiment of the present invention one；
Fig. 9 to Figure 13 is structural representation of the forming method of the through hole in the embodiment of the present invention one in its preparation process
Figure；
Figure 14 to Figure 17 is structural representation of the forming method of the through hole in the embodiment of the present invention two in its preparation process
Figure.
Embodiment
As stated in the Background Art, with the continuous reduction of characteristic size, photoetching difficulty is caused more to increase.
In the forming process of through hole, one is due to the etching choosing of the material to dielectric layer and the material to hard mask layer
Select than that can not possibly reach infinitely great, two the problems such as being due to dimension of picture control deviation and photoetching alignment deviation, and then cause institute
The through hole pattern of formation is abnormal.
Therefore, the invention provides a kind of forming method of through hole, including:
Semi-conductive substrate is provided, on the semiconductor substrate formed with a dielectric layer；
One first mask layer is formed on the dielectric layer, formed with one first opening in first mask layer；
A moment erosion protective layer is at least covered in the side wall of the described first opening；
Using first mask layer and the etch-protecting layer as mask, the dielectric layer is etched with the dielectric layer
Form the through hole of corresponding first opening.
In the forming method of the through hole of the present invention, the first mask layer is protected using etch-protecting layer, avoids the
One mask layer is avoided the pattern of the first opening on the first mask layer abnormal, so as to ensure that what is formed leads to by etching injury
The integrality in hole.
The forming method of through hole proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
According to following explanation, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing using very simplified form and
Non- accurately ratio is used, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Embodiment one
Fig. 8 is the schematic flow sheet of the forming method of the through hole in the embodiment of the present invention one；Fig. 9 to Figure 13 is real for the present invention
Apply structural representation of the forming method of the through hole in example one in its preparation process.Below with reference to Fig. 8 to Figure 13, describe in detail
A kind of embodiment of the present invention.
First, step S101 is performed, with reference to shown in figure 9, there is provided semi-conductive substrate 100, be formed on a dielectric layer
101.Optionally, the material of dielectric layer 101 includes advanced low-k materials, and so-called advanced low-k materials are, for example, that its dielectric is normal
Number is less than 3.9 and is not less than 2.55 material.Further, the material of dielectric layer 101 can be the material of silica base, example
The silica of silica or Fluorin doped such as carbon doping, in the present embodiment, the material of dielectric layer 101 is the silica of Fluorin doped.
Optionally, the formation process of dielectric layer 101 can be chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD) etc..It is preferred that
, the dielectric layer 101 with the titanium dioxide silicon substrate of low-k can utilize plasma enhanced chemical vapor deposition
(PECVD) formed, can further reduce the dielectric constant of material.
Then, step S102 is performed, with continued reference to Fig. 9 and Figure 10, one first mask layer is formed on the dielectric layer
102, formed with one first opening 108 in first mask layer 102.Optionally, the material of the first mask layer 102 includes nonmetallic
Hard mask material, such as silicon nitride and silica, the material of the first mask layer 102 may also include metal hard mask material, example
Such as titanium nitride and tantalum nitride.Optionally, the first mask layer 102 can utilize physical vapour deposition (PVD) (PVD) formation.
Specifically, the first 108 forming methods of opening of first mask layer 102 include：
First step, the anti-reflecting layer of spin coating first and the first photoresist layer successively on first mask layer；
Second step, perform exposure imaging technique, graphical first photoresist layer；
Third step, using first photoresist layer as the first anti-reflecting layer described in mask etching and the first mask material
The bed of material, to form the opening 108；
Four steps, first anti-reflecting layer 103 and first photoresist can be removed by being ashed handling process
Layer 104.
Then, step S103 is performed, with reference to shown in figure 10, Figure 11 and Figure 12, one is covered on first mask layer 102
Etch-protecting layer 105, the etch-protecting layer 105 cover the side wall of the opening 108.Wherein, the etch-protecting layer includes
It is more than 10 with the etching selection ratio of dielectric layer:1 film layer, the material of the present embodiment dielectric layer 101 are Fluorin doped silica, because
This, the etch-protecting layer 105 can be selected silicon nitride and be formed.
As noted previously, as the etching selection ratio between dielectric layer and the first mask layer is relatively, for example, dielectric layer with
Etching selection ratio between first mask layer is less than 10:1, so as to be mask etching dielectric layer directly using the first mask layer
When, then the first mask layer is easily consumed, and then the through hole pattern resulted in the dielectric layer is abnormal.In the present embodiment, according to
The material of dielectric layer 101 from the etch-protecting layer 106 with larger etching selection ratio, effectively prevent the first mask accordingly
The problem of layer is largely consumed in etching process.
Wherein, the etch-protecting layer 106 can utilize chemical vapor deposition method and return carving technology, specifically：Can first it select
One layer of etch-protecting layer 105 is deposited with chemical vapor deposition (CVD), then is returned by dry etching and carves the etch-protecting layer 105,
And then the bottom of opening 108 of exposure first mask layer 102, and remain in etch-protecting layer 105 on opening sidewalls
Part, formed etch-protecting layer 106 is covered the side wall of the opening 108 of the first mask layer 102, to play protection first
The effect of mask layer 102.
Then, step S104 is performed, is to cover with first mask 102 and etch-protecting layer 106 with reference to figure 12 and Figure 13
Film, the dielectric layer 101 is etched to form the through hole 107 of a corresponding opening 108 in the dielectric layer 101.Specifically,
The reactive ion etching (Reactive Ion Etching, RIE) that lithographic method can be selected in such as dry etching, to ensure
It is provided simultaneously with anisotropy and higher selectivity.The etch-protecting layer, which can play, prevents first mask layer from horizontal stroke occurs
Effect to etching, and then ensure that the pattern of the through hole 107.
Finally, step S105 is performed, with continued reference to Figure 10 and Figure 11, removes the remaining etch-protecting layer 106, specifically
The preferable lithographic method of isotropism in dry etching can be selected to remove.
Embodiment two
The forming method of the through hole is applied in Damascus technics by the present embodiment, with to through hole provided by the invention
Forming method be further described.Figure 14 to Figure 17 is the forming method of the through hole in the embodiment of the present invention two in its preparation
During structural representation.Below with reference to Figure 14 to Figure 17, a kind of embodiment of the invention is described in detail.
First, step S201 is performed, with specific reference to shown in Figure 14, there is provided semi-conductive substrate (not shown), wherein,
Underlying dielectric layers 200, etching barrier layer 202 and dielectric layer 203 are sequentially formed with the Semiconductor substrate.And described
In underlying dielectric layers 200 with the intersection of etching barrier layer 202 can buried regions have a metal interconnecting wires 201.Specifically, metal interconnecting wires
The metal filled in 201 is, for example, copper, and etching barrier layer 202 is, for example, nitrogenous carborundum (NDC) layer.
Further, dielectric layer 203 is, for example, porous SiOCH layers or Fluorin doped silicon oxide layer.Optionally, underlying dielectric layers
200th, etching barrier layer 202 and dielectric layer 203 can be formed using chemical vapor deposition method, be not detailed herein.Preferably,
Metal interconnecting wires 201 can be formed using physical vaporous deposition.
Then, step S202 is performed, with continued reference to shown in Figure 14, one first mask layer is formed on the dielectric layer 203,
Formed with the first opening 210 in first mask layer.
Wherein, first mask layer can use single layer structure, can also use sandwich construction.For example, first mask
Layer includes metal hard mask layer 205, and in the present embodiment, the first mask layer is sandwich construction, in addition to cushion 204 and/or
Sealer 206.And the cushion 204 is formed on the dielectric layer 203, the titanium nitride layer 205 is formed described
On cushion 204, the sealer 206 is formed on the titanium nitride layer 205.
Specifically, the material of metal hard mask layer 205 is, for example, Ta, Ti, TaN or TiN.In the present embodiment, metallic hard
Matter mask layer 205 is titanium nitride layer；Cushion 204 is tetraethyl orthosilicate (TEOS) layer, can be as the metallic hard being subsequently formed
Stress-buffer layer between matter mask layer 205 and dielectric layer 203；Sealer 206 is silicon oxide layer, and can play prevents gold
Belong to the effect that hard mask layer exposure produces oxidation reaction in atmosphere.Cushion 204, metal hard mask layer 205 and surface
Protective layer 206 can be formed using chemical vapour deposition technique.Preferably, metal hard mask layer 205 can be sunk using physical vapor
Area method is formed.
In the present embodiment, it is, for example, formed with one first opening 210, its forming method in first mask layer：
First, the first anti-reflecting layer 207 and the first photoresist layer 208 are coated successively, graphical first photoresist layer 208,
Form the figure of corresponding first opening 210；
The formation of anti-reflecting layer can eliminate the reflex of light source, avoid the semiconductor base below due to photoresist
(including metal level and dielectric layer) has higher reflectance factor so that exposure light source easily occurs anti-in semiconductor substrate surface
Penetrate, cause deformation or the dimensional discrepancy of photoetching offset plate figure, cause the situation of the incorrect transfer of mask plate figure；
Then, with patterned first photoresist layer 208 for the first anti-reflecting layer 207 described in mask etching and described
First mask layer, to form first opening 210；
Specifically, dry etch process can be used to etch the first anti-reflecting layer 207, sealer 206, metal hard
Mask layer 205 and cushion 204, etching stopping is in cushion 204.
Then, step S203 is performed, referring next to shown in Figure 15, is at least covered in the side wall of the described first opening 210
One etch-protecting layer 219, to be protected to metal hard mask in the first mask layer.In the present embodiment, etch-protecting layer 219
The side wall of first opening 210 is not only covered, while also covers the top of first mask layer.
Preferably, by forming one layer of etching with dielectric layer with larger etching selection ratio on first mask layer
Protective layer 219, to avoid in the first mask layer metal hard mask layer by etching injury.
In the present embodiment, because metal hard mask layer 205 is titanium nitride layer, dielectric layer 203 is the silicon oxide layer of fluorine doped
, therefore etch-protecting layer 219 is from the silicon nitride layer with silica with larger etching selection ratio.Wherein, etch-protecting layer
219 forming method can use chemical vapor deposition method such as low-pressure chemical vapor deposition or plasma enhanced chemical gas
Mutually prepared by the method for deposition.
Then, step S204 is performed, referring next to shown in Figure 15 to Figure 17, is protected with first mask layer and the etching
Sheath 219 is dielectric layer 203 described in mask etching, to form corresponding first opening 210 in the dielectric layer 203
Through hole 211.
In the present embodiment, the through hole 211 is formed using two step etching technics, also, the etch-protecting layer 219 combines
Two step etching technics are formed simultaneously, and its step specifically includes：
First step, covers a protected material bed of material 209 on first mask layer, and the protected material bed of material 209 covers
The side wall of first opening 210 and bottom；
Second step, one second mask layer is formed on the protected material bed of material 209, in second mask layer formed with
One second opening 212, the position of the first opening described in the position correspondence of second opening 212, and perpendicular to height side
Upwards, the size of second opening 212 is more than or equal to the size of the described first opening 210；
Specifically, second mask layer is, for example, photoresist layer, and in the present embodiment, using preferable scheme, described
Two mask layers include the second anti-reflecting layer 217 and the second photoresist layer 218, and second anti-reflecting layer 217 is formed in protected material
On the bed of material 209, the second photoresist layer 218 is formed on the second anti-reflecting layer 217；And second photoresist layer 218 for after graphical
Photoresist layer, in second photoresist layer 218 formed with described second opening 212；
Third step, first time etching technics is performed, to form corresponding first opening in the dielectric layer 203
210 and do not run through the groove of the dielectric layer 203, meanwhile, the protected material bed of material 209 is removed in the described first opening 210
The part of bottom, retain the protected material bed of material 209 described first opening 210 side wall part, for form etching protect
Sheath 219；
In the present embodiment, the part in the protected material bed of material 209 above the first mask layer is again covered with the second mask layer,
Therefore, in first time etching technics, the part protected material bed of material 209 above the first mask layer is retained, and with first
The protected material bed of material for 210 side walls that are open collectively forms etch-protecting layer 219.
Specifically, lithographic method can select such as reactive ion etching (Reactive Ion in dry etching
Etching, RIE), reactive ion etching is a kind of dry etching technology between ise and plasma etching,
It has the advantages of anisotropic etching and higher selectivity concurrently.Etching process also results in sealer 206 exposed to the
Part in two openings is etched removal；
Four steps, second mask layer is removed, to expose the etch-protecting layer 219；
In the present embodiment, the second anti-reflecting layer 217 and the second photoresist layer 218 can be removed by being ashed processing；
5th step, it is that mask performs second of etching with first mask layer and the etch-protecting layer 219, to institute
State the dielectric layer 203 in groove and perform second of etching, remove the dielectric layer 203 corresponded in the groove, to be formed
Through the through hole 211 of the dielectric layer 203.
Specifically, the deep reaction ion etching that lithographic method can be selected in dry etch process, to laterally etched control
System is more outstanding.
In summary, in the forming method of through hole provided by the invention, one layer is deposited on the first mask layer to dielectric layer
Select than high etch-protecting layer, and then, during via etch, the integrality of the first mask layer is effectively protected, so as to
Optimize because dimension of picture control deviation and photoetching alignment deviation cause the groove pattern abnormal problem of through hole.And then also can
Solve critical size and reduce the difficulty brought to follow-up reliability testing, while also solve photoetching alignment deviation and brought to back segment
The potential risk of metal short circuit, is very significantly improved damascene structure.
In addition, on etching technics, compared with conventional etch processes, reduce to the material of dielectric layer and to the first mask
The requirement of the etching selection ratio of the material of layer, therefore, greatly reduces etching technics difficulty, has more preferable technological feasibility,
It is applicable board scope to also increase a lot, advantage is provided for mass production.
Obviously, those skilled in the art can carry out the spirit of various changes and modification without departing from the present invention to invention
And scope.So, if these modifications and variations of the present invention belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to comprising including these changes and modification.
Claims (13)
- A kind of 1. forming method of through hole, it is characterised in that including：Semi-conductive substrate is provided, on the semiconductor substrate formed with a dielectric layer；One first mask layer is formed on the dielectric layer, formed with one first opening in first mask layer；A moment erosion protective layer is at least covered in the side wall of the described first opening；Using first mask layer and the etch-protecting layer as mask, the dielectric layer is etched to be formed in the dielectric layer The through hole of one corresponding first opening.
- 2. the forming method of through hole according to claim 1, it is characterised in that described the first of first mask layer opens The forming method of mouth includes：One first anti-reflecting layer and patterned first photoresist layer are sequentially formed on the first mask layer；Using patterned first photoresist layer as the first anti-reflecting layer described in mask etching and first mask layer, with described First opening is formed in first mask layer；Remove first anti-reflecting layer and first photoresist layer.
- 3. the forming method of through hole according to claim 1, it is characterised in that it is described logical to be formed to etch the dielectric layer The method in hole includes：Cover a protected material bed of material on first mask layer, the side wall of protected material bed of material covering first opening and Bottom；One second mask layer is formed on the protected material bed of material, is open in second mask layer formed with one second, it is described The position of first opening described in the position correspondence of second opening, and in short transverse, the chi of second opening The very little size for being more than or equal to the described first opening；First time etching technics is performed, to form corresponding first opening in the dielectric layer and not run through the medium Layer groove, meanwhile, remove the protected material bed of material described first opening bottom part, retain the protected material bed of material In the part of the side wall of the described first opening, to form the etch-protecting layer；Second mask layer is removed, exposes the etch-protecting layer；Second is performed using first mask layer and the etch-protecting layer as mask to etch, to the dielectric layer in the groove Perform second to etch, remove the dielectric layer corresponded in the groove, to be formed through the described logical of the dielectric layer Hole.
- 4. the forming method of through hole according to claim 3, it is characterised in that second mask layer includes：One second anti-reflecting layer；One coated on the second photoresist layer on second anti-reflecting layer.
- 5. the forming method of through hole according to claim 1, it is characterised in that the Semiconductor substrate includes：Substrate；Underlying dielectric layers, formed on the substrate；Metal interconnecting wires, formed in the underlying dielectric layers；Etching barrier layer, formed on the underlying dielectric layers and the metal interconnecting wires.
- 6. the forming method of through hole according to claim 5, it is characterised in that the material of the metal interconnecting wires is copper.
- 7. the forming method of through hole according to claim 5, it is characterised in that the etching barrier layer is nitrogenous carbonization Silicon layer.
- 8. the forming method of through hole according to claim 1, it is characterised in that the dielectric layer is medium with low dielectric constant Layer.
- 9. the forming method of through hole according to claim 8, it is characterised in that the dielectric layer includes Fluorin doped silica Layer.
- 10. the forming method of through hole according to claim 1, it is characterised in that first mask layer includes metallic hard Matter mask layer.
- 11. the forming method of through hole according to claim 10, it is characterised in that first mask layer includes titanium nitride Layer.
- 12. the forming method of through hole according to claim 11, it is characterised in that first mask layer is also comprising buffering At least one of layer and sealer, the cushion are formed on the dielectric layer, and the titanium nitride layer is formed in institute State on cushion, the sealer is formed on the titanium nitride layer.
- 13. the forming method of through hole according to claim 1, it is characterised in that etching the dielectric layer to be formed In the etching process for stating through hole, the etching selection ratio of the etch-protecting layer and the dielectric layer is more than or equal to 10:1.
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| CN201710702565.8A CN107481969B (en) | 2017-08-16 | 2017-08-16 | Through hole forming method |
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| CN201710702565.8A CN107481969B (en) | 2017-08-16 | 2017-08-16 | Through hole forming method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111162082A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111430361A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111430362A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111933581A (en) * | 2020-09-25 | 2020-11-13 | 南京晶驱集成电路有限公司 | Preparation method of semiconductor structure |
| CN116759384A (en) * | 2023-08-17 | 2023-09-15 | 长电集成电路(绍兴)有限公司 | Wiring layer, preparation method thereof and packaging structure |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162082A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111162082B (en) * | 2020-01-02 | 2022-05-27 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111430361A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111430362A (en) * | 2020-04-09 | 2020-07-17 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111430361B (en) * | 2020-04-09 | 2023-07-25 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN111933581A (en) * | 2020-09-25 | 2020-11-13 | 南京晶驱集成电路有限公司 | Preparation method of semiconductor structure |
| CN116759384A (en) * | 2023-08-17 | 2023-09-15 | 长电集成电路(绍兴)有限公司 | Wiring layer, preparation method thereof and packaging structure |
| CN116759384B (en) * | 2023-08-17 | 2023-11-03 | 长电集成电路(绍兴)有限公司 | Wiring layer, preparation method thereof and packaging structure |
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