KR100807026B1 - Method of fabricating semicondcucor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to simplify a fabricating process by eliminating the necessity of a process for forming a photoresist layer in the lower part of a contact hole before a trench is etched. A lower interconnection(115) is formed on a semiconductor substrate. An interlayer dielectric(140) is stacked on the lower interconnection. A sub layer(143) having etch selectivity with respect to the interlayer dielectric, a first sacrificial layer(145) having etch selectivity with respect to the sub layer, and a second sacrificial layer(147) having etch selectivity with respect to the first sacrificial layer are sequentially formed on the interlayer dielectric. The second sacrificial layer is made of the same material as the sub layer, thicker than the sub layer. A mask pattern for forming a contact hole is formed on the second sacrificial layer, and the second sacrificial layer, the first sacrificial layer, the sub layer and the interlayer dielectric are etched to remove a predetermined thickness of at least the interlayer dielectric. A mask pattern(165) for forming a trench(175) is formed in the substrate, and the second and first sacrificial layers in a trench region is etched. The mask pattern for forming the trench is removed, and the sub layer exposed to the trench region is etched wherein a predetermined thickness of the second sacrificial layer is left. The interlayer dielectric is etched by using the residual second sacrificial layer as an etch mask so that at least part of the lower interconnection is exposed.

Description

Method of fabricating a semiconductor device {Method of fabricating semicondcucor device}

1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

6 to 11 are process cross-sectional views showing respective steps of an embodiment of the method of manufacturing a semiconductor device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact for connecting interlayer wiring.

A semiconductor device is a type of circuit device formed by forming a conductor, a non-conductor, and a semiconductor film on a semiconductor substrate to form an electronic, electrical element, and wiring. As the integration of semiconductor devices has progressed, semiconductor devices have become very complex and precise, and the formation process needs to be controlled with extreme precision.

The size of devices and wirings is gradually reduced for high integration of semiconductor devices, and multilayering is performed to form many devices in a limited area. In order to connect the device and the wiring, and to connect the upper wiring and the lower wiring, a hole is formed in the interlayer insulating film and a conductor is filled in the hole to form a contact.

As the device is highly integrated, the width of the device and the wiring may be reduced, and thus the resistance of the wiring may be increased, thereby causing a resistance capacitor delay (RC DELAY) when the operation signal is transmitted, and the reliability and stability of the operation of the device may be a problem. One way to reduce internal resistance is to use copper as the wiring metal. When copper is used as the wiring metal, the damascene technique is frequently used because of its poor etching properties. The dual damascene process is a process of forming a via and a trench in an interlayer insulating film, and then filling and planarizing copper.

Referring to FIG. 1, a lower wiring pattern 15 is formed on a substrate 10 having an insulating layer formed of a silicon oxide film through a damascene process. An interlayer insulating film is formed over the lower wiring pattern 15. The interlayer insulating film is formed by sequentially stacking the silicon nitride film, which is the stopper layer 20, and the silicon oxide film 40. A photoresist mask pattern is formed on the interlayer insulating film, and the contact hole 50 is etched. In this case, the contact hole etching is performed until the silicon nitride film, which is the lower stopper layer 20, is exposed.

Referring to FIG. 2, the photoresist layer 55 is formed in the lower portion of the contact hole to prevent damage to the lower wiring while the contact hole 50 blocked by the stopper layer 20 is formed on the substrate. When the photoresist is laminated on the substrate and the entire photoresist is removed by ashing or the like without the entire exposure depending on the type of photoresist, the photoresist may remain only under the contact hole. For this process, photoresist types such as Novolak, which are well flowable and well protected during etching, can be used.

Referring to FIG. 3, a photoresist pattern 65 for forming an upper wiring trench is formed following the state of FIG. 2.

Referring to FIG. 4, following the state of FIG. 3, trench formation etching is performed on the upper portion of the interlayer insulating layer using the photoresist pattern 65 as an etching mask. In this process, when the residual photoresist layer 55 under the contact hole is thick, the photoresist layer is formed on the silicon oxide film 40 in contact with the photoresist layer 55 at the bottom of the trench 75 during the trench etching. Interfering with etching, the convex fence 80 is left at the portion where the trench 75 and the contact hole are connected (fence phenomenon).

Referring to FIG. 5, the photoresist pattern 65 ′ of the substrate, the photoresist layer 55 remaining in the contact hole and the photoresist pattern 65 ′ remaining on the substrate are removed in the state of FIG. 4. At this time, the remaining photoresist layer 55 is not sufficiently removed, making it difficult to remove the silicon nitride film stopper layer 20 thereunder, and then, after the contact plug (not shown) is formed, between the contact plug and the lower wiring pattern 15. May interfere with the electrical connection.

In addition, after the photoresist pattern 65 'is removed, the periphery of the trench 75 of the interlayer insulating film acting as a hard mask in the stopper layer 20 removal step is damaged, and copper is filled in this part in a subsequent copper lamination step. There was a problem that it was not removed in the subsequent chemical mechanical polishing (CMP) step and consequently widened the trench width of the upper wiring, and these portions of adjacent upper wiring touched each other, causing a short circuit.

Alternatively, when the interlayer insulating film of the wiring material is an oxide film having a low dielectric constant when a portion of the wiring material such as copper filling the trench 75 or the contact hole 90 is accumulated on the upper surface of the interlayer insulating film using a chemical mechanical polishing process, Pattern defects resulting from the mechanical polishing process, such as a serration pattern (85), may occur, and impurities such as copper oxide may be generated on the surface of the interlayer insulating layer, thereby reducing the yield of semiconductor devices. do.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, and the present invention is caused by damage to the trench periphery of the interlayer insulating film when the chemical mechanical polishing process is performed to remove the upper wiring material or when the stopper layer is removed before. It aims at preventing the phenomenon which a serrated pattern produces and a short circuit generate | occur | produces.

In addition, the present invention may provide a method for preventing the occurrence of the fence phenomenon by the conventional photoresist residual layer during the dual damascene process.

The present invention for achieving the above object,

Forming a lower wiring on a semiconductor substrate, stacking an interlayer insulating film over the lower wiring, an auxiliary film having an etch selectivity with the interlayer insulating film over the interlayer insulating film, a first sacrificial film having an etch selectivity with the auxiliary film, Sequentially forming a second sacrificial layer having an etching selectivity with the first sacrificial layer and the same material as the auxiliary layer and thicker than the auxiliary layer, forming a contact hole forming mask pattern on the second sacrificial layer, and forming at least the interlayer insulating layer Etching the second sacrificial layer, the first sacrificial layer, the auxiliary layer, and the interlayer insulating layer to remove a part of the thickness of the second insulating layer; forming a trench forming mask pattern on the substrate from which the contact hole forming mask pattern is removed from the substrate; Removing the second sacrificial layer and the first sacrificial layer by etching, removing the trench forming mask pattern, and removing the auxiliary layer exposed in the trench region. Performing etching to, but is characterized in that formed in a step to expose at least a portion of the lower interconnection by etching the interlayer insulating film in the second sacrificial film step, an etch mask, the remaining second sacrificial film, leaving a portion thickness.

In the present invention, etching is usually performed by anisotropic dry etching, and the interlayer insulating film may be formed of a silicon oxide film, particularly a low dielectric constant silicon oxide film having a relative dielectric constant of less than 3.5.

In the present invention, the auxiliary layer or the second sacrificial layer may be formed of a silicon nitride layer having a high etching selectivity when the interlayer insulating layer is formed of a silicon oxide layer.

In the present invention, after forming the lower wiring, a silicon nitride film used as a stopper layer may be formed before the interlayer insulating film is formed. In this case, the etching step of exposing at least a portion of the lower wiring may be performed by first etching the stopper film and the stopper film. And an etching step of removing the remaining layer of the second sacrificial layer used as the etching mask.

After the steps of the present invention, the trenches and contact holes formed by etching are filled through the wiring conductor film deposition, and the contact plugs and the upper wirings are formed through a CMP process or an etch back process that exposes an auxiliary film or an interlayer insulating film. It is common to be.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Referring to FIG. 6, a lower wiring is formed on the substrate 10 where the insulating layer is exposed through a damascene process. The silicon nitride film stopper layer 120 is formed to have a thickness of, for example, 500 to 1000 angstroms on the substrate on which the lower wiring 115 is formed. The silicon oxide film 140 is stacked to form an interlayer insulating film over the stopper layer 120. The interlayer insulating film is usually formed of a silicon oxide film, and may be formed of a low dielectric film such as an SOG film or an FSG film having a relative dielectric constant of about 3 to 3.5 in order to prevent an increase in parasitic capacitor capacity due to high integration. Although shown in one layer in the figure, it may actually be formed through a plurality of different processes.

An auxiliary film 143 made of a silicon nitride film, a first sacrificial film 145 made of a silicon oxide film, and a second sacrificial film 147 made of a silicon nitride film are formed on the interlayer insulating film. For example, the auxiliary layer 143 may have a thickness of about 500 angstroms, and the second sacrificial layer 147 may have a thickness of about 2,000 angstroms.

A photoresist layer is further stacked on the substrate on which the second sacrificial layer 147 is formed through spinning, and a contact hole forming mask pattern 149 is formed through the exposure and development to expose the contact region.

Referring to FIG. 7, a portion of the silicon oxide layer 140 forming the second sacrificial layer 147, the first sacrificial layer 145, the auxiliary layer 143, and the interlayer insulating layer is formed by using the contact hole forming mask pattern as an etching mask. Etch it. Etching can be performed by changing the etchant gas in situ method in the same etching equipment as the material of the layer is changed, and can be generally performed by active ion etching method with strong anisotropy. .

In this case, the etching depth of the interlayer insulating layer may be the same as or slightly more than the length of the contact of the semiconductor device to be formed in the future. Such depth control may be performed by adjusting various conditions, particularly time, such as etchant concentration and type when etching the interlayer insulating film.

After etching, the contact hole forming mask pattern is removed by ashing or the like to form a partial contact hole 150 of FIG. 7.

Referring to FIG. 8, a trench pattern mask pattern 165 for forming upper wirings is formed on the substrate through an exposure process following the step of FIG. 7. Unlike the prior art, the photoresist layer filling the contact hole is not formed. This reduces one exposure process using photoresist. The trench forming mask pattern 165 is formed through the same exposure process as the contact hole forming mask pattern, but is formed by changing a pattern of an exposure photo mask or a reticle. Subsequently, an etching process of removing the second sacrificial layer 147 and the first sacrificial layer 145 from the trench region is performed using the trench formation mask pattern 165 as an etching mask.

Subsequently, as shown in FIG. 9, the trench formation mask pattern 165 of FIG. 8 is first removed, and then anisotropic etching is performed on the substrate to remove the silicon nitride film. In this step, the relatively thin auxiliary layer 143 in the trench region is completely removed from the silicon nitride layer exposed on the substrate, and the second sacrificial layer 147 formed overall in the other region is left in the remaining layer 147 thickness. It remains. For this etching thickness control, a time ethching technique may also be used. In the process of removing the auxiliary layer 143 of the trench region, since the trench pattern mask pattern 165 is already removed from the substrate, the trench inside may be relatively clean with almost no polymer.

Referring to FIG. 10, in the state of FIG. 9, an interlayer insulating layer etched on the entire surface of the substrate is performed. Since the substrate is covered with the second sacrificial layer having the remaining thickness except the trench region, the stepped pattern is lowered according to the anisotropic etching only in the trench 175 region. Meanwhile, as the etching conditions are adjusted in this process, the angled portion may be changed into a smooth curve shape, or the upper portion of the trench 175 or the hole 150 'may be wider than the lower portion. In this case, the fillability of the subsequent plug and upper wiring metal stack for the contact hole can be improved.

As a result, trench and contact hole patterns are exposed in the interlayer insulating film. In this case, the silicon nitride film stopper layer 120 stacked on the lower interconnection serves as a stopper that prevents the lower interconnection pattern from being damaged due to excessive etching under the contact hole by preventing the progress of etching.

Thereafter, the stopper layer 120 is removed from the step of FIG. 10 so that a part of the lower wiring 115 is exposed on the bottom of the contact hole. In this case, it is preferable to remove the second sacrificial film remaining layer 147 ′ having a thinner thickness, such as the silicon nitride film material, such as the stopper layer 120. In order to enable such a process, it is necessary to adjust the relative stacking thickness of the stopper layer, the second sacrificial film, and the auxiliary film. For example, the thickness of the second sacrificial layer may be greater than the thickness of the stopper layer plus the thickness of the auxiliary layer.

In this case, since the photoresist pattern is removed, the inner wall or the bottom of the contact hole may maintain a clean state with less polymer as compared with the etching with the photoresist pattern.

Subsequently, a metal film, such as copper, is formed to form a contact plug and an upper wiring on the substrate. Before the copper lamination, a tantalum / tartalum nitride film may be thinly laminated as a barrier film or as an adhesive layer to prevent diffusion of copper. After the copper metal film is laminated, a first CMP process is performed to remove the copper metal film stacked on the first sacrificial film remaining on the substrate. In addition, a second CMP process is performed on the first sacrificial layer using the auxiliary layer 143 as a stop layer to expose the auxiliary layer 143 to the entire surface of the substrate. As a result, the upper wiring 190 and the contact plug 195 are formed. The first CMP and the second CMP process may be performed simultaneously or sequentially.

In this embodiment, the process is simplified because it is not necessary to fill the photoresist layer to protect the bottom of the already completed contact hole prior to trench formation. In addition, since there is no room for a fence phenomenon, the form of the trench and the contact hole connection portion may increase the fillability of the metal layer. In addition, since the second sacrificial film remaining layer used as a hard mask in the etching of the trench forming step or the first sacrificial film used as the lower film in the metal layer CMP step is removed as a result, damage occurs at the trench inlet, and the upper wiring width is wide. This reduces the problem of short circuits with adjacent wiring.

Compared to the existing process, the process can be simplified by forming a contact hole and reducing the process of forming a photoresist layer under the contact hole before the trench etching, and the non-opening of the contact hole in a subsequent process due to the photoresist layer. Reduction in productivity and yield.

In addition, metal fillability is reduced by reducing fence defects, and damage between trenches is prevented to reduce short circuits between upper interconnections, thereby improving reliability and stability of semiconductor devices.

This can be done by removing only a few sequences from the existing process, allowing the use of existing equipment and process technology.

Claims (5)

Forming a lower wiring on the semiconductor substrate, Stacking an interlayer insulating film over the lower wiring; An auxiliary film having an etch selectivity with the interlayer insulating film over the interlayer insulating film, a first sacrificial film having an etch selectivity with the auxiliary film, an etching selectivity with the first sacrificial film, and having the same material as the auxiliary film; Sequentially forming a second sacrificial film thicker than the auxiliary film, Etching the second sacrificial layer, the first sacrificial layer, the auxiliary layer, and the interlayer insulating layer to form a contact hole forming mask pattern over the second sacrificial layer and to remove at least a portion of the interlayer insulating layer; Forming a trench forming mask pattern on the substrate from which the contact hole forming mask pattern is removed, and removing the second sacrificial layer and the first sacrificial layer by etching in the trench region; Etching to remove the trench formation mask pattern and to remove the auxiliary layer exposed in the trench region, but to leave a partial thickness of the second sacrificial layer; And etching the interlayer insulating film to expose at least a portion of the lower interconnection using the remaining second sacrificial film as an etching mask. The method of claim 1, Wherein the interlayer insulating film is formed of a low dielectric constant silicon oxide film having a relative dielectric constant of 3 to 3.5, and the auxiliary film or the second sacrificial film is formed of a silicon nitride film. The method according to claim 1 or 2, After forming the lower wiring and before forming the interlayer insulating film, a stopper layer is formed of a silicon nitride film, The etching step of exposing at least a portion of the lower interconnection comprises first etching to expose the stopper layer and an etching step of removing the remaining layer of the second sacrificial layer used as an etching mask together with the stopper layer. A method for forming a semiconductor device. The method of claim 3, wherein And the thickness of the second sacrificial layer is greater than the thickness of the stopper layer plus the thickness of the auxiliary layer. The method of claim 3, wherein In the removing of the thickness of the interlayer insulating layer using the contact hole forming mask pattern as an etch mask, the etch depth of the interlayer insulating layer is deeper than the length of the contact plug to be formed in the semiconductor device. The method of claim 1, wherein the etching depth is controlled by adjusting the etching time between the interlayer insulating layers.

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