CN103187362B - There is the manufacture method of the dual damascene damascene structure device of air gap - Google Patents
There is the manufacture method of the dual damascene damascene structure device of air gap Download PDFInfo
- Publication number
- CN103187362B CN103187362B CN201110457697.1A CN201110457697A CN103187362B CN 103187362 B CN103187362 B CN 103187362B CN 201110457697 A CN201110457697 A CN 201110457697A CN 103187362 B CN103187362 B CN 103187362B
- Authority
- CN
- China
- Prior art keywords
- layer
- air gap
- interlayer dielectric
- damascene
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
Present invention is disclosed a kind of manufacture method with the dual damascene damascene structure of air gap, by forming sacrifice layer in interlayer dielectric layer, and utilize the method for etching or thermal decomposition to remove part or all of sacrifice layer, thus form air gap in dual damascene damascene structure device; By formed can in subsequent technique thermal decomposition remove sacrificial structure to define position and the size of metal connecting line layer, described sacrificial structure forms groove after removing, formation process is simple and easy to realize, and avoids the problem of the dielectric constant values rising that the etching injury of etching technics to interlayer dielectric layer causes; By and first interlayer dielectric layer other at this sacrificial structure form supporting layer, thus the air gap formed is half filling, the size of air gap can be kept and maintain the mechanical stability of interlayer dielectric layer, therefore, the lower and good mechanical stability of device of the dielectric constant with the interlayer dielectric layer of the dual damascene damascene structure device of air gap of formation.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, particularly relate to a kind of manufacture method with the semiconductor device of dual damascene damascene structure.
Background technology
Copper-connection is the main flow interconnection technique in current very lagre scale integrated circuit (VLSIC), and electro-coppering is one of critical process in copper-connection.Copper wiring technique is put forward by IBM as far back as in September, 1997, mosaic technology of being known as (also claiming Damascus).And be applied to and prepare microprocessor, high-performance memory and digital signal processor etc.It adopts and replaces corrosion of metal to determine live width and the spacing of line the corrosion of dielectric material.Mosaic technology is divided into single mosaic technology and dual-damascene technics, and difference is whether the technique line of reach through hole and this layer is prepare simultaneously.
Along with the integrated level of semiconductor device is more and more higher, the principal element of speed of restriction semiconductor device is no longer transistor delay, but postpones with electric conducting material (such as metal) resistance-capacitance (RC) be associated that interconnects.After recognizing this point, in order to reduce the electric capacity of conductive interconnect material thus reduce RC delay, those skilled in the art have carried out extensive work for researching and developing new material and manufacturing process.Such as, using as the dielectric substance in conductive interconnect material layer, select to adopt the dielectric substance with low-k.In all material, what dielectric constant was minimum surely belongs to air, the dielectric constant of air is 1, the dielectric constant of other layer of dielectric material is all greater than 1, therefore, technical staff starts to focus in interlayer dielectric layer and forms air gap (Air Gap), and the formation of air gap can reduce the overall dielectric constant of interlayer dielectric layer further, to reduce the electric capacity between electric conducting material, improve the performance of semiconductor device.
In the manufacture method of existing making damascene structure, forming a kind of method with the semiconductor device of air gap is in current interlayer dielectric layer, by photoetching and etching method, the gap that size is less is formed between metal interconnecting wires, then chemical vapour deposition (CVD) (CVD) method is utilized, current interlayer dielectric layer covers and forms dielectric layer between later layer, and do not fill this gap, thus form air gap in current media layer, although the method reaches the object reducing integrated circuit RC and postpone, but due to the restriction of manufacturing process itself, for the semiconductor device that critical size (CD) is less, the method is when formation has the semiconductor device of multiple metal interconnecting layers, due to the restriction of the less and accuracy of existing photoetching process in the interval (Space) between metal interconnecting wires, the via plug (Plug) of later layer metal level is difficult to aim at the metal interconnecting wires of current layer, but be connected with the air gap between metal interconnecting wires, the metallic copper of filling in later layer via plug is made to drop in air gap, cause the short circuit problem of semiconductor device.Therefore, for small size semiconductor device, how to increase metallic copper and lower floor's connecting hole to punctual process window, become the problem needing in the industry to solve.
In prior art, another kind of method is formed by forming a kind of sacrifice layer can removed in special process, after completing current metal interconnecting layer and a rear metal interconnecting layer, at special process, such as, removes sacrifice layer in heating process, to form air gap; But the method has problem equally, the sacrifice layer that the method is formed is that entirety is covered on interlayer dielectric layer, therefore after follow-up whole removal, often form large area air gap, the size of the air gap formed not easily adjusts, greatly reduce the mechanical anti-pressure ability of device, even therefore the subsiding of metal interconnecting layer in device, the serious performance reducing semiconductor device.
Therefore, in Damascus technics, how to regulate the size of air gap, to reduce dielectric layer overall dielectric constant and to keep the balance between mechanical anti-pressure ability, become the problem that another needs to solve.
Summary of the invention
The object of this invention is to provide a kind of manufacture method with the dual damascene damascene structure of air gap of half interstitital texture of size adjustable.
For solving the problem, the invention provides a kind of manufacture method with the dual damascene damascene structure of air gap, comprising the following steps:
There is provided Semiconductor substrate, described Semiconductor substrate is formed with successively the first interlayer dielectric layer and at least one sacrificial structure, the material of described sacrificial structure is can the polymer of thermal decomposition;
Described sacrificial structure both sides and the first interlayer dielectric layer form supporting layer and sacrifice layer successively;
Etch described sacrificial structure and the first interlayer dielectric layer, to form through hole in described sacrificial structure and the first interlayer dielectric layer;
Carry out thermal decomposition, remove remaining sacrificial structure, form groove;
Metal throuth hole connector and metal connecting line layer is formed in described through hole and groove;
Etch described sacrifice layer, form gap;
Form the second interlayer dielectric layer, in described gap, form air gap.
Further, the temperature of described thermal decomposition process is higher than the decomposition temperature of described sacrificial structure.
Further, the material of described supporting layer is one in silicon oxide carbide, silicon dioxide, porous silicon or its combination in any.
Further, the material of described first interlayer dielectric layer is one in low dielectric constant materials, silicon oxide carbide, silica or silicon oxynitride or its combination.
Further, the material of described sacrifice layer is one in low dielectric constant materials, silica or silicon oxynitride or its combination in any.
Further, the material of described cap layer is one in low dielectric constant materials, porous silicon, silica or silicon oxynitride or its combination in any.
Further, the cross-sectional width of described groove is less than or equal to the cross-sectional width of sacrificial structure.
The present invention also provides a kind of manufacture method with the dual damascene damascene structure of air gap, comprises the following steps:
There is provided Semiconductor substrate, described Semiconductor substrate is formed with the first interlayer dielectric layer and at least one sacrificial structure, the material of described sacrificial structure is can the polymer of thermal decomposition;
Described sacrificial structure both sides and the first interlayer dielectric layer cover supporting layer and fills sacrifice layer, the material of described sacrifice layer is can the polymer of thermal decomposition;
Etch described sacrificial structure and the first interlayer dielectric layer, to form through hole at described sacrificial structure and the first interlayer dielectric layer;
Carry out first time thermal decomposition, remove remaining sacrificial structure, to form groove;
Fill in described through hole and groove and form metal throuth hole connector and metal connecting line layer;
Described sacrifice layer and metal connecting line layer cover cap layer, and the material of described cap layer is porous mass;
Carry out second time thermal decomposition, decompose described sacrifice layer, to form air gap, and form the second interlayer dielectric layer in described cap layer.
Further, the decomposition temperature of described sacrifice layer is higher than the decomposition temperature of described sacrificial structure, the decomposition temperature that the temperature of described first time thermal decomposition states sacrificial structure higher than described lower than the decomposition temperature of described sacrifice layer, the temperature of described second time thermal decomposition is higher than the heat decomposition temperature of described sacrifice layer.
Further, the material of described supporting layer is one in silicon oxide carbide, silicon dioxide, porous silicon or its combination in any.
Further, the material of described first interlayer dielectric layer is one in low dielectric constant materials, silicon oxide carbide, silica or silicon oxynitride or its combination.
Further, the material of described cap layer is porous mass.
Further, the cross-sectional width of described groove is less than or equal to the cross-sectional width of sacrificial structure.
The manufacture method of dual damascene damascene structure of the present invention, first by forming sacrifice layer in interlayer dielectric layer, and utilize the method for etching or thermal decomposition to remove part or all of sacrifice layer, thus form air gap in dual damascene damascene structure device; Secondly, by formed can in subsequent technique thermal decomposition remove sacrificial structure to define position and the size of metal connecting line layer, described sacrificial structure forms groove after removing, formation process is simple and easy to realize, and avoids the problem of the dielectric constant values rising that the etching injury of etching technics to interlayer dielectric layer causes; Then, by and first interlayer dielectric layer other at this sacrificial structure form supporting layer, thus the air gap formed is half filling, the size of air gap can be kept and maintain the mechanical stability of interlayer dielectric layer, therefore, the lower and good mechanical stability of device of the dielectric constant with the interlayer dielectric layer of the dual damascene damascene structure device of air gap of formation.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of the dual damascene damascene structure in the embodiment of the present invention one with air gap.
Fig. 2 ~ Figure 12 is the structural representation of the manufacturing process of the dual damascene damascene structure in the embodiment of the present invention one with air gap.
Figure 13 is the schematic flow sheet of the manufacture method of the dual damascene damascene structure in the embodiment of the present invention two with air gap.
Figure 14 ~ Figure 16 is the structural representation of the manufacturing process of the dual damascene damascene structure in the embodiment of the present invention two with air gap.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is, by forming sacrifice layer in interlayer dielectric layer, and utilize the method for etching or thermal decomposition to remove part or all of sacrifice layer, thus air gap is formed in dual damascene damascene structure device, wherein, first formed can in subsequent technique the position of the sacrificial structure definition metal connecting line layer that thermal decomposition is removed and size, to increase the accuracy of aiming at of metal interconnecting layer and lower via hole connector; Secondly, by and first interlayer dielectric layer other at this sacrificial structure form supporting layer, to regulate the size of air gap and to improve the mechanical stability of interlayer dielectric layer, thus the lower and good mechanical stability of the dielectric constant forming interlayer dielectric layer and there is the dual damascene damascene structure device of air gap.
[embodiment one]
Fig. 1 is the schematic flow sheet of the manufacture method of the dual damascene damascene structure in one embodiment of the invention with air gap, described in there is the manufacture method of the dual damascene damascene structure of air gap, comprising:
Step S01: provide Semiconductor substrate, described Semiconductor substrate is formed with successively the first interlayer dielectric layer and at least one sacrificial structure, and the material of described sacrificial structure is can the polymer of thermal decomposition;
Step S02: cover supporting layer and fill sacrifice layer on described sacrificial structure both sides and the first interlayer dielectric layer;
Step S03: utilize photoetching and etching technics, etches described sacrificial structure and the first interlayer dielectric layer, to form through hole in described first interlayer dielectric layer;
Step S04: carry out thermal decomposition, removes remaining sacrificial structure, to form groove on described first interlayer dielectric layer;
Step S05: fill in described through hole and groove and form metal throuth hole connector and metal connecting line layer;
Step S06: utilize photoetching and etching technics, etches described sacrifice layer, to form gap;
Step S07: cover the second interlayer dielectric layer, to form air gap in described gap.
Fig. 2 ~ Figure 12 is the structural representation of the manufacturing process of dual damascene damascene structure in one embodiment of the invention.The manufacture method of the dual damascene damascene structure with air gap is described in the present embodiment in detail below in conjunction with Fig. 2 ~ Figure 12.
As shown in Figures 2 and 3, in step S01, provide Semiconductor substrate 100, described Semiconductor substrate 100 can be the semiconductor material such as monocrystalline silicon, polysilicon or germanium silicon compound; Active circuit is formed in described Semiconductor substrate 100, include source region 101 and various doped region, such as N trap, P trap and lightly-doped source drain region (LDD), in addition other various element separation are also had, the necessary structures in order to form semiconductor device such as such as fleet plough groove isolation structure (STI); Said structure is determined according to actual semiconductor device process for making, is well known to those skilled in the art technology contents, therefore does not repeat them here.In the present embodiment, described Semiconductor substrate 100 is formed first interlayer dielectric layer 104 and at least one sacrificial structure 106 successively, can also be formed with etching barrier layer 102 between described first interlayer dielectric layer 100 and described first interlayer dielectric layer 104, described etching barrier layer 102 forms the effect playing etching stopping in via process in subsequent etching.
Concrete, step S01 comprises following process: first, described Semiconductor substrate 100 forms etching barrier layer 102, and the material of described etching barrier layer 102 can be silica, silicon nitride or silicon oxynitride etc., and chemical vapour deposition technique or physical vaporous deposition can be adopted to be formed; Then, described etching barrier layer 102 is formed the first interlayer dielectric layer 104, the material of described first interlayer dielectric layer 104 can be one in low dielectric constant materials, silicon oxide carbide, silica or silicon oxynitride or its combination, it is preferably wherein low-k (Low-K) material, to maintain the dielectric constant of the first interlayer dielectric layer 104 2 ~ 3, such as porous silicon, porous SiLK or silicon oxide carbide etc., described first interlayer dielectric layer 104 can adopt chemical vapour deposition technique or physical vaporous deposition to be formed; Then, described first interlayer dielectric layer 104 forms sacrificial film 106a, the material of described sacrificial film 106a is can the polymer of thermal decomposition, the copolymer (Copolymer of Copolymer of Butylnorbornene and Triethoxysilyl Norbornene) etc. of such as butyl norborene and the silica-based norborene of three ethoxies, described sacrificial film 106a can adopt the method for spin coating to be formed on described first interlayer dielectric layer 104, and cures; Then, on described sacrificial film 106a, the photoresist 200 of the first patterning is formed by the photoetching process of coating, exposure, development; Subsequently, with the photoresist 200 of described first patterning for mask, etch described sacrificial film 106a, to form at least one sacrificial structure 106 as shown in Figure 3, described sacrificial structure 106 is as the substitute in early stage of subsequent metal connecting line layer, the position of described sacrificial structure 106 and size are determined according to the position of technological requirement metal connecting line layer and size, and therefore first the position of described metal connecting line layer and size are determined by sacrificial structure 106, remove the photoresist 200 of the first patterning afterwards.
As shown in Figure 4 and Figure 5, in step S02, the side of described sacrificial structure 106 and the first interlayer dielectric layer 104 cover supporting layer 108, the material of described supporting layer 108 can be one in silicon oxide carbide, silicon dioxide, porous silicon or its combination in any, chemical vapour deposition technique or physical vaporous deposition deposition can be utilized to be formed, the dielectric constant of described supporting layer 108 controls 2 ~ 3, to maintain good dielectric properties; Then, deposition of sacrificial layer 110 on described supporting layer 108, the material of described sacrifice layer 110 can be one in low dielectric constant materials, silica or silicon oxynitride or its combination, the thickness of described sacrifice layer 110 is greater than the thickness of described sacrificial structure 106, to cover sacrificial structure 106 and supporting layer 108 completely, in the subsequent process steps of the present embodiment, in described sacrifice layer 110, form air gap (Air Gap) by etching technics; Then, carry out cmp, grinding, until expose the surface of described sacrificial structure 106, forms structure as shown in Figure 5.
As shown in Figure 6 and Figure 7, in step S03, in described sacrificial film 106, the photoresist 202 of the second patterning is formed by the photoetching process of coating, exposure, development, then with the photoresist 202 of the second patterning for sacrificial structure described in mask etching 106 and the first interlayer dielectric layer 104, to form through hole 300 as shown in Figure 7 in described first interlayer dielectric layer 104, remove the photoresist 202 of the second patterning afterwards.The cross-sectional width of described through hole 300 is less than or equal to the cross-sectional width of sacrificial structure 300.
In step S04, carry out thermal decomposition, described remaining sacrificial structure 106 evaporative removal in thermal decomposition process, the temperature of described thermal decomposition is higher than the decomposition temperature of described sacrificial structure, to form groove 301 as shown in Figure 8 on described first interlayer dielectric layer 104, described through hole 300 is arranged in described first interlayer dielectric layer 104, described groove 301 is positioned on described first interlayer dielectric layer 104, described groove 301 is connected with described through hole 300, in the step of follow-up formation metal connecting line layer, metal throuth hole connector is formed in described through hole 300, metal connecting line layer is formed in described groove 301.
As shown in Figure 9, in step S05, fill in described groove 301 and described through hole 300 and form metal connecting line layer 112 and metal throuth hole connector 114; Specifically comprise: first on described through hole 300, groove 301 and described sacrifice layer 110, deposition forms interconnection line barrier layer (not indicating in figure), the material on described interconnection line barrier layer can be one in titanium nitride, tantalum nitride, titanium or tantalum or its combine; Then, described interconnect barrier forms the thin metal seed layer of one deck; Then utilize described metal seed layer to electroplate, form metal interconnecting layer and fill described through hole 300 and groove 301; Then, carry out chemical mechanical milling tech, remove the metal interconnecting layer beyond groove 300, thus form metal throuth hole connector and metal connecting line layer in described through hole 300 and groove 301.
As shown in Figure 10, in step S06, first on described metal connecting line layer 112 and described sacrifice layer 110, form cap layer 114, the material of described cap layer 114 is one in low dielectric constant materials, silica or silicon oxynitride or its combination; Then, in the photoetching process of described cap layer 114 by coating, exposure, development, described sacrificial film 106 is formed the photoresist 204 of the 3rd patterning, utilizes photoetching and etching technics, etch described cap layer 114 and sacrifice layer 108, to form gap 302.
In step S07, form the second interlayer dielectric layer 500, to form air gap 400 in described gap 302, described second interlayer dielectric layer 500 can adopt chemical vapour deposition technique to be formed, because the cross-sectional width of air gap 400 is very little, in deposition process, deposit to fill described gap 302 completely, thus form air gap 400 in gap 302.Owing to there is described supporting layer 108 outside described air gap 400, thus the mechanical that improve around air gap 400, simultaneously when follow-up formation later layer metal interconnecting layer, when the through hole of later layer metal interconnecting layer and the out-of-alignment situation of groove of current metal interconnecting layer occur, when filling out copper material in through hole, copper material can not enter in the air gap 400 between current metal interconnecting layer, increases the process window that later layer metal connecting line layer is aimed at current layer metal connecting line layer.
[embodiment two]
Figure 13 is the manufacture method of the schematic flow sheet of the manufacture method of the dual damascene damascene structure in another embodiment of the present invention with air gap, described dual damascene damascene structure, comprises the following steps:
Step S11: provide Semiconductor substrate, described Semiconductor substrate is formed with the first interlayer dielectric layer and at least one sacrificial structure, and the material of described sacrificial structure is can the polymer of thermal decomposition;
Step S12: cover supporting layer and fill sacrifice layer on described sacrificial structure both sides and the first interlayer dielectric layer, the material of described sacrifice layer is can the polymer of thermal decomposition;
Step S13: utilize photoetching and etching technics, etches described sacrificial structure and the first interlayer dielectric layer, to form through hole;
Step S14: carry out first time thermal decomposition, removes remaining sacrificial structure, to form groove;
Step S15: fill in described through hole and groove and form metal throuth hole connector and metal connecting line layer;
Step S16: cover cap layer on described sacrifice layer and metal connecting line layer, the material of described cap layer is porous mass;
Step S17: carry out second time thermal decomposition, decomposes described sacrifice layer, to form air gap, and covers the second interlayer dielectric layer in described cap layer.
Figure 14 ~ Figure 15 is the structural representation of the manufacturing process of dual damascene damascene structure in another embodiment of the present invention, below on the basis of embodiment one, in conjunction with Figure 14 ~ Figure 15 and Fig. 2 ~ as 9, describe the manufacture method in the present embodiment with the dual damascene damascene structure of air gap in detail.
Composition graphs 2 ~ Fig. 3, the manufacture method in described step S11 is identical with the manufacture method of step S01 described in described embodiment one.
As shown in Figure 4 and Figure 5, described step S12 is on the basis of embodiment one step S02, the material of described sacrifice layer 110 is chosen as can the polymer of thermal decomposition, the material of described sacrifice layer 110 is with the copolymer (Copolymer of Copolymer of Butylnorbornene and Triethoxysilyl Norbornene) etc. that can be butyl norborene and the silica-based norborene of three ethoxies, because the length different decomposition temperature of organic compound substituting group kind and chain is just different, therefore the derivative of this compound has multiple, the decomposition temperature that can meet sacrifice layer 110 higher than the selection of the material of the decomposition temperature of sacrificial structure 106 all within thought range of the present invention, described sacrifice layer 110 can adopt the method for spin coating to be formed on described supporting layer 108, in the subsequent process steps of the present embodiment, be not thermal decomposited in first time thermal decomposition process, and in second time thermal decomposition process, decompose removal to form air gap (Air Gap).
Composition graphs 6 ~ Fig. 7, described step S13 are identical with the manufacture method of step S03 described in described embodiment one.
In described step S14, carry out first time thermal decomposition, described first time the heat decomposition temperature decomposition temperature of stating sacrificial structure 106 higher than described lower than the decomposition temperature of described sacrifice layer 110, thus ensure that described remaining sacrificial structure 106 is removed in first time thermal decomposition process, and sacrifice layer 110 still retains, form structure as shown in Figure 8.
Composition graphs 9, the forming process of described step S15 is identical with the forming process of step S05 in embodiment one.
As shown in figure 14, in described step S16, in embodiment one step S06 basis on, the material of described cap layer 114 is chosen as porous material, such as porous silicon or porous polymer etc., and the thickness of described cap layer 114 is determined according to the clearance of sacrifice layer.
As shown in Figure 15 and Figure 16, in described step S17, carry out second time thermal decomposition, the temperature of described second time thermal decomposition is higher than the heat decomposition temperature of described sacrifice layer, decompose described sacrifice layer 110, to form air gap 400, and cover the second interlayer dielectric layer 500 in described cap layer 114.The material of described cap layer 114 is chosen as porous material, in second time thermal decomposition process, can distribute after sacrifice layer 110 decomposes from the porous of cap layer 114.Wherein, the thickness of cap layer 114 temperature that is thinner or the second thermal decomposition is higher, the time is longer, sacrifice layer clearance is higher, the dielectric constant of semiconductor device is lower, but the corresponding reduction of mechanical resistance to compression stability, therefore the mechanical resistance to compression stability of semiconductor device is taken into account, can by the adjustment thickness of cap layer 114 or the temperature and time of the second thermal decomposition, to determine the clearance of sacrifice layer 110, while the dielectric constant reducing semiconductor device, maintain mechanical resistance to compression stability, improve the performance of semiconductor device.
In sum, the manufacture method of dual damascene damascene structure of the present invention, first by forming sacrifice layer in interlayer dielectric layer, and utilize the method for etching or thermal decomposition to remove part or all of sacrifice layer, thus form air gap in dual damascene damascene structure device; Secondly, by formed can in subsequent technique thermal decomposition remove sacrificial structure to define position and the size of metal connecting line layer, described sacrificial structure forms groove after removing, formation process is simple and easy to realize, and avoids the problem of the dielectric constant values rising that the etching injury of etching technics to interlayer dielectric layer causes; Then, by and first interlayer dielectric layer other at this sacrificial structure form supporting layer, thus the air gap formed is half filling, the size of air gap can be kept and maintain the mechanical stability of interlayer dielectric layer, therefore, the lower and good mechanical stability of device of the dielectric constant with the interlayer dielectric layer of the dual damascene damascene structure device of air gap of formation.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (11)
1. there is a manufacture method for the dual damascene damascene structure device of air gap, comprise
There is provided Semiconductor substrate, described Semiconductor substrate is formed with successively the first interlayer dielectric layer and at least one sacrificial structure, the material of described sacrificial structure is can the polymer of thermal decomposition;
Described sacrificial structure both sides and the first interlayer dielectric layer form supporting layer and sacrifice layer successively;
Etch described sacrificial structure and the first interlayer dielectric layer, to form through hole in described sacrificial structure and the first interlayer dielectric layer;
Carry out thermal decomposition, remove remaining sacrificial structure, form groove;
Metal throuth hole connector and metal connecting line layer is formed in described through hole and groove;
Etch described sacrifice layer, form gap;
Form the second interlayer dielectric layer, in described gap, form air gap.
2. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 1, it is characterized in that, the temperature of described thermal decomposition process is higher than the decomposition temperature of described sacrificial structure.
3. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 1, it is characterized in that, the material of described supporting layer is one in silicon oxide carbide, silicon dioxide, porous silicon or its combination in any.
4. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 1, it is characterized in that, the material of described first interlayer dielectric layer is one in low dielectric constant materials, silica or silicon oxynitride or its combination.
5. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is one in low dielectric constant materials, silica or silicon oxynitride or its combination in any.
6. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 1, it is characterized in that, the cross-sectional width of described groove is less than or equal to the cross-sectional width of sacrificial structure.
7. there is a manufacture method for the dual damascene damascene structure device of air gap, it is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate is formed with the first interlayer dielectric layer and at least one sacrificial structure, the material of described sacrificial structure is can the polymer of thermal decomposition;
Described sacrificial structure both sides and the first interlayer dielectric layer cover supporting layer and sacrifice layer, and the material of described sacrifice layer is can the polymer of thermal decomposition;
Etch described sacrificial structure and the first interlayer dielectric layer, to form through hole at described sacrificial structure and the first interlayer dielectric layer;
Carry out first time thermal decomposition, remove remaining sacrificial structure, form groove;
Fill in described through hole and groove and form metal throuth hole connector and metal connecting line layer;
Described sacrifice layer and metal connecting line layer cover cap layer, and the material of described cap layer is porous mass;
Carry out second time thermal decomposition, decompose described sacrifice layer, to form air gap, and form the second interlayer dielectric layer in described cap layer.
8. there is the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 7, it is characterized in that, the decomposition temperature of described sacrifice layer is higher than the decomposition temperature of described sacrificial structure, the decomposition temperature that the temperature of described first time thermal decomposition states sacrificial structure higher than described lower than the decomposition temperature of described sacrifice layer, the temperature of described second time thermal decomposition is higher than the heat decomposition temperature of described sacrifice layer.
9. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 7, it is characterized in that, the material of described supporting layer is one in silicon oxide carbide, silicon dioxide, porous silicon or its combination in any.
10. have the manufacture method of the dual damascene damascene structure device of air gap as claimed in claim 7, it is characterized in that, the material of described first interlayer dielectric layer is one in low dielectric constant materials, silica or silicon oxynitride or its combination.
11. manufacture methods as claimed in claim 7 with the dual damascene damascene structure device of air gap, it is characterized in that, the cross-sectional width of described groove is less than or equal to the cross-sectional width of sacrificial structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110457697.1A CN103187362B (en) | 2011-12-31 | 2011-12-31 | There is the manufacture method of the dual damascene damascene structure device of air gap |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110457697.1A CN103187362B (en) | 2011-12-31 | 2011-12-31 | There is the manufacture method of the dual damascene damascene structure device of air gap |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187362A CN103187362A (en) | 2013-07-03 |
| CN103187362B true CN103187362B (en) | 2015-07-29 |
Family
ID=48678458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110457697.1A Active CN103187362B (en) | 2011-12-31 | 2011-12-31 | There is the manufacture method of the dual damascene damascene structure device of air gap |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187362B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105655288B (en) * | 2014-12-02 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105826279B (en) * | 2015-01-06 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN107195582B (en) * | 2017-07-03 | 2019-04-12 | 北方工业大学 | Diffusion barrier layer preparation method and copper interconnection structure |
| CN113097065A (en) * | 2020-01-09 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101828249A (en) * | 2007-10-18 | 2010-09-08 | 东京毅力科创株式会社 | Method and system for forming an air gap structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833320B2 (en) * | 2002-11-04 | 2004-12-21 | Intel Corporation | Removing sacrificial material by thermal decomposition |
-
2011
- 2011-12-31 CN CN201110457697.1A patent/CN103187362B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101828249A (en) * | 2007-10-18 | 2010-09-08 | 东京毅力科创株式会社 | Method and system for forming an air gap structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187362A (en) | 2013-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8138082B2 (en) | Method for forming metal interconnects in a dielectric material | |
| US10396026B2 (en) | Precut metal lines | |
| US7871923B2 (en) | Self-aligned air-gap in interconnect structures | |
| JP6068492B2 (en) | Low dielectric constant dielectric protective spacer for forming through-substrate via pattern in low dielectric constant wiring layer | |
| US9613880B2 (en) | Semiconductor structure and fabrication method thereof | |
| US20090212334A1 (en) | Semiconductor device and a method for manufacturing the same | |
| TW201810591A (en) | Semiconductor device and method for manufacturing the same | |
| TWI575582B (en) | Methods of forming contact structures for semiconductor devices and the resulting devices | |
| TW201732931A (en) | Semiconductor structure and manufacturing method thereof | |
| CN103165414B (en) | The method forming the pattern for semiconductor device | |
| US7939445B1 (en) | High density via and metal interconnect structures, and methods of forming the same | |
| US8637400B2 (en) | Interconnect structures and methods for back end of the line integration | |
| CN102324400A (en) | Method for manufacturing copper interconnection structure | |
| CN103515300A (en) | Method for forming air gap in metal interconnection process | |
| CN103187362B (en) | There is the manufacture method of the dual damascene damascene structure device of air gap | |
| US20150187601A1 (en) | Interconnect structure and method for forming the same | |
| CN102760688B (en) | Dual damascene structure and formation method thereof as well as semiconductor device | |
| CN108447820B (en) | Apparatus for multiple patterning with non-chamfered vias and method of forming non-chamfered vias | |
| WO2008151166A1 (en) | Damascene process having retained capping layer through metallization for protecting low-k dielectrics | |
| CN107591389A (en) | The interconnection of interior sacrificial spacer | |
| CN103066014A (en) | Copper/ air gap preparation method | |
| CN104143528B (en) | The forming method of interconnection structure | |
| US7851353B2 (en) | Method of forming a metal silicide layer, devices incorporating metal silicide layers and design structures for the devices | |
| CN108630651A (en) | On-chip capacitance device with chinampa | |
| US9607885B2 (en) | Semiconductor device and fabrication method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |