CN105826279B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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Abstract
A kind of semiconductor structure and forming method thereof, including：Substrate is provided, the substrate surface has the first device layer；First through hole is formed in first device layer；Sacrificial layer is formed in the sidewall surfaces of the first through hole；After forming the sacrificial layer, the bottom that the first through hole exposes is etched, the second through-hole is formed in the substrate and the first device layer；Plug structure is formed in second through-hole；The sacrificial layer is removed, gap is formed between the plug structure and the first device layer.The electrical property of the semiconductor structure improves, reliability improves.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the continuous development of semiconductor fabrication, the characteristic size of semiconductor devices constantly reduces, and the collection of chip
It is higher and higher at spending.However, current two-dimensional package structure has been difficult to meet growing chip integration demand, therefore three
Tieing up encapsulation technology becomes the key technology for crossing over integrated chip bottleneck.
Three-dimensional stacked technology based on silicon hole (Through Silicon Via, abbreviation TSV) structure is existing three-dimensional
One kind in encapsulation technology, the three-dimensional stacked technology based on silicon hole are to improve one of the main method of chip integration.
The three-dimensional stacked technology based on through-silicon via structure has the following advantages：High Density Integration；Significantly shorten electricity
The length of interconnection, so as to well solve the problems such as appearing in the signal delay in two-dimentional system grade chip technology；It utilizes
Silicon hole technology can integrate the chip (such as radio frequency, memory, logic, MEMS) with different function to realize
Encapsulate the multi-functional of chip.
Include the conductive plunger through substrate in the through-silicon via structure, the conductive plunger can will be formed with device
Several substrates of part layer stack setting, and so that the device layer positioned at several substrate surfaces is electrically connected by the conductive plunger,
To make integrated chip.
However, with the continuous development of semiconductor technology, device density is continuously improved, and device feature size constantly contracts
Small, the performance for also having correspondingly caused through-silicon via structure is bad, is easy that packaging performance is caused to decline or fail.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, the semiconductor structure it is electrical
It can improve, reliability improves.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate surface has the first device layer；First through hole is formed in first device layer；In the side wall table of the first through hole
Face forms sacrificial layer；After forming the sacrificial layer, the bottom that the first through hole exposes is etched, in the substrate and the
The second through-hole is formed in one device layer；Plug structure is formed in second through-hole；The sacrificial layer is removed, in the plug
Gap is formed between structure and the first device layer.
Optionally, the forming step of the sacrificial layer includes：In first device layer surface and the first through hole
Side wall and bottom surface formed expendable film；The expendable film for removing the first through hole bottom, forms the sacrificial layer.
Optionally, the sacrificial layer is also formed into first device layer surface.
Optionally, the technique of the expendable film of removal first through hole bottom is anisotropic dry etch process.
Optionally, the anisotropic dry etch process is no mask etching technique.
Optionally, the material of the sacrificial layer is one or more in amorphous carbon, amorphous silicon or polysilicon；Removal
The technique of the sacrificial layer is plasma dry cineration technics.
Optionally, the depth of the first through hole is greater than or equal to the 10% of first device layer thickness.
Optionally, the substrate includes opposite first surface and second surface, and first device layer is located at the lining
The first surface at bottom.
Optionally, further include：After forming the gap, the second surface of the substrate is thinned, until sudden and violent
Until the top surface for exposing the plug structure.
Optionally, further include：After forming the gap, before the second surface of the substrate is thinned,
First device layer surface forms separation layer, and the separation layer is suitable for being in contact with the pedestal of reduction process equipment.
Optionally, the material of the separation layer is one or more in silica, silicon nitride or silicon oxynitride；It is described every
The formation process of absciss layer is chemical vapor deposition method.
Optionally, the plug structure includes：Positioned at the insulating layer of the second through-hole side wall and bottom surface；Positioned at insulating layer
The conductive plunger of surface and full second through-hole of filling.
Optionally, the forming step of the plug structure includes：In first device layer surface and the second through-hole
Side wall and bottom surface form insulating film；Conductive film is formed in the insulating film surface；Planarize the conductive film and insulating film
Until exposing first device layer surface, the insulating layer and conductive plunger are formed.
Optionally, the material of the conductive plunger is copper；The material of the insulating layer is silica, silicon nitride, nitrogen oxidation
It is one or more in silicon.
Optionally, the substrate includes semiconductor base and the second device layer positioned at semiconductor substrate surface；Described
One device layer is located at second device layer surface.
Optionally, second device layer include device architecture, conductive structure and device architecture and conductive structure it
Between the second dielectric layer that is electrically isolated.
Optionally, first device layer includes interconnection layers and is electrically isolated between the interconnection layers
First medium layer.
Optionally, the formation process of the first through hole is more dry etching technics；The formation work of second through-hole
Skill is more dry etching technics.
Optionally, the multistep etching technics includes：It is passivated etching, forms etching in the first device layer or substrate
Through-hole, the etching through hole inner wall surface have passivation layer；Depassivation etching is carried out, the passivation of etching through hole bottom surface is removed
Layer；Main etching is carried out, after depassivation etching, etching through hole bottom is performed etching, the depth of etching through hole is made to increase；Weight
The multiple passivation etching, depassivation etching and main etch step, until forming first through hole or the second through-hole.
Correspondingly, present invention offer is a kind of to be formed by semiconductor structure using any of the above-described method, including：Substrate,
The substrate surface has the first device layer；The second through-hole in the substrate and the first device layer；Positioned at described second
Plug structure in through-hole；Gap between the plug structure and the first device layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the forming method of the present invention, first through hole is formed in the first device layer of substrate surface first；Described
The sidewall surfaces of one through-hole form sacrificial layer；The bottom exposed again to the first through hole performs etching, until in substrate and
The second through-hole is formed in first device layer, second through-hole is used to form plug structure；After forming plug structure, removal
Made sacrificial layer can form gap between plug structure and the first device layer.The gap can be used as plug structure
Buffering between device layer is avoided because of the coefficient of thermal expansion difference between the plug structure and the first device layer, in technique
It causes the first device layer of the plug structure pair to squeeze in processing procedure, to avoid first device layer from being stressed, ensure that
The structure and performance of first device layer are stablized.Moreover, because having between the plug structure and first device layer
Gap is isolated, and shows so as to avoid the material atom in the plug structure that electromigration occurs in first device layer surface
As ensure that the performance of the plug structure and the first device layer is stablized.Therefore, it is formed by the reliability of semiconductor structure
It improves, performance improvement.
In the structure of the present invention, due to having gap between the plug structure and the first device layer, the gap can
As the buffering between plug structure and device layer, avoid because of the coefficient of thermal expansion between the plug structure and the first device layer
Difference causes the first device layer of the plug structure pair to cause to squeeze, and to avoid first device layer from being stressed, ensures
The structure and performance of first device layer are stablized.Moreover, because having between the plug structure and first device layer
There is gap isolation, so as to avoid the material atom in the plug structure that electromigration occurs in first device layer surface
Phenomenon ensure that the performance of the plug structure and the first device layer is stablized.Therefore, it is formed by the reliable of semiconductor structure
Property improve, performance improvement.
Description of the drawings
Fig. 1 and Fig. 2 is a kind of schematic diagram of through-silicon via structure of the embodiment of the present invention；
Fig. 3 to Figure 11 is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Specific implementation mode
As stated in the background art, the pattern of through-silicon via structure is bad, electrical property is bad.
Please refer to Fig.1 and Fig. 2, Fig. 1 and Fig. 2 be the embodiment of the present invention a kind of through-silicon via structure schematic diagram, Fig. 2 is figure
1 overlooking structure diagram, Fig. 1 are cross-sectional views of the Fig. 2 along the directions AA ', including：Substrate；Positioned at 100 surface of substrate
Device layer 101, there is in the device layer 101 electrical interconnection line 110；Plug in the device layer 101 and substrate 100
Structure 102, the plug structure 102 run through the device layer 101 and substrate 100, and the plug structure 102 includes：Conduction is inserted
Plug 120 and positioned at 120 sidewall surfaces of conductive plunger insulating layer 121.
The technique and subsequent technique for forming the conductive plunger 120 have pyroprocess, in order to meet two layers of difference
Electrical transmission between 100 surface device of substrate, the cross-sectional area of the conductive plunger 120 is larger, moreover, the device layer
101 is different from the coefficient of thermal expansion of the conductive plunger 120, therefore, in the pyroprocess, the conductive plunger 120
Material occur to thermally expand it is serious compared with device layer, to can cause to squeeze to the device layer 101, make the device layer 101 by
Stress.
And as the density of semiconductor devices increases, the electrical interconnection line and the conductive plunger 120 that are located in device layer 101
The distance between center D constantly reduces, and in the case where the device layer 101 is stressed, the conductive plunger 120 and electricity are mutual
Electromigration effect enhancing between line 110.Under electric field action, the metallic atom in the conductive plunger 120 is easy in institute
The surface for stating device layer 101 is migrated to the electrical interconnection line 110, and when the device layer 101 has stress, the metal is former
The transfer ability enhancing of son, more easily causes and short circuit occurs between the conductive plunger 120 and electrical interconnection line 110, influence to be formed
Semiconductor devices performance.
To solve the above-mentioned problems, a kind of semiconductor structure of present invention offer and forming method thereof.In the forming method
In, first first through hole is formed in the first device layer of substrate surface；It is formed and is sacrificed in the sidewall surfaces of the first through hole
Layer；The bottom exposed again to the first through hole performs etching, until the second through-hole is formed in substrate and the first device layer,
Second through-hole is used to form plug structure；After forming plug structure, made sacrificial layer is removed, it can be in plug knot
Gap is formed between structure and the first device layer.The gap can as the buffering between plug structure and device layer, avoid because
Coefficient of thermal expansion difference between the plug structure and the first device layer causes the plug structure pair in manufacturing process
One device layer squeezes, and to avoid first device layer from being stressed, ensure that the structure and performance of first device layer
Stablize.Moreover, because there is gap isolation, so as to avoid described insert between the plug structure and first device layer
In first device layer surface ELECTROMIGRATION PHENOMENON occurs for material atom in plug structure, ensure that the plug structure and the
The performance of one device layer is stablized.Therefore, reliability raising, the performance improvement of semiconductor structure are formed by.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 11 is the cross-sectional view of the forming process of the semiconductor structure of the embodiment of the present invention.
Referring to FIG. 3, providing substrate 200,200 surface of the substrate has the first device layer 201.
In the present embodiment, the substrate 200 includes opposite first surface 210 and second surface 220, first device
Part layer 201 is located at the first surface 210 of the substrate 200.First device layer 201 is in last part technology (Back-End Of
Line, abbreviation BEOL) in formed, first device layer 201 include interconnection layers and between the interconnection layers into
The first medium layer that row is electrically isolated, the semiconductor devices that first device layer 201 is used to make to be formed in the substrate 200 carry out
It is electrically interconnected.
The material of the interconnection layers is conductive material, and the conductive material includes copper, tungsten, aluminium, silver, titanium, tantalum, titanium nitride
Or it is one or more in tantalum nitride.The material of the first medium layer is silica, silicon nitride, silicon oxynitride, low-K dielectric material
It is one or more in material or ultralow K dielectric materials.
In the present embodiment, the substrate 200 includes semiconductor base and the second device positioned at semiconductor substrate surface
Layer；First device layer 201 is located at second device layer surface.Wherein, the surface of second device layer, that is, lining
The first surface at bottom 200.
The semiconductor base be silicon substrate, germanium substrate, silicon-on-insulator substrate, silicon-Germanium substrate, silicon carbide substrates or
III-V compound substrate (such as gallium nitride or GaAs).In the present embodiment, the semiconductor base is silicon substrate.
Second device layer includes device architecture, the conductive structure being electrically connected with the device architecture and in device
The second dielectric layer being electrically isolated between structure and conductive structure.Second device layer is in front process (Front-End
Of Line, abbreviation FEOL) in formed.
The device architecture includes：Gate structure, capacitance structure, electric resistance structure, storage unit, the fuse knot of transistor
Structure, sensor structure.The conductive structure includes：Positioned at semiconductor substrate surface and device architecture surface conductive plunger, with
And the electrical interconnection line at the top of conductive plunger；The material of the conductive structure be metal, the metal include copper, tungsten, aluminium,
It is one or more in silver, titanium, tantalum, titanium nitride or tantalum nitride.The second dielectric layer is for protecting the device architecture and electricity
Interconnection line, and for making disjunct device architecture and electrical interconnection line be electrically isolated from each other, the material of the second dielectric layer is oxygen
SiClx, silicon nitride, silicon oxynitride, low-K dielectric material or ultralow K dielectric materials.
Referring to FIG. 4, forming first through hole 202 in first device layer 201.
The sidewall surfaces of the first through hole 202 need to form sacrificial layer, and the first through hole 202 for forming sacrificial layer is used for
Form part plug structure, so as to after removal of the sacrificial layer, plug structure and the side wall of the first through hole 202 it
Between form gap, the thermal expansion of the plug structure is buffered with the gap, with this eliminate the first device layer 201 acquisition answer
Power.
10% of the depth of the first through hole 202 more than or equal to 201 thickness of the first device layer, and described first
The depth of through-hole 202 is subsequently formed by the depth in gap；In order to ensure that the gap being subsequently formed is capable of providing sufficient space
To buffer the thermal expansion of plug structure, the depth of the first through hole 202 is unsuitable too small；Further, since follow-up need described
The sidewall surfaces of first through hole form sacrificial layer, and sacrificial layer thickness is uniform in order to ensure to be formed by, the first through hole 202
Depth is unsuitable too deep, and no it will cause the depth-to-width ratio of the first through hole 202 is larger, the formation process that can improve sacrificial layer is difficult
Degree, reduces the uniformity of sacrificial layer.
In the present embodiment, 202 bottom-exposed of the first through hole goes out 200 surface of the substrate, i.e., the described first through hole
202 depth is the thickness of first device layer 201.In other embodiments, the bottom of the first through hole can be less than
Or it is higher than 200 surface of the substrate.
Due to subsequently needing the sidewall surfaces in the first through hole 202 to form sacrificial layer, the first through hole
202 aperture needs the aperture for being more than the plug structure being subsequently formed；Specifically, the aperture of the first through hole 202 is described
The aperture of plug structure adds twice of the sacrificial layer thickness being subsequently formed.In the present embodiment, the hole of the first through hole 202
Diameter is 1 micron~100 microns.
Since the depth of the first through hole 202 is unsuitable too small, the depth of the first through hole 202 is larger, i.e. institute
The depth-to-width ratio for stating first through hole 202 is larger, in order to ensure that the pattern for being formed by first through hole 202 is superior, ensures described first
The side wall of through-hole 202 is perpendicular to 201 surface of the first device layer.
The processing step of the first through hole 202 includes：Mask layer is formed on 201 surface of the first device layer, it is described
Mask layer exposes the corresponding region for needing to form first through hole 202；Using the mask layer as mask, first device is etched
Layer 201, forms the first through hole 202.
The technique for etching first device layer 201 is anisotropic dry etch process, and described anisotropic
Dry etch process is dry etch process.The multistep etching technics includes：It is passivated etching, in the first device layer 201
Or etching through hole is formed in substrate 200, the etching through hole inner wall surface has passivation layer；Depassivation etching is carried out, removal is carved
Lose the passivation layer on via bottoms surface；Main etching is carried out, the first device layer 201 exposed is etched, in the first device layer 201
Form etching；The passivation etching, depassivation etching and main etch step are repeated, until forming first through hole 202.
The gas of the passivation etching technics includes carbon fluorine gas and carrier gas；The carbon fluorine gas includes CF4、C3F8、C4F8、
CH2F2、CH3F、CHF3In it is one or more；The carrier gas includes Ar, He or N2One or more of.The passivation is carved
Etching technique can be formed being formed by etching through hole inner wall surface using polymer as the passivation layer of material, meanwhile, the passivation
Etching technics can also consume the part polymer material, and the thickness of passivation layer is formed by with control.
The gas of depassivation etching technics includes SF6And carrier gas；The carrier gas includes Ar, He or N2In one kind or several
Kind.The depassivation etching technics is used to remove the passivation layer of etching through hole bottom surface, to expose the bottom of etching through hole
Surface, subsequently to carry out main etching to the etching through hole bottom, to deepen the depth of etching through hole.
The main etching gas SF6And carrier gas；The carrier gas includes Ar, He or N2One or more of.The master
Etching technics is identical as the gas flow of the depassivation etching technics, bias voltage, plasma source power or bias power
Or it is different.The main etching technique is used to deepen the depth of etching through hole, in the main etching technique, due to etching through hole
Sidewall surfaces have a passivation layer protection not being removed, thus it is described live etching technics only to the etching through hole bottom that exposes into
Row etching, while deepening the etching through hole depth, will not cause to consume, so as to make most to the side wall of etching through hole
End form at first through hole 202 side wall perpendicular to the surface of the first device layer 201.
The material of the mask layer includes in Other substrate materials, silicon nitride, amorphous carbon, titanium, titanium nitride, tantalum or tantalum nitride
One in or it is a variety of.In the present embodiment, after forming the first through hole 202, the mask layer is removed.
Referring to FIG. 5, in 201 surface of the first device layer and the side wall and bottom surface of the first through hole 202
Form expendable film 203.
The expendable film 203 is used to form the sacrificial layer positioned at 202 sidewall surfaces of first through hole, and the sacrificial layer defines
It is subsequently formed structure size and the position in the gap between plug structure and the first device layer 201.
The material of the expendable film 203 is one or more combinations in polysilicon, amorphous silicon or amorphous carbon；It is described
Expendable film 203, which needs to use, to be easily removed, and has higher etching with the first device layer 201 and the plug structure being subsequently formed
The material for selecting ratio can reduce the damage to first device layer 201 and plug structure in subsequently removal sacrificial layer,
And the by-product remained in gap can be reduced.
The formation process of the expendable film 203 is chemical vapor deposition method, physical gas-phase deposition or atomic layer deposition
Product technique；The thickness of the expendable film 203 is 100 angstroms~100000 angstroms.The thickness of the expendable film 203 is subsequently formed sacrificial
The thickness of domestic animal layer, therefore the thickness of the expendable film 230 determines the plug structure that is subsequently formed to 201 side wall of the first device layer
Distance, i.e., the width in the described gap；And the gap provides thermal expansion cushion space for the plug structure being subsequently formed, institute
The width for stating gap is unsuitable narrow, and the cushion space otherwise thermally expanded is insufficient, and the width in the gap also should not be too large, otherwise can
Increase is formed by semiconductor structure the space occupied area.
Referring to FIG. 6, the expendable film 203 (as shown in Figure 5) of 202 bottom of the first through hole is removed, it is logical described first
The sidewall surfaces in hole 202 form sacrificial layer 203a.
The technique for removing the expendable film 203 of first through hole 202 bottom is anisotropic dry etch process, it is described respectively to
The etching direction of anisotropic dry etch process is located at first perpendicular to 201 surface of the first device layer, so as to retain
The partial sacrifice film 203 of 202 sidewall surfaces of through-hole, to form sacrificial layer 203a.
In the present embodiment, the etching technics of the sacrificial layer 203a is formed as no mask etching technique, the etching work
Skill is when etching the expendable film 203 of 202 bottom surface of first through hole, also to the partial sacrifice positioned at 201 surface of the first device layer
Film 203 performs etching.In the present embodiment, since the depth-to-width ratio of the first through hole 202 is larger, it is used to form expendable film 203
Material gas be difficult to enter the first through hole bottom, then be formed in 203 thickness of expendable film of 202 bottom surface of first through hole
Less than 203 thickness of expendable film for being formed in 201 surface of the first device layer, therefore, when etching the expendable film 203, etching
When the expendable film 203 of complete 202 bottom surface of the first through hole, the expendable film 203 on 201 surface of the first device layer is not yet complete
The full removal that is etched, therefore 201 surface of the first device layer still has partial sacrifice film 203.Therefore, in the present embodiment, institute
It states sacrificial layer 203a and is also formed into 201 surface of the first device layer.
In other embodiments, when having etched the expendable film 203 of 202 bottom surface of the first through hole, described first
The expendable film 203 on 201 surface of device layer is also completely removed, then the sacrificial layer 203a is only formed in the first through hole 202
Sidewall surfaces.
In other embodiments, it before etching the expendable film 203, is formed graphically on 203 surface of the expendable film
Layer, the patterned layer exposes the first through hole 202, is mask with the expendable film 203, using anisotropic dry method
Etching technics etches the expendable film 203, removes the expendable film 203 of 202 bottom surface of first through hole, forms the sacrificial layer
203a；After forming the sacrificial layer 203a, the patterned layer is removed.
The anisotropic dry etch process parameter for etching the expendable film 203 includes：Etching gas includes carbon fluorine gas
Body, O2And carrier gas, the flow of etching gas is 50sccm~1000sccm, and gas pressure is 1mtorr~50mtorr, biased electrical
Pressure is 10V~500V, and power is 100W~800W, and temperature is 40 DEG C~200 DEG C；The carbon fluorine gas includes CF4、C3F8、C4F8、
CH2F2、CH3F、CHF3In it is one or more；The carrier gas is Ar, He or N2One or more of.
Referring to FIG. 7, after forming the sacrificial layer 203a, the exposure (as shown in Figure 6) of the first through hole 202 is etched
The bottom gone out forms the second through-hole 204 in the substrate 200 and the first device layer 201.
Second through-hole 204 is used to form plug structure.In the present embodiment, since the sacrificial layer 203a is located at institute
202 sidewall surfaces of 201 surface of the first device layer and first through hole are stated, before etching forms the second through-hole 204, without additional
Mask layer is formed, the bottom that the first through hole 202 exposes can be etched using the sacrificial layer 203a as mask.
In the present embodiment, 202 bottom-exposed of the first through hole goes out 200 surface of substrate, then forms the second through-hole 204
Technique performs etching the substrate 200 exposed, until forming the second through-hole 204.
In another embodiment, the first through hole bottom surface is higher than substrate surface, i.e., the described first through hole bottom tool
The first device layer for having segment thickness then forms the etching technics of second through-hole first to the first device of first through hole bottom
Part layer later again performs etching the substrate exposed up to exposing substrate surface until forming the second through-hole.
In other embodiments, the first through hole bottom surface is less than the substrate surface, i.e., the described first through hole bottom
Portion stretches into the substrate 200, and the first through hole bottom-exposed goes out substrate, then forms the etching technics pair of second through-hole
The substrate exposed performs etching, until forming the second through-hole.
The aperture of second through-hole 204 be 1 micron~100 microns, that is, the aperture of first through hole 202 subtract it is sacrificial
Twice of 203 thickness of domestic animal film；The depth of second through-hole 204 is 30 microns~100 microns.Due to second through-hole 204
Depth it is larger, the depth-to-width ratio of second through-hole 204 is larger, and the formation process of second through-hole 204 is that more dry is carved
Etching technique.
The multistep etching technics includes：Be passivated etching, 202 bottom of first through hole the first device layer 201 or
Etching through hole is formed in substrate 200, and forms passivation layer in the etching through hole inner wall surface；Carry out depassivation etching, removal
The passivation layer of etching through hole bottom surface；Main etching is carried out, after depassivation etching, etching through hole bottom is performed etching,
The depth of etching through hole is set to increase；The passivation etching, depassivation etching and main etch step are repeated, until forming the second through-hole
204。
The gas of the passivation etching technics includes carbon fluorine gas and carrier gas；The carbon fluorine gas includes CF4、C3F8、C4F8、
CH2F2、CH3F、CHF3In it is one or more；The carrier gas includes Ar, He or N2One or more of.The passivation is carved
Etching technique can be formed being formed by etching through hole inner wall surface using polymer as the passivation layer of material, meanwhile, the passivation
Etching technics can also consume the part polymer material, and the thickness of passivation layer is formed by with control.
The gas of depassivation etching technics includes SF6And carrier gas；The carrier gas includes Ar, He or N2In one kind or several
Kind.The depassivation etching technics is used to remove the passivation layer of etching through hole bottom surface, to expose the bottom of etching through hole
Surface, subsequently to carry out main etching to the etching through hole bottom, to deepen the depth of etching through hole.
The main etching gas SF6And carrier gas；The carrier gas includes Ar, He or N2One or more of.The master
Etching technics is identical as the gas flow of the depassivation etching technics, bias voltage, plasma source power or bias power
Or it is different.The main etching technique is used to deepen the depth of etching through hole, in the main etching technique, due to etching through hole
Sidewall surfaces have a passivation layer protection not being removed, thus it is described live etching technics only to the etching through hole bottom that exposes into
Row etching, while deepening the etching through hole depth, will not cause to consume, so as to make most to the side wall of etching through hole
End form at the second through-hole 204 side wall perpendicular to the surface of the first device layer 201.
Referring to FIG. 8, forming plug structure 205 in second through-hole 204 (as shown in Figure 7).
The plug structure 205 is used to form through-silicon via structure.The plug structure 205 includes：Positioned at the second through-hole 204
Side wall and the insulating layer of bottom surface 250；Positioned at 250 surface of insulating layer and the conductive plunger of filling completely second through-hole 204
251.The insulating layer 250 is for being electrically isolated the conductive plunger 251 and semiconductor base；The conductive plunger 251 is used for
It is electrically connected between the substrate 200 overlapped.
The forming step of the plug structure 205 includes：In 201 surface of the first device layer and the second through-hole 205
Side wall and bottom surface formed insulating film；Conductive film is formed in the insulating film surface；Planarize the conductive film and insulation
Film forms the insulating layer 250 and conductive plunger 251 until exposing 201 surface of the first device layer.
The material of the conductive film is one or more combinations in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, described
The formation process of conductive film includes chemical vapor deposition method, physical gas-phase deposition, electroplating technology or chemical plating process.
In the present embodiment, the material of the conductive film includes copper, and the formation process of the conductive film is electroplating technology；The electroplating technology
Including：Conductive seed layer is formed in insulating film surface using depositing operation；Using electroplating technology in the conductive seeds layer surface
Conductive material layer is grown, until full second through-hole of filling, forms conductive film；The material of the seed layer can be copper, tungsten,
One or more combinations in aluminium, titanium, tantalum, titanium nitride, tantalum nitride.
The material of the insulating layer 250 is one or more combinations in silica, silicon nitride, silicon oxynitride；It is described exhausted
The formation process of velum is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
In the present embodiment, the flatening process is CMP process；In the present embodiment, the chemical machine
Tool polishing process is additionally operable to sacrificial layer 203a of the removal positioned at 201 surface of the first device layer, makes to be formed by insulating layer 250 and lead
251 surface of electric plug is flushed with 201 surface of the first device layer.In other embodiments, the flatening process can also be nothing
Mask etching technique.
Referring to FIG. 9, the sacrificial layer 203a (as shown in Figure 8) is removed, in the plug structure 205 and the first device layer
Gap 206 is formed between 201.
The gap 206 is used to provide thermal expansion overdose space for plug structure 205, avoids the plug structure 205
Thermal expansion causes to squeeze to the first device layer 201, avoids first device layer 201 from being stressed effect, ensure that the first device
The electrical connection stability of interconnection layers in part layer 201；Also, the plug structure 205 and institute can be isolated in the gap 206
The first device layer is stated, avoids the metallic atom in the conductive plunger 251 that electromigration occurs on 201 surface of the first device layer, prevents
It is only short-circuit between the interconnection layers in the conductive plunger 251 and the first device layer 201, and improve the conductive plunger 251
Resistivity controllability.
In the present embodiment, the technique for removing the sacrificial layer 203a is plasma dry cineration technics；It is described it is equal from
In daughter dry ashing technique, process gas contains oxygen；The plasma dry cineration technics is isotropic etching
Technique.The parameter of the plasma dry cineration technics includes：Etching gas includes oxygen, and the flow of oxygen is 100sccm
~5000sccm, plasma source exciting power be 100W~2000W, bias power be 0~500W, etching temperature be 35 DEG C~
250 DEG C, etch period is 5s~200s.
In other embodiments, the technique for removing the sacrificial layer 203a can also be isotropic wet etching work
Skill.
Referring to FIG. 10, after forming the gap 206, separation layer is formed on 201 surface of the first device layer
207。
Due to subsequently needing the second surface 220 to the substrate 200 to be thinned, until exposing the conductive plunger
251 top surface therefore, it is necessary to overturn the substrate 200, and makes 201 surface of the first device layer be fixed on reduction process
On the pedestal of equipment.In order to avoid 201 surface of the first device layer is damaged in reduction process, need in first device
201 surface of layer form separation layer 207, and the separation layer 207 is suitable for being in contact with the pedestal of reduction process equipment.
The material of the separation layer 207 is one or more in silica, silicon nitride or silicon oxynitride；The separation layer
207 formation process is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.The separation layer
207 are not filled by in the gap 206, and the separation layer 207 is located at 206 top of the gap, and makes 206 envelope of the gap
It closes.
In the present embodiment, the material of the separation layer 207 is silica, and formation process is plasma enhanced chemical gas
Mutually deposition (PECVD) technique or high density plasma CVD (HDP CVD, High Density Plasma
Chemical Vapor Deposition) technique, plasma enhanced chemical vapor deposition technique or high-density plasma
Learning gas-phase deposition can be such that the material of separation layer 207 is piled up in first at the top of gap, can the gap 206 not by
Filling is closed when full.
Using plasma enhancing chemical vapor deposition method forms separation layer 207, the plasma in the present embodiment
Enhancing chemical vapor deposition method parameter includes：Pressure is the support of 1 support~10, and temperature is 360 degrees Celsius~420 degrees Celsius, radio frequency
Power is 400 watts~2000 watts, and the flow of oxygen is 500 standard milliliters/minute~4000 standard milliliters/minute, positive silicic acid second
The flow of ester is 500 standard milliliters/minute~5000 standard milliliters/minute, the flow of helium be 1000 standard milliliters/minute~
5000 standard milliliters/minute.
1 is please referred to Fig.1, after forming the separation layer 207, the second surface 220 of the substrate 200 is subtracted
It is thin, until the top surface for exposing the plug structure 205.
It is CMP process to carry out thinned technique to the second surface 220 of the substrate 200.It is inserted due to described
Plug structure 205 is formed in the second through-hole 205 (as shown in Figure 7), and the side wall and bottom surface of second through-hole 205 have absolutely
Edge layer 250, the conductive plunger 251 is located at 250 surface of the insulating layer, and the CMP process needs to remove position
In the insulating layer 250 of 205 bottom surface of the second through-hole, to expose the top surface of the conductive plunger 251, so as to follow-up energy
Enough second surfaces 220 in the substrate 200 form wiring layer or another substrate for being formed with device layer of bonding.
To sum up, in the present embodiment, first through hole is formed in the first device layer of substrate surface first；It is logical described first
The sidewall surfaces in hole form sacrificial layer；The bottom exposed again to the first through hole performs etching, until in substrate and first
The second through-hole is formed in device layer, second through-hole is used to form plug structure；After forming plug structure, removal is made
Sacrificial layer can form gap between plug structure and the first device layer.The gap can be used as plug structure and device
Buffering between part layer is avoided because of the coefficient of thermal expansion difference between the plug structure and the first device layer, in manufacturing process
In cause the first device layer of the plug structure pair squeeze, to avoid first device layer from being stressed, ensure that described
The structure and performance of first device layer are stablized.Moreover, because having gap between the plug structure and first device layer
Isolation, so as to avoid the material atom in the plug structure that ELECTROMIGRATION PHENOMENON occurs in first device layer surface,
It ensure that the performance of the plug structure and the first device layer is stablized.Therefore, the reliability for being formed by semiconductor structure carries
High, performance improvement.
Correspondingly, the embodiment of the present invention also provide it is a kind of semiconductor structure is formed by using the method, continuing with ginseng
Figure 11 is examined, including：Substrate 200,200 surface of the substrate have the first device layer 201；Positioned at the substrate 200 and the first device
The second through-hole in part layer 201；Plug structure 205 in second through-hole；Positioned at the plug structure 205 and first
Gap 206 between device layer 201.
In the present embodiment, the substrate 200 includes opposite first surface 210 and second surface 220, first device
Part layer 201 is located at the first surface 210 of the substrate 200.First device layer 201 is including interconnection layers and is located at institute
The first medium layer being electrically isolated between interconnection layers is stated, first device layer 201 is formed for making in the substrate 200
Semiconductor devices be electrically interconnected.
The material of the interconnection layers is conductive material, and the conductive material includes copper, tungsten, aluminium, silver, titanium, tantalum, titanium nitride
Or it is one or more in tantalum nitride.The material of the first medium layer is silica, silicon nitride, silicon oxynitride, low-K dielectric material
It is one or more in material or ultralow K dielectric materials.
In the present embodiment, the substrate 200 includes semiconductor base and the second device positioned at semiconductor substrate surface
Layer；First device layer 201 is located at second device layer surface.Wherein, the surface of second device layer, that is, lining
The first surface at bottom 200.
The semiconductor base be silicon substrate, germanium substrate, silicon-on-insulator substrate, silicon-Germanium substrate, silicon carbide substrates or
III-V compound substrate (such as gallium nitride or GaAs).In the present embodiment, the semiconductor base is silicon substrate.
Second device layer includes device architecture, the conductive structure being electrically connected with the device architecture and in device
The second dielectric layer being electrically isolated between structure and conductive structure.
The device architecture includes：Gate structure, capacitance structure, electric resistance structure, storage unit, the fuse knot of transistor
Structure, sensor structure.The conductive structure includes：Positioned at semiconductor substrate surface and device architecture surface conductive plunger, with
And the electrical interconnection line at the top of conductive plunger；The material of the conductive structure be metal, the metal include copper, tungsten, aluminium,
It is one or more in silver, titanium, tantalum, titanium nitride or tantalum nitride.The second dielectric layer is for protecting the device architecture and electricity
Interconnection line, and for making disjunct device architecture and electrical interconnection line be electrically isolated from each other, the material of the second dielectric layer is oxygen
SiClx, silicon nitride, silicon oxynitride, low-K dielectric material or ultralow K dielectric materials.
The aperture of second through-hole is 1 micron~100 microns；The depth of second through-hole is 30 microns~100 micro-
Rice.
The plug structure 205 includes：Positioned at the second through-hole side wall and the insulating layer of bottom surface 250；Positioned at insulating layer
The conductive plunger 251 of 250 surfaces and full second through-hole of filling.The insulating layer 250 is for being electrically isolated the conductive plunger
251 and semiconductor base；The conductive plunger 251 between the substrate 200 overlapped for being electrically connected.
The material of the conductive plunger 251 is one or more groups in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride
It closes.The material of the insulating layer 250 is one or more combinations in silica, silicon nitride, silicon oxynitride.
The width in the gap 206 is 100 angstroms~100000 angstroms；The depth in the gap 206 is greater than or equal to described the
The 10% of one device layer, 201 thickness.The gap 206 is used to provide thermal expansion overdose space for plug structure 205, avoids described
The first device layer of thermal expansion pair 201 of plug structure 205 causes to squeeze, and first device layer 201 is avoided to be stressed effect,
It ensure that the electrical connection stability of the interconnection layers in the first device layer 201；Also, described insert can be isolated in the gap 206
Plug structure 205 and first device layer, avoid the metallic atom in the conductive plunger 251 on 201 surface of the first device layer
Electromigration occurs, prevents short circuit between the interconnection layers in the conductive plunger 251 and the first device layer 201, and improve institute
State the controllability of the resistivity of conductive plunger 251.
In the present embodiment, 201 surface of the first device layer also has separation layer 207.The material of the separation layer 207 is
It is one or more in silica, silicon nitride or silicon oxynitride.The separation layer 207 is not filled by in the gap 206, described
Separation layer 207 is located at 206 top of the gap, and the gap 206 is made to close.
To sum up, in the present embodiment, due to having gap between the plug structure and the first device layer, the gap can
As the buffering between plug structure and device layer, avoid because of the coefficient of thermal expansion between the plug structure and the first device layer
Difference causes the first device layer of the plug structure pair to cause to squeeze, and to avoid first device layer from being stressed, ensures
The structure and performance of first device layer are stablized.Moreover, because having between the plug structure and first device layer
There is gap isolation, so as to avoid the material atom in the plug structure that electromigration occurs in first device layer surface
Phenomenon ensure that the performance of the plug structure and the first device layer is stablized.Therefore, it is formed by the reliable of semiconductor structure
Property improve, performance improvement.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate surface has the first device layer；
First through hole is formed in first device layer；
Sacrificial layer is formed in the sidewall surfaces of the first through hole；
After forming the sacrificial layer, the bottom that the first through hole exposes is etched, in the substrate and the first device layer
The second through-hole of interior formation；
Plug structure is formed in second through-hole；
The sacrificial layer is removed, gap is formed between the plug structure and the first device layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the forming step packet of the sacrificial layer
It includes：Expendable film is formed in first device layer surface and the side wall and bottom surface of the first through hole；Remove described
The expendable film of one via bottoms forms the sacrificial layer.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the sacrificial layer is also formed into described
First device layer surface.
4. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the sacrifice of removal first through hole bottom
The technique of film is anisotropic dry etch process.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the anisotropic dry etching
Technique is no mask etching technique.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the sacrificial layer is without fixed
It is one or more in shape carbon, amorphous silicon or polysilicon；The technique for removing the sacrificial layer is plasma dry ash chemical industry
Skill.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that the depth of the first through hole is more than
Or equal to the 10% of first device layer thickness.
8. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes opposite first
Surface and second surface, first device layer are located at the first surface of the substrate.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that further include：Forming the gap
Later, the second surface of the substrate is thinned, until the top surface for exposing the plug structure.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that further include：Forming the gap
Later, before the second surface of the substrate being thinned, separation layer, the isolation are formed in first device layer surface
Layer is suitable for being in contact with the pedestal of reduction process equipment.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the material of the separation layer is oxygen
It is one or more in SiClx, silicon nitride or silicon oxynitride；The formation process of the separation layer is chemical vapor deposition method.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the plug structure includes：It is located at
The insulating layer of second through-hole side wall and bottom surface；Conduction positioned at the surface of insulating layer and full second through-hole of filling is inserted
Plug.
13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the formation of the plug structure walks
Suddenly include：Insulating film is formed in the side wall and bottom surface of first device layer surface and the second through-hole；In the insulation
Film surface forms conductive film；The conductive film and insulating film are planarized until exposing first device layer surface, shape
At the insulating layer and conductive plunger.
14. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the material of the conductive plunger is
Copper；The material of the insulating layer is one or more in silica, silicon nitride, silicon oxynitride.
15. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes semiconductor-based
Bottom and the second device layer positioned at semiconductor substrate surface；First device layer is located at second device layer surface.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that second device layer includes device
Part structure, conductive structure and the second dielectric layer being electrically isolated between device architecture and conductive structure.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that first device layer includes electricity
Interconnection layer and the first medium layer being electrically isolated between the interconnection layers.
18. the forming method of semiconductor structure as described in claim 1, which is characterized in that the formation work of the first through hole
Skill is more dry etching technics；The formation process of second through-hole is more dry etching technics.
19. the forming method of semiconductor structure as claimed in claim 18, which is characterized in that the multistep etching technics packet
It includes：It is passivated etching, forms etching through hole in the first device layer or substrate, the etching through hole inner wall surface has passivation
Layer；Depassivation etching is carried out, the passivation layer of the etching through hole bottom surface is removed；Main etching is carried out, is carved in depassivation
After erosion, the etching through hole bottom is performed etching, the depth of the etching through hole is made to increase；The repetition passivation etching,
Depassivation etches and main etch step, until forming the first through hole or second through-hole.
20. a kind of being formed by semiconductor structure using such as any one of claim 1 to 19 method, which is characterized in that including：
Substrate, the substrate surface have the first device layer；
The second through-hole in the substrate and the first device layer；
Plug structure in second through-hole；
Gap between the plug structure and the first device layer.
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| CN114566461A (en) * | 2022-03-02 | 2022-05-31 | 成都海威华芯科技有限公司 | Semiconductor device deep back hole manufacturing method and device based on front and back side through holes |
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