CN103474387A - Method of forming air space between grooves - Google Patents
Method of forming air space between grooves Download PDFInfo
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- CN103474387A CN103474387A CN2012101872342A CN201210187234A CN103474387A CN 103474387 A CN103474387 A CN 103474387A CN 2012101872342 A CN2012101872342 A CN 2012101872342A CN 201210187234 A CN201210187234 A CN 201210187234A CN 103474387 A CN103474387 A CN 103474387A
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Abstract
The invention provides a method of forming an air space between grooves. A semiconductor substrate is provided in advance. A surface of the semiconductor substrate successively comprises a first etching stop layer and a patterning light resistance glue layer from bottom to top. An exposed area of the patterning light resistance glue layer defines a critical size of each groove. Ultra-low temperature oxide layers are deposited on the first etching stop layer and the surface of the patterning light resistance glue layer and anisotropic etching is performed on the ultra-low temperature oxide layers so as to form sidewall layers which are located on two sides of the patterning light resistance glue layer. Metal copper is deposited and chemical mechanical grinding is performed till that a height is the same with the height of the patterning light resistance glue layer so as to form the metal copper in the grooves. Hole cover layers are formed on the metal copper and the surface of the patterning light resistance glue layer. The patterning light resistance glue layer is removed through the hole cover layers so as to form the air space between grooves. By using the method of the invention, RC delay of a whole IC can be reduced.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly between a kind of groove, form the method for airspace.
Background technology
At present, back segment (back-end-of-line at semiconductor device, BEOL) in technique, can be according to the difference multiple layer metal interconnection layer of need to growing on Semiconductor substrate, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, and this just need to manufacture groove (trench) and connecting hole, then plated metal in above-mentioned groove and connecting hole to above-mentioned insulating barrier, the metal of deposition is metal interconnecting wires, generally selects copper as metal interconnected wire material.Insulating barrier can specifically arrange according to the needs of processing procedure.For example be included in the etch stop layer formed successively on Semiconductor substrate, for example the silicon carbide layer of nitrating; Low-k (Low-K) insulation material layer, for example contain black diamond (black diamond, the BD) material etc. of the similar oxide (Oxide) of silicon, oxygen, carbon, protium.
Form the method for groove in prior art, comprise the following steps:
Step 011, provide semi-conductive substrate, described semiconductor substrate surface comprises etch stop layer and interlayer dielectric layer from bottom to top successively, coating photoresistance glue (PR on interlayer dielectric layer, Photo Resist) layer, and the described photoresistance glue-line of patterning, the photoresistance glue-line of patterning appears the critical size (CD) of zone definitions groove;
Step 012, the photoresistance glue-line of patterning of take are mask, and the dry etching interlayer dielectric layer, stop etching at etch stop layer, form groove.In existing etching technics, the method for general using plasma etching forms groove.
Fill metallic copper after the photoresistance glue-line of step 013, removal patterning in groove.
Development along with integrated circuit, the number of plies of back segment metal interconnecting layer is more and more intensive, require interlayer dielectric layer to there is lower K value, although interlayer dielectric layer has adopted the low dielectric constant insulating material layer, but the dielectric constant of BD is 2.7～3, therefore the resistance capacitance (RC) that how further to reduce whole integrated circuit (IC) postpones, and improves the electric property of device, becomes current problem demanding prompt solution.
Summary of the invention
In view of this, the technical problem that the present invention solves is: the RC that reduces whole IC postpones.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention provides a kind of method that forms airspace between groove, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the photoresistance glue-line of the first etch stop layer and patterning from bottom to top successively, and the photoresistance glue-line of patterning appears the critical size of zone definitions groove;
In the photoresistance glue-line surface deposition ultralow temperature oxide layer of the first etch stop layer and patterning, and described ultralow temperature oxide layer is carried out to anisotropic etching, form the side wall layer that is positioned at patterning photoresistance glue-line both sides;
Plated metal copper also carries out cmp to flushing with the height of patterning photoresistance glue-line, forms the metallic copper in groove;
Surface at metallic copper and patterning photoresistance glue-line is formed with opercular layer;
See through and have opercular layer to remove patterning photoresistance glue-line, form the airspace between groove.
After the cmp metallic copper, before being formed with opercular layer, the method further comprises the coating amorphous carbon film, and returns quarter, makes the patterning photoresistance glue-line surface of damaging through going back to when the amorphous carbon film of carving is filled in by the cmp metallic copper.
The method that is formed with opercular layer comprises: molecule deposition sieve membrane, the well-regulated hole of described molecular screen membrane tool; Perhaps deposit the second etch stop layer, and the position that has patterning photoresistance glue-line on the second etch stop layer surface below it forms through hole.
The method of removing patterning photoresistance glue-line comprises the method for oxygen ashing or the method for oxygen-carrying ion body etching.
The formation temperature of described ultralow temperature oxide layer is lower than 100 degrees centigrade.
After forming the airspace between groove, the method further comprises the interlayer dielectric layer that forms lower floor.
The dielectric constant of described interlayer dielectric layer is 2～7.
Described interlayer dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2the combination in any of one or several in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium SiNC layer.
As seen from the above technical solutions, adopt photoresistance glue as sacrifice layer, form airspace after final the removal between groove, there is airspace between groove, the dielectric constant of air is 1, and the dielectric constant of BD is 2.7～3, from relatively can finding out of dielectric constant, the formation of airspace makes the overall dielectric constant of interlayer dielectric layer descend, thereby has reached the purpose of the RC delay that reduces whole IC.
The accompanying drawing explanation
Fig. 1 forms the schematic flow sheet of the method for airspace between embodiment of the present invention groove.
Fig. 2 a to Fig. 2 e forms the concrete generalized section of the method for airspace between embodiment of the present invention groove.
Fig. 2 f is that the embodiment of the present invention is having the cross-sectional view of lower floor's interlayer dielectric layer when layer metal interconnecting layer surface deposition.
The structural representation of photoresistance glue damage appears in Fig. 3 while being the actual abrasive metal copper of the present invention.
Fig. 4 is that the present invention overcomes the structural representation that Fig. 3 defect is filled photoresistance glue damage position.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention utilizes schematic diagram have been described in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram that means structure can be disobeyed local amplification of general ratio work, should not using this as limitation of the invention, in addition, in actual making, should comprise the three-dimensional space of length, width and the degree of depth.
Core concept of the present invention is: adopt photoresistance glue as sacrifice layer, after final the removal, form airspace between groove, airspace has substituted original interlayer dielectric layer, thereby has reached the purpose of the RC delay that reduces whole IC.And, the present invention has adopted and has been different from the method that prior art etching interlayer dielectric layer forms groove, but exposure imaging photoresistance glue-line, the CD of definition groove, there is not the process of etching interlayer dielectric layer in the groove formed so, so groove has higher characteristic size uniformity.
Form the method for airspace between embodiment of the present invention groove, its schematic flow sheet as shown in Figure 1, comprises the following steps, and below in conjunction with Fig. 2 a to Fig. 2 e, is elaborated.
The ultralow temperature oxide layer is low temperature oxide layer (Low Temperature Oxide, LTO) a kind of, why select the side wall layer of ultralow temperature oxide layer as photoresistance glue, be because the formation temperature of ultralow temperature oxide layer lower than 100 degrees centigrade, fusion temperature lower than photoresistance glue, be unlikely to, in the process that forms side wall layer, to change the pattern of photoresistance glue-line.And the Thickness Ratio of side wall layer is thinner, with the CD of groove, compare, substantially can ignore.This step is key of the present invention, and PR limits by side wall layer, is the PR core technology that a kind of PR of take is core, and follow-up PR can be removed, in this formation airspace, position.
Usually, the cmp metallic copper is to flushing with the height of patterning photoresistance glue-line, to need in theory the ideal state reached, in fact, when grinding, the relative copper of photoresistance glue is softer, so can be when grinding approaches photoresistance glue, damage photoresistance glue, make photoresistance glue surface depression as shown in Figure 3 occur, the photoresistance glue-line 102 ' damaged, will cause so follow-up while depositing interlayer dielectric layer thereon, the height injustice of diverse location interlayer dielectric layer, therefore for overcoming this defect, after the cmp metallic copper, before being formed with opercular layer, the coating amorphous carbon film, and return quarter, make the patterning photoresistance glue-line surface of damaging through going back to when the amorphous carbon film 400 of carving is filled in by the cmp metallic copper, as shown in Figure 4.Amorphous carbon film is illustrated embodiment of the present invention, the material on the patterning photoresistance glue-line surface that other damage in the time of can being filled in by the cmp metallic copper, may be used to the present invention, as long as also can easily remove this material when removing photoresistance glue.
Concrete, the method that is formed with opercular layer can be: molecule deposition sieve membrane, the well-regulated hole of described molecular screen membrane tool.That is to say the insulation material layer that this has opercular layer to be gas permeability, guarantee that follow-up photoresistance glue can volatilize away.Fig. 2 d has opercular layer 105 to take molecular screen membrane to describe as example.
The method that is formed with opercular layer has multiple, can also be: deposit the second etch stop layer, and the position that has patterning photoresistance glue-line on the second etch stop layer surface below it forms through hole.In like manner, follow-up photoresistance glue can volatilize away through through hole.
The method of removing patterning photoresistance glue-line comprises the method for oxygen ashing or the method for oxygen-carrying ion body etching.
Here, if photoresistance glue has damage, its top is filled with amorphous carbon film, and amorphous carbon film also can be removed by the method for above-mentioned oxygen ashing or the method for oxygen-carrying ion body etching.
So far, the embodiment of the present invention has realized forming between groove the method for airspace.
Further, the embodiment of the present invention can also comprise step 16, refer to Fig. 2 f, the interlayer dielectric layer 107 of deposition lower floor.Those skilled in the art can know, can make groove and connecting hole on the interlayer dielectric layer of lower floor, connecting hole can be electrically connected with metallic copper 104, and being connected part can develop and method for etching plasma removal dielectric layer realizes that interlayer is interconnected by photoresistance at needs with this layer.Do not repeat them here.The dielectric constant of interlayer dielectric layer 107 is 2～7, can be silicon oxide carbide SiOC layer, silicon dioxide SiO
2the combination in any of one or several in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium SiNC layer.
At present, characteristic size uniformity (Critical Dimension Uniform, CDU) is to need the important indicator of investigating in process for fabrication of semiconductor device.Usually, in semiconductor fabrication process, etching side-play amount (etch bias) equal the to develop characteristic size of rear detection (After Development Inspection, ADI) deducts after etching the characteristic size that detects (After Etch Inspection, AEI).There are several chip units (Die) in wafer, have several single lines (Iso) and close line (Dense) in each chip unit.The etching side-play amount of Iso and Dense is more approaching, illustrates that its characteristic size uniformity is higher, also shows as Iso and Dense groove dimensions mean value is more approaching.When prior art forms groove, need long-time etching interlayer dielectric layer, and the etch rate of Iso and Dense is different, causes the AEI difference of Iso and Dense just larger, finally cause the CDU of groove poor.And method of the present invention does not relate to the etching interlayer dielectric layer, in step 11, the photoresistance glue-line 102 that exposure imaging forms patterning has just defined the characteristic size of groove, and the groove dimensions obtained at Iso and Dense place does not have difference substantially, so the CDU of groove is also just higher.Be the etching process of mask to dielectric layer owing to not comprising photoresistance in technique of the present invention, make process costs greatly reduce.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (8)
1. form the method for airspace between a groove, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the photoresistance glue-line of the first etch stop layer and patterning from bottom to top successively, and the photoresistance glue-line of patterning appears the critical size of zone definitions groove;
In the photoresistance glue-line surface deposition ultralow temperature oxide layer of the first etch stop layer and patterning, and described ultralow temperature oxide layer is carried out to anisotropic etching, form the side wall layer that is positioned at patterning photoresistance glue-line both sides;
Plated metal copper also carries out cmp to flushing with the height of patterning photoresistance glue-line, forms the metallic copper in groove;
Surface at metallic copper and patterning photoresistance glue-line is formed with opercular layer;
See through and have opercular layer to remove patterning photoresistance glue-line, form the airspace between groove.
2. the method for claim 1, it is characterized in that, after the cmp metallic copper, before being formed with opercular layer, the method further comprises the coating amorphous carbon film, and return quarter, make the patterning photoresistance glue-line surface of damaging through going back to when the amorphous carbon film of carving is filled in by the cmp metallic copper.
3. method as claimed in claim 2, is characterized in that, the method that is formed with opercular layer comprises: molecule deposition sieve membrane, the well-regulated hole of described molecular screen membrane tool; Perhaps deposit the second etch stop layer, and the position that has patterning photoresistance glue-line on the second etch stop layer surface below it forms through hole.
4. method as claimed in claim 3, is characterized in that, the method for removing patterning photoresistance glue-line comprises the method for oxygen ashing or the method for oxygen-carrying ion body etching.
5. the method for claim 1, is characterized in that, the formation temperature of described ultralow temperature oxide layer is lower than 100 degrees centigrade.
6. the method for claim 1, is characterized in that, after forming the airspace between groove, the method further comprises the interlayer dielectric layer that forms lower floor.
7. method as claimed in claim 6, is characterized in that, the dielectric constant of described interlayer dielectric layer is 2～7.
8. method as claimed in claim 7, is characterized in that, described interlayer dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO
2the combination in any of one or several in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium SiNC layer.
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| CN201210187234.2A CN103474387B (en) | 2012-06-08 | 2012-06-08 | The method of airspace is formed between groove |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826279A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN116114949A (en) * | 2023-02-27 | 2023-05-16 | 联纲光电科技股份有限公司 | VR glove preparation method and breathable intelligent VR glove |
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| US20030224591A1 (en) * | 2002-05-31 | 2003-12-04 | Applied Materials, Inc. | Airgap for semiconductor devices |
| US20040127001A1 (en) * | 2002-12-27 | 2004-07-01 | International Business Machines Corporation | Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence |
| CN101022088A (en) * | 2007-03-02 | 2007-08-22 | 上海集成电路研发中心有限公司 | Method for producing copper-gas dielectric suspension Damscus structure |
| US20110104898A1 (en) * | 2009-11-05 | 2011-05-05 | Hynix Semiconductor Inc. | Method of Forming Semiconductor Device |
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2012
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030224591A1 (en) * | 2002-05-31 | 2003-12-04 | Applied Materials, Inc. | Airgap for semiconductor devices |
| US20040127001A1 (en) * | 2002-12-27 | 2004-07-01 | International Business Machines Corporation | Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence |
| CN101022088A (en) * | 2007-03-02 | 2007-08-22 | 上海集成电路研发中心有限公司 | Method for producing copper-gas dielectric suspension Damscus structure |
| US20110104898A1 (en) * | 2009-11-05 | 2011-05-05 | Hynix Semiconductor Inc. | Method of Forming Semiconductor Device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826279A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN105826279B (en) * | 2015-01-06 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN116114949A (en) * | 2023-02-27 | 2023-05-16 | 联纲光电科技股份有限公司 | VR glove preparation method and breathable intelligent VR glove |
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