CN103474388A - Method of forming air space between grooves - Google Patents

Method of forming air space between grooves Download PDF

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Publication number
CN103474388A
CN103474388A CN2012101872357A CN201210187235A CN103474388A CN 103474388 A CN103474388 A CN 103474388A CN 2012101872357 A CN2012101872357 A CN 2012101872357A CN 201210187235 A CN201210187235 A CN 201210187235A CN 103474388 A CN103474388 A CN 103474388A
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layer
patterning
groove
metal copper
line
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CN103474388B (en
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张城龙
胡敏达
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention provides a method of forming an air space between grooves. The method is characterized in that a semiconductor substrate is provided in advance and a surface of the semiconductor substrate successively comprises a first etching stop layer and a patterning light resistance glue layer from bottom to top; an exposed area of the patterning light resistance glue layer defines a critical size of each groove; ultra-low temperature oxide layers are deposited on the first etching stop layer and the surface of the patterning light resistance glue layer and anisotropic etching is performed on the ultra-low temperature oxide layers so as to form sidewall layers which are located on two sides of the patterning light resistance glue layer; the patterning light resistance glue layer is removed; metal copper is deposited and chemical mechanical grinding or a plasma etching method are performed so that a copper surface height is the same level with a height of the sidewall layers so as to form a metal copper layer with sidewall layer intervals; a second etching stop layer is deposited on a surface of the metal copper layer with sidewall layer intervals; a through hole is formed at a position possessing the patterning light resistance glue layer during initialization of a lower portion of the surface of the second etching stop layer; the metal copper layer below the through hole is removed and the air space between the grooves is formed. RC delay of a whole IC is reduced.

Description

Form the method for airspace between groove
Technical field
The present invention relates to semiconductor device processing technology, particularly between a kind of groove, form the method for airspace.
Background technology
At present, back segment (back-end-of-line at semiconductor device, BEOL) in technique, can be according to the difference multiple layer metal interconnection layer of need to growing on Semiconductor substrate, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, and this just need to manufacture groove (trench) and connecting hole, then plated metal in above-mentioned groove and connecting hole to above-mentioned insulating barrier, the metal of deposition is metal interconnecting wires, generally selects copper as metal interconnected wire material.Insulating barrier can specifically arrange according to the needs of processing procedure.For example be included in the etch stop layer formed successively on Semiconductor substrate, for example the silicon carbide layer of nitrating; Low-k (Low-K) insulation material layer, for example contain black diamond (black diamond, the BD) material etc. of the similar oxide (Oxide) of silicon, oxygen, carbon, protium.
Form the method for groove in prior art, comprise the following steps:
Step 011, provide semi-conductive substrate, described semiconductor substrate surface comprises etch stop layer and interlayer dielectric layer from bottom to top successively, coating photoresistance glue (PR on interlayer dielectric layer, Photo Resist) layer, and the described photoresistance glue-line of patterning, the photoresistance glue-line of patterning appears the critical size (CD) of zone definitions groove;
Step 012, the photoresistance glue-line of patterning of take are mask, and the dry etching interlayer dielectric layer, stop etching at etch stop layer, form groove.In existing etching technics, the method for general using plasma etching forms groove.
Fill metallic copper after the photoresistance glue-line of step 013, removal patterning in groove.
Development along with integrated circuit, the number of plies of back segment metal interconnecting layer is more and more intensive, require interlayer dielectric layer to there is lower K value, although interlayer dielectric layer has adopted the low dielectric constant insulating material layer, but the dielectric constant of BD is 2.7～3, therefore the resistance capacitance (RC) that how further to reduce whole integrated circuit (IC) postpones, and improves the electric property of device, becomes current problem demanding prompt solution.
Summary of the invention
In view of this, the technical problem that the present invention solves is: the RC that reduces whole IC postpones.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention provides a kind of method that forms airspace between groove, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the photoresistance glue-line of the first etch stop layer and patterning from bottom to top successively, and the photoresistance glue-line of patterning appears the critical size of zone definitions groove;
In the photoresistance glue-line surface deposition ultralow temperature oxide layer of the first etch stop layer and patterning, and described ultralow temperature oxide layer is carried out to anisotropic etching, form the side wall layer that is positioned at patterning photoresistance glue-line both sides;
Remove patterning photoresistance glue-line;
Plated metal copper also carries out cmp or plasma etching method makes the copper apparent height flush with the height of side wall layer, forms the metal copper layer of sidewall layer spaces;
At metal copper layer surface deposition second etch stop layer of sidewall layer spaces, and the position that has patterning photoresistance glue-line when initial below it on the second etch stop layer surface forms through hole;
Remove the metal copper layer of through hole below, form the airspace between groove.
The metal copper layer of removing the through hole below adopts the method for wet etching to carry out in the solution that comprises acid solution and hydrogen peroxide.
Described acid solution is one or more the mixed liquor in hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid or other acid solution.
The method of removing patterning photoresistance glue-line comprises method or the method for oxygen-carrying ion body etching or the method for wet etching of oxygen ashing.
The formation temperature of described ultralow temperature oxide layer is lower than 100 degrees centigrade.
After forming the airspace between groove, the method further comprises the interlayer dielectric layer that forms lower floor.
The dielectric constant of described interlayer dielectric layer is 2～7.
Described interlayer dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO 2the combination in any of one or several in layer, hydroxide silicon layer, silicon nitride layer, carbonitride of silicium SiNC layer.
As seen from the above technical solutions, form metal copper layer between side wall layer, this metal copper layer comprises the metal copper layer in groove, also comprises that follow-up needs removal forms the metal copper layer of airspace.The metal copper layer revealed by through hole is immersed in the solution that comprises acid solution and hydrogen peroxide, carry out wet etching, this part copper dissolution is fallen, form airspace between groove, airspace has substituted the interlayer dielectric layer of prior art, thereby has reached the purpose of the RC delay that reduces whole IC.And, the present invention has adopted and has been different from the method that prior art etching interlayer dielectric layer forms groove, but exposure imaging photoresistance glue-line, the CD of definition groove, there is not the process of etching interlayer dielectric layer in the groove formed so, so groove has higher characteristic size uniformity.
The accompanying drawing explanation
Fig. 1 forms the schematic flow sheet of the method for airspace between embodiment of the present invention groove.
Fig. 2 a to Fig. 2 f forms the concrete generalized section of the method for airspace between embodiment of the present invention groove.
Fig. 2 g is that the embodiment of the present invention is having the cross-sectional view of lower floor's interlayer dielectric layer when layer metal interconnecting layer surface deposition.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention utilizes schematic diagram have been described in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram that means structure can be disobeyed local amplification of general ratio work, should not using this as limitation of the invention, in addition, in actual making, should comprise the three-dimensional space of length, width and the degree of depth.
Core concept of the present invention is: form metal copper layer between side wall layer, this metal copper layer comprises the metal copper layer in groove, also comprises that follow-up needs removal forms the metal copper layer of airspace.The metal copper layer revealed by through hole is immersed in the solution that comprises acid solution and hydrogen peroxide, carry out wet etching, this part copper dissolution is fallen, form airspace between groove, airspace has substituted the interlayer dielectric layer of prior art, thereby has reached the purpose of the RC delay that reduces whole IC.And, the present invention has adopted and has been different from the method that prior art etching interlayer dielectric layer forms groove, but exposure imaging photoresistance glue-line, the CD of definition groove, there is not the process of etching interlayer dielectric layer in the groove formed so, so groove has higher characteristic size uniformity.
Form the method for airspace between embodiment of the present invention groove, its schematic flow sheet as shown in Figure 1, comprises the following steps, and below in conjunction with Fig. 2 a to Fig. 2 f, is elaborated.
Step 11, refer to Fig. 2 a, semi-conductive substrate 100 is provided in advance, described Semiconductor substrate 100 surfaces comprise the photoresistance glue-line 102 of the first etch stop layer 101 and patterning, the critical size of the zone definitions groove that photoresistance glue-line 102 appears of patterning from bottom to top successively;
Step 12, refer to Fig. 2 b, in the photoresistance glue-line 102 surface deposition ultralow temperature oxide layers of the first etch stop layer 101 and patterning, and described ultralow temperature oxide layer is carried out to anisotropic etching, form the side wall layer 103 that is positioned at patterning photoresistance glue-line both sides;
The ultralow temperature oxide layer is low temperature oxide layer (Low Temperature Oxide, LTO) a kind of, why select the side wall layer of ultralow temperature oxide layer as photoresistance glue, be because the formation temperature of ultralow temperature oxide layer lower than 100 degrees centigrade, fusion temperature lower than photoresistance glue, be unlikely to, in the process that forms side wall layer, to change the pattern of photoresistance glue-line.
Step 13, refer to Fig. 2 c, remove patterning photoresistance glue-line 102;
The method of removing patterning photoresistance glue-line comprises method or the method for oxygen-carrying ion body etching or the method for wet etching of oxygen ashing.
Step 14, refer to Fig. 2 d, plated metal copper also carries out cmp or plasma etching method makes the copper apparent height flush with the height of side wall layer, forms the metal copper layer 104 of sidewall layer spaces;
Step 15, refer to Fig. 2 e, at metal copper layer 104 surface deposition second etch stop layers 105 of sidewall layer spaces, and the position that has patterning photoresistance glue-line when initial below it on the second etch stop layer surface forms through hole 106;
Wherein, the quantity that has the position formation through hole of patterning photoresistance glue-line when each is initial is not limit, and a through hole only is shown in Fig. 2 e.The through hole width does not limit yet, and the interlayer dielectric layer that is unlikely to subsequent deposition collapses in airspace and gets final product.The second etch stop layer 105 is generally carborundum, silicon nitride, the combination of one or several in carbon nitrogen silicon layer.The process that forms through hole is generally at the second etch stop layer 105 surface-coated photoresistance glue, size and position by patterning photoresistance glue definition through hole, then take this patterning photoresistance glue is mask, etching the second etch stop layer 105, thus form through hole on the second etch stop layer 105.
Step 16, refer to Fig. 2 f, remove the metal copper layer of through hole 106 belows, form the airspace 107 between groove.
This step is key of the present invention, because through hole can reveal metal copper layer, the metal copper layer of other positions is covered by the second etch stop layer, immerse in the solution that comprises acid solution and hydrogen peroxide so will there is the device of this structure, the metal copper layer revealed by through hole is carried out to wet etching.Described acid solution can be one or more the mixed liquor in hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid or other acid solution, or other can be reacted with metallic copper in conjunction with hydrogen peroxide, the material of dissolved copper.
Wherein, take acid solution as hydrochloric acid is example, the chemical equation reacted is:
H 2O 2+2(HCl)+Cu=CuCl 2+2(H 2O)。
Like this, the metallic copper in groove still retains, and forms airspace between groove.
So far, the embodiment of the present invention has realized forming between groove the method for airspace.
Further, the embodiment of the present invention can also comprise step 17, refer to Fig. 2 g, the interlayer dielectric layer 108 of deposition lower floor.Those skilled in the art can know, on the interlayer dielectric layer of lower floor, can make groove and connecting hole, and connecting hole can be electrically connected with metal copper layer 104, does not repeat them here.The dielectric constant of interlayer dielectric layer 108 is 2～7, can be silicon oxide carbide (SiOC) layer, silicon dioxide (SiO 2) one or more combination in any in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium (SiNC) layer.
At present, characteristic size uniformity (Critical Dimension Uniform, CDU) is to need the important indicator of investigating in process for fabrication of semiconductor device.Usually, in semiconductor fabrication process, etching side-play amount (etch bias) equal the to develop characteristic size of rear detection (After Development Inspection, ADI) deducts after etching the characteristic size that detects (After Etch Inspection, AEI).There are several chip units (Die) in wafer, have several single lines (Iso) and close line (Dense) in each chip unit.From single line to Mi Xianchu, the spacing between groove and groove reduces gradually.The characteristic size of ADI refers to the centre position size that measures PR after exposure imaging, and the characteristic size of AEI refers to the bottom position size that measures the groove after etching.The etching side-play amount of Iso and Dense is more approaching, illustrates that its characteristic size uniformity is higher, also shows as Iso and Dense groove dimensions mean value is more approaching.When prior art forms groove, need long-time etching interlayer dielectric layer, and the etch rate of Iso and Dense is different, cause the AEI difference of Iso and Dense just larger, so etch bias is just larger, finally causes the CDU of groove poor.And method of the present invention does not relate to the etching interlayer dielectric layer, in step 11, the photoresistance glue-line 102 that exposure imaging forms patterning is by the width of groove and highly all define out, and the groove dimensions obtained at Iso and Dense place does not have difference substantially, so the CDU of groove is also just higher.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (8)

1. form the method for airspace between a groove, be applied in the last part technology of semiconductor device, the method comprises:
Semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the photoresistance glue-line of the first etch stop layer and patterning from bottom to top successively, and the photoresistance glue-line of patterning appears the critical size of zone definitions groove;
In the photoresistance glue-line surface deposition ultralow temperature oxide layer of the first etch stop layer and patterning, and described ultralow temperature oxide layer is carried out to anisotropic etching, form the side wall layer that is positioned at patterning photoresistance glue-line both sides;
Remove patterning photoresistance glue-line;
Plated metal copper also carries out cmp or plasma etching method makes the copper apparent height flush with the height of side wall layer, forms the metal copper layer of sidewall layer spaces;
At metal copper layer surface deposition second etch stop layer of sidewall layer spaces, and the position that has patterning photoresistance glue-line when initial below it on the second etch stop layer surface forms through hole;
Remove the metal copper layer of through hole below, form the airspace between groove.
2. the method for claim 1, is characterized in that, the metal copper layer of removing the through hole below adopts the method for wet etching to carry out in the solution that comprises acid solution and hydrogen peroxide.
3. method as claimed in claim 2, is characterized in that, described acid solution is one or more the mixed liquor in hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid or other acid solution.
4. method as claimed in claim 3, is characterized in that, the method for removing patterning photoresistance glue-line comprises method or the method for oxygen-carrying ion body etching or the method for wet etching of oxygen ashing.
5. the method for claim 1, is characterized in that, the formation temperature of described ultralow temperature oxide layer is lower than 100 degrees centigrade.
6. the method for claim 1, is characterized in that, after forming the airspace between groove, the method further comprises the interlayer dielectric layer that forms lower floor.
7. method as claimed in claim 6, is characterized in that, the dielectric constant of described interlayer dielectric layer is 2～7.
8. method as claimed in claim 7, is characterized in that, described interlayer dielectric layer is silicon oxide carbide SiOC layer, silicon dioxide SiO 2the combination in any of one or several in layer, hydroxide silicon layer, silicon nitride layer or carbonitride of silicium SiNC layer.
CN201210187235.7A 2012-06-08 2012-06-08 The method of airspace is formed between groove Active CN103474388B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795359A (en) * 2015-04-13 2015-07-22 上海华力微电子有限公司 Method of forming air gaps in dielectric layers among metal interconnections
CN106935544A (en) * 2015-12-30 2017-07-07 台湾积体电路制造股份有限公司 The formed method of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
CN101022088A (en) * 2007-03-02 2007-08-22 上海集成电路研发中心有限公司 Method for producing copper-gas dielectric suspension Damscus structure
US20070249170A1 (en) * 2006-04-25 2007-10-25 David Kewley Process for improving critical dimension uniformity of integrated circuit arrays

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413852B1 (en) * 2000-08-31 2002-07-02 International Business Machines Corporation Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
US20070249170A1 (en) * 2006-04-25 2007-10-25 David Kewley Process for improving critical dimension uniformity of integrated circuit arrays
CN101022088A (en) * 2007-03-02 2007-08-22 上海集成电路研发中心有限公司 Method for producing copper-gas dielectric suspension Damscus structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795359A (en) * 2015-04-13 2015-07-22 上海华力微电子有限公司 Method of forming air gaps in dielectric layers among metal interconnections
CN106935544A (en) * 2015-12-30 2017-07-07 台湾积体电路制造股份有限公司 The formed method of semiconductor device
CN106935544B (en) * 2015-12-30 2019-12-03 台湾积体电路制造股份有限公司 The formed method of semiconductor device

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