CN102339790A - Manufacture method of semiconductor device - Google Patents
Manufacture method of semiconductor device Download PDFInfo
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- CN102339790A CN102339790A CN2011103353459A CN201110335345A CN102339790A CN 102339790 A CN102339790 A CN 102339790A CN 2011103353459 A CN2011103353459 A CN 2011103353459A CN 201110335345 A CN201110335345 A CN 201110335345A CN 102339790 A CN102339790 A CN 102339790A
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Abstract
The invention discloses a manufacture method of a semiconductor device. The method comprises the following steps: forming a medium layer on a semiconductor substrate; etching the medium layer to form a redundant metal groove and a metal conductor groove, wherein the depth of the redundant metal groove is less than that of the metal conductor groove; depositing a metal layer in the redundant metal groove, in the metal conductor groove and on the medium layer; and performing chemical mechanical grinding process until partial or whole metal layer in the redundant metal groove is removed to form a metal conductor in the metal conductor groove. On the premise that a uniform grinding effect is achieved, the coupling capacitance in the metal layers and among the metal layers introduced by redundant metal filling is reduced, even completely eliminated.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of manufacturing method of semiconductor device.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain through etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes the dual damascene process of through hole (also claiming contact hole) and plain conductor simultaneously.Specifically; Single damascene structure (also claiming single inlay structure) only is to change the production method of single-layer metal lead into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled); Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together.The common method of making dual-damascene structure generally has following several kinds: all-pass hole precedence method (Full VIA First), half via-first method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; In dielectric layer 110, form metallic channel through photoetching and etching technics then; Depositing metal layers subsequently, said metal level are filled in the metallic channel and on said dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technology and remove the metal on the said dielectric layer 110, thereby in said metallic channel, processed plain conductor 140.
As stated, in Damascus technics, need utilize chemical mechanical milling tech, be embedded in the plain conductor 140 in the dielectric layer 110 with final formation.Yet,, therefore can cause the depression of not expecting (dishing) and corrode (erosion) phenomenon the selectivity of grinding because the rate that removes of metal and dielectric layer material is generally inequality.Depression occurs in metal often and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is thin excessively.Depression and erosion are subject to the structure of figure and the density influence of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, the method for solution is to fill the pattern density homogenizing that redundant metal pattern makes domain at the white space of domain, thereby also forms redundant metal (dummy metal) 150 when in dielectric layer 110, forming plain conductor 140, and is as shown in Figure 2.But,, but introduced in the extra metal level inevitably and the coupling capacitance of metal interlevel though redundant metal has improved the uniformity of pattern density.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor device, to reduce or to have eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
For solving the problems of the technologies described above, the present invention provides a kind of manufacture method of semiconductor device, comprising:
On Semiconductor substrate, form dielectric layer;
The said dielectric layer of etching is to form redundant metallic channel and metallic channel, and the degree of depth of said redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech, part or all of metal level in removing said redundant metallic channel is to form plain conductor in said metallic channel.
Optional, in the manufacture method of described semiconductor device, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
The said dielectric layer of etching forms redundant metallic channel; And
The said dielectric layer of etching forms metallic channel.
Optional, in the manufacture method of described semiconductor device, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
The said dielectric layer of etching forms redundant metallic channel and through hole;
The said dielectric layer of etching forms metallic channel with the position at said through hole.
Optional, in the manufacture method of described semiconductor device, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
On said dielectric layer, form hard mask layer;
Said hard mask layer of etching and dielectric layer are to form hard mask layer groove and redundant metallic channel;
The said dielectric layer of etching forms through hole with the position at said hard mask layer groove;
The said dielectric layer of etching forms metallic channel with the position at said hard mask layer groove.
The present invention is after metallization medium layer; The said dielectric layer of etching is to form redundant metallic channel and metallic channel; Continue follow-up layer metal deposition and chemical mechanical milling tech again, and utilize chemical mechanical milling tech to remove all or part of metal level in the said redundant metallic channel, and in said metallic channel, form plain conductor; The present invention is reaching under the prerequisite of uniform grinding effect, reduces or has eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 is the schematic flow sheet of the manufacture method of semiconductor device of the present invention;
Fig. 4 A～4E is the cross-sectional view of the corresponding device of each step in the manufacture method of semiconductor device of the embodiment of the invention one;
Fig. 5 A～5E is the cross-sectional view of the corresponding device of each step in the manufacture method of semiconductor device of the embodiment of the invention two;
Fig. 6 A～6G is the cross-sectional view of the corresponding device of each step in the manufacture method of semiconductor device of the embodiment of the invention three.
Embodiment
Mention that in background technology though redundant metal has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows that the relative area that reduces metal can reduce electric capacity with increase intermetallic distance.That is to say that the volume that reduces redundant metal can reduce owing to adding the extra intermetallic coupling capacitance that redundant metal is introduced.For this reason; The present invention is after metallization medium layer, and the said dielectric layer of etching continues follow-up layer metal deposition and chemical mechanical milling tech again to form redundant metallic channel and metallic channel; All or part of metal level in removing said redundant metallic channel; And in said metallic channel, form plain conductor, and reaching under the prerequisite of uniform grinding effect, reduce or eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
Please refer to Fig. 3, it is the schematic flow sheet of the manufacture method of semiconductor device of the present invention.As shown in Figure 3, the manufacture method of said semiconductor device comprises the steps:
S310: on Semiconductor substrate, form dielectric layer;
S320: the said dielectric layer of etching is to form redundant metallic channel and metallic channel, and the degree of depth of said redundant metallic channel is less than the degree of depth of said metallic channel;
S330: depositing metal layers in said redundant metallic channel and metallic channel and on the dielectric layer; And
S340: carry out chemical mechanical milling tech, part or all of metal level in removing said redundant metallic channel is to form plain conductor in said metallic channel.
The manufacture method of the semiconductor device that respectively the present invention is proposed below in conjunction with generalized section is done further to specify.
Embodiment one
Shown in Fig. 4 A, at first, on Semiconductor substrate 400, form dielectric layer 410.Be formed with the metal line (not shown) in the said Semiconductor substrate 400.Because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 400, forms metal line, but those skilled in the art are still this and know.Wherein, dielectric layer 410 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of conduction fast.Preferable; It is black diamond (black diamond that said dielectric layer 410 adopts the trade mark of Material Used (Applied Materials) company; BD) silicon oxide carbide; Perhaps adopt the Coral material of Novellus company, perhaps adopt again and utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.The thickness of said dielectric layer 410 equals the thickness of plain conductor and the thickness of dielectric layers sum that the cmp step grinds away
In other embodiments of the invention; Before forming dielectric layer 410 on the said Semiconductor substrate 400; Also can form etching stop layer (not shown) earlier; Said etching stop layer can be used for preventing metal diffusing in the metal line in dielectric layer 410, and said in addition etching stop layer can prevent that also the metal line in the Semiconductor substrate 400 is etched in follow-up etching process of carrying out.The material of said etching stop layer for example is a silicon nitride, and the dielectric layer of itself and follow-up formation has good adhesive force property.
Shown in Fig. 4 B; Then; Utilize photoetching process on said dielectric layer 410, to form first mask layer with redundant metallic channel pattern, and be mask with said first mask layer, the said dielectric layer 410 of etching is to form redundant metallic channel 411; And then remove said first mask layer, the mode of said first mask layer dry method capable of using or wet method is removed.
Shown in Fig. 4 C; Thereafter; Utilize photoetching process on said dielectric layer 410, to form second mask layer with metallic channel pattern, and be mask with said second mask layer, the said dielectric layer 410 of etching forms metallic channels 412; The degree of depth of said redundant metallic channel 411 is removed said second mask layer then less than the degree of depth of said metallic channel 412.In the present embodiment, the degree of depth of said redundant metallic channel 411 (highly) be about metallic channel 412 the degree of depth 25%～80%.Certainly, the height of said redundant metallic channel 411 can change according to concrete technology accordingly, and the present invention also will not limit this.
Shown in Fig. 4 D, subsequently, depositing metal layers 420 in said redundant metallic channel 411 and metallic channel 412, because the characteristic of depositing operation also can deposit metal on this process medium layer 410, the material of wherein said metal level 420 is a copper.
Shown in Fig. 4 E, last, carry out chemical mechanical milling tech, part or all of metal level in removing said redundant metallic channel 411 is to form plain conductor 422 in said metallic channel 412.Owing in redundant metallic channel 411, formed redundant metal in the abovementioned steps; Therefore this grinding steps still can reach uniform grinding effect; Therefore all or part of metal of having removed in the redundant metallic channel 411 of this step simultaneously reduces even has eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.Preferable, shown in Fig. 4 E, the metal level of said redundant metallic channel 411 is all ground away, thereby has eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
Need to prove; Above-mentioned is to be that example has been introduced the present invention in detail to form earlier redundant metallic channel 411 and then to form metallic channel 412, yet will be appreciated that, in other specific embodiment; Also can form metallic channel 412 earlier, and then form redundant metallic channel 411.
Embodiment two
Shown in Fig. 5 A, at first, on Semiconductor substrate 500, form dielectric layer 510, the thickness of said dielectric layer 510 equals the thickness of plain conductor and the thickness of dielectric layers sum that the cmp step grinds away.
Shown in Fig. 5 B; Then; Utilize photoetching process on dielectric layer 510, to form first mask layer with redundant metallic channel pattern and through-hole pattern; And be mask with said first mask layer, the said dielectric layer 510 of etching to be forming redundant metallic channel 511 and through hole 513, and then removes said first mask layer.In the present embodiment, redundant metallic channel 511 utilizes same photoetching and etch step to form with through hole 513, and the height of said redundant metallic channel 511 is identical with the height of through hole 513.Yet will be appreciated that said redundant metallic channel and through hole be photoetching and etch step formation at twice also, thereby form different redundant metallic channel and the through holes of the degree of depth.
Shown in Fig. 5 C, subsequently, on said dielectric layer 510, form second mask layer, and be mask with said second mask layer with metallic channel pattern, etching dielectric layer 510 forms metallic channel 512 with the position at said through hole 513.
Shown in Fig. 5 D, subsequently, depositing metal layers 520 in said redundant metallic channel 511, metallic channel 512 and through hole 513 is because the characteristic of depositing operation also can deposit metal on the dielectric layer 510.
Shown in Fig. 5 E; At last; Carry out chemical mechanical milling tech, all or part of metal level in removing said redundant metallic channel 512 is to form plain conductor 522 in said metallic channel 511 and through hole 513; Owing in redundant metallic channel 511, formed redundant metal in the abovementioned steps; Therefore still can reach uniform grinding effect, all or part of again metal of having removed in the redundant metallic channel 511 in this step simultaneously can reduce or eliminates in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
Embodiment three
Shown in Fig. 6 A, at first, on Semiconductor substrate 600, form dielectric layer 610.
Shown in Fig. 6 B, then, on said dielectric layer 610, form hard mask layer 630, preferably, have preferable etching selection ratio at hard mask layer described in the subsequent etching technology 630 and dielectric layer 610.
Shown in Fig. 6 C, subsequently, etching hard mask layer 630 and dielectric layer 610; To form hard mask layer groove 631 and redundant metallic channel 611; Wherein, the order that forms hard mask layer groove 631 and redundant metallic channel 611 can be changed, promptly; Can form hard mask layer groove 631 earlier, and then form redundant metallic channel 611; Perhaps, form redundant metallic channel 611 earlier, and then form hard mask layer groove 631.
Shown in Fig. 6 D, thereafter, the said dielectric layer 610 of etching forms through hole 613 with the position at hard mask layer groove 631, and said hard mask layer groove 631 has played the effect of autoregistration (Self-alignment).
Shown in Fig. 6 E, then, dielectric layer shown in the etching 610 forms metallic channel 612 with the position at through hole 613.
Shown in Fig. 6 F, subsequently, depositing metal layers 620 in redundant metallic channel 611, metallic channel 612 and through hole 613 is because the characteristic of depositing operation also can deposit metal on this process medium layer 610.
Shown in Fig. 6 G; At last; Carry out chemical mechanical milling tech, all or part of metal level in removing said redundant metallic channel 612 is to form plain conductor 622 in said metallic channel 611 and through hole 613; Owing in redundant metallic channel 611, formed redundant metal in the abovementioned steps; Therefore still can obtain uniform grinding effect, therefore all or part of again metal of having removed in the redundant metallic channel 611 in this step simultaneously reduces even has eliminated in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel fully.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses all is the difference with other embodiment, the reference mutually of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for the purpose of convenience, each embodiment of aid illustration the present invention lucidly.
In addition; Although be that example has specified the present invention with the dual damascene metal interconnect structure (referring to embodiment two) of single Damascus metal interconnect structure (referring to embodiment one), through hole elder generation etching and the dual damascene metal interconnect structure (referring to embodiment three) of the first etching of the hard mask groove of autoregistration formula respectively below, those skilled in the art can also carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (4)
1. the manufacture method of a semiconductor device comprises:
On Semiconductor substrate, form dielectric layer;
The said dielectric layer of etching is to form redundant metallic channel and metallic channel, and the degree of depth of said redundant metallic channel is less than the degree of depth of said metallic channel;
Depositing metal layers in said redundant metallic channel and metallic channel and on the dielectric layer; And
Carry out chemical mechanical milling tech, part or all of metal level in removing said redundant metallic channel.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
The said dielectric layer of etching forms redundant metallic channel; And
The said dielectric layer of etching forms metallic channel.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
The said dielectric layer of etching forms redundant metallic channel and through hole;
The said dielectric layer of etching forms metallic channel with the position at said through hole.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the said dielectric layer of etching comprises with the step that forms redundant metallic channel and metallic channel:
On said dielectric layer, form hard mask layer;
Said hard mask layer of etching and dielectric layer are to form hard mask layer groove and redundant metallic channel;
The said dielectric layer of etching forms through hole with the position at said hard mask layer groove;
The said dielectric layer of etching forms metallic channel with the position at said hard mask layer groove.
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| CN2011103353459A CN102339790A (en) | 2011-10-29 | 2011-10-29 | Manufacture method of semiconductor device |
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| CN2011103353459A CN102339790A (en) | 2011-10-29 | 2011-10-29 | Manufacture method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658968A (en) * | 2013-11-21 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving flatness in fixed point grinding process of semiconductor sample |
| CN108933081A (en) * | 2017-05-23 | 2018-12-04 | 格芯公司 | Via hole and jump pore structure |
| CN111208658A (en) * | 2020-03-02 | 2020-05-29 | 合肥鑫晟光电科技有限公司 | Transfer printing plate, preparation method thereof, display substrate and display panel |
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| JP2001148421A (en) * | 1999-11-18 | 2001-05-29 | Sony Corp | Semiconductor device and method for manufacturing the same |
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US20090239375A1 (en) * | 2008-03-19 | 2009-09-24 | Philipp Riess | Dual Damascene Process |
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2011
- 2011-10-29 CN CN2011103353459A patent/CN102339790A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001148421A (en) * | 1999-11-18 | 2001-05-29 | Sony Corp | Semiconductor device and method for manufacturing the same |
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US20090239375A1 (en) * | 2008-03-19 | 2009-09-24 | Philipp Riess | Dual Damascene Process |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104658968A (en) * | 2013-11-21 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for improving flatness in fixed point grinding process of semiconductor sample |
| CN104658968B (en) * | 2013-11-21 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for improving flatness in semiconductor samples fixed point process of lapping |
| CN108933081A (en) * | 2017-05-23 | 2018-12-04 | 格芯公司 | Via hole and jump pore structure |
| CN108933081B (en) * | 2017-05-23 | 2022-04-12 | 格芯美国公司 | Via and skip structures |
| CN111208658A (en) * | 2020-03-02 | 2020-05-29 | 合肥鑫晟光电科技有限公司 | Transfer printing plate, preparation method thereof, display substrate and display panel |
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Application publication date: 20120201 |