CN102412198B - Semiconductor device fabrication method - Google Patents
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- CN102412198B CN102412198B CN201110335315.8A CN201110335315A CN102412198B CN 102412198 B CN102412198 B CN 102412198B CN 201110335315 A CN201110335315 A CN 201110335315A CN 102412198 B CN102412198 B CN 102412198B
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Abstract
The invention discloses a semiconductor device fabrication method, which ensures that the depths of a redundant metal trench and an auxiliary pattern redundant metal trench are smaller than the depth of a metal wire trench, so that the heights of a finally formed redundant metal line and a finally formed auxiliary pattern redundant metal line are smaller than the height of a metal wire. Compared with the prior art, the semiconductor device fabrication method reduces the thicknesses (heights) of the redundant metal line and the auxiliary pattern redundant metal line, consequently, an etching process window can be effectively enlarged, and moreover, the coupling capacitance in the metal layers filled with the redundant metal line and the auxiliary pattern redundant metal line and the coupling capacitance between the metal layers can be decreased.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly a kind of manufacturing method of semiconductor device.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, be subject to the restriction of the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing, the manufacture method of copper interconnecting line can not obtain by etching sheet metal as aluminum interconnecting, and the manufacture method of the copper interconnecting line extensively adopting is now the embedding technique that is called Damascus technics.This Damascus technics comprises the dual damascene process of only making single Damascus technics of plain conductor and making through hole (also claiming contact hole) and plain conductor simultaneously.Specifically, single damascene structure (also claiming single inlay structure) is only that the production method of single-layer metal wire is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled), dual-damascene structure is that through hole and plain conductor are combined, and so only needs metal filled step together.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half through hole precedence method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, first existing a kind of plain conductor manufacture craft comprise the steps:, metallization medium layer 110 first in Semiconductor substrate 100; Then in dielectric layer 110, form metallic channel by photoetching and etching technics; Depositing metal layers subsequently, described metal level is filled in metallic channel and has also deposited metal on described dielectric layer 110 surfaces; Then, carry out cmp (CMP) technique and remove the metal on described dielectric layer 110, thereby in described metallic channel, made plain conductor 140.
As mentioned above, in Damascus technics, need to utilize chemical mechanical milling tech, finally to form the plain conductor 140 being embedded in dielectric layer 110.But, because the removal rate of metal and dielectric layer material is generally not identical, therefore can causes less desirable depression (dishing) and corrode (erosion) phenomenon the selectivity of grinding.Depression often occurs in metal and goes down to the plane of contiguous dielectric layer or more than exceeding the plane of contiguous dielectric layer, and erosion is that the part of dielectric layer is excessively thin.Depression and erosion are subject to the structure of figure and the Effects of Density of figure.Therefore,, in order to reach uniform grinding effect, require the metallic pattern density in Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not meet the requirement of the cmp uniformity.At present, the method solving is the pattern density homogenizing that makes domain at the white space filling redundancy metal line pattern of domain, thereby form plain conductor 140 in dielectric layer 110 in, also form redundancy metal line (dummy metal) 150, as shown in Figure 2.But, although redundancy metal line has improved the uniformity of pattern density, but inevitably introduced in extra metal level and the coupling capacitance of metal interlevel.
Bring the negative effect of device in order to reduce extra coupling capacitance, in the time of design redundancy metal, will reduce as far as possible the filling quantity of redundancy metal, and make main graphic (plain conductor figure) and redundancy metal spacing large as far as possible.But the excessive pattern density of regional area that can cause again of the spacing of main graphic and redundancy metal is inhomogeneous, affect the regional area flatness of chemical mechanical milling tech.Under given live width condition, depth of focus (DOF) process window of various bargraphss has following relationship: the intensive lines > of intensive lines > half isolates lines.Utilize this relation, by half intensive lines and isolated lines, increase auxiliary pattern can expand the process window of half intensive lines and isolated lines.That is, auxiliary pattern can expand the lithographic process window of half intensive lines and isolated lines, improves the regional area flatness of the cmp of metal, but also can cause in larger metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The invention provides a kind of manufacturing method of semiconductor device, effectively to expand lithographic process window and to reduce redundancy metal line and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
For solving the problems of the technologies described above, the invention provides a kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district, auxiliary pattern redundancy metal district and nonredundancy metal area;
In described Semiconductor substrate, form dielectric layer;
In described redundancy metal district and auxiliary pattern redundancy metal district, form hard mask layer;
Taking described hard mask layer as dielectric layer described in mask etching, to form redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, the degree of depth of described auxiliary pattern redundancy metal groove and redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel and on dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal line, auxiliary pattern redundancy metal line and plain conductor, the height of described auxiliary pattern redundancy metal line and redundancy metal line is less than the height of described plain conductor.
Optionally, in described manufacturing method of semiconductor device, the hard mask layer thickness in described auxiliary pattern redundancy metal district is identical with the hard mask layer thickness in described redundancy metal district.The degree of depth of described auxiliary pattern redundancy metal groove is identical with the degree of depth of described redundancy metal groove.
Optionally, in described manufacturing method of semiconductor device, the hard mask layer thickness in described auxiliary pattern redundancy metal district is not identical with the hard mask layer thickness in described redundancy metal district.The degree of depth of described auxiliary pattern redundancy metal groove is not identical with the degree of depth of described redundancy metal groove.
Optionally, in described manufacturing method of semiconductor device, before forming redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, also comprise: the correspondence position at described metallic channel forms through hole.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district, auxiliary pattern redundancy metal district and nonredundancy metal area;
In described Semiconductor substrate, form dielectric layer;
On described dielectric layer, form hard mask layer, and hard mask layer described in etching, to form hard mask redundancy groove in redundancy metal district, in auxiliary pattern redundancy metal district, form hard mask auxiliary pattern groove, on nonredundancy metal area, form hard mask metallic channel, described hard mask metallic channel exposes described dielectric layer, and the degree of depth of described hard mask metallic channel is greater than the degree of depth of hard mask redundancy groove and hard mask auxiliary pattern groove;
The remaining hard mask layer of etching and dielectric layer, form redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, and the degree of depth of described auxiliary pattern redundancy metal groove and redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel and on dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal line, auxiliary pattern redundancy metal line and plain conductor, the height of described auxiliary pattern redundancy metal line and redundancy metal line is less than the height of described plain conductor.
Optionally, in described manufacturing method of semiconductor device, before forming redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, also comprise: the correspondence position at described metallic channel forms through hole.
The present invention makes the degree of depth of redundancy metal groove and auxiliary pattern redundancy metal groove be less than the degree of depth of metallic channel, therefore the height of the final redundancy metal line forming and auxiliary pattern redundancy metal line is less than the height of plain conductor, compared with prior art reduce the thickness (highly) of redundancy metal line and auxiliary pattern redundancy metal line, can effectively expand lithographic process window, and the metal level of minimizing redundancy metal line and auxiliary pattern redundancy metal line filling introducing is interior and the coupling capacitance of metal interlevel.
In addition, the present invention makes the degree of depth of redundancy metal groove be less than the degree of depth of auxiliary pattern redundancy metal groove, thereby the height that makes the redundancy metal line forming is less than the height of auxiliary pattern redundancy metal line, further reduces auxiliary pattern redundancy metal line and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Brief description of the drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 A～3F is the cross-sectional view of device corresponding to each step in the manufacturing method of semiconductor device of the embodiment of the present invention one;
Fig. 4 A～4F is the cross-sectional view of device corresponding to each step in the manufacturing method of semiconductor device of the embodiment of the present invention two;
Fig. 5 A～5G is the cross-sectional view of device corresponding to each step in the manufacturing method of semiconductor device of the embodiment of the present invention three;
Fig. 6 A～6F is the cross-sectional view of device corresponding to each step in the manufacturing method of semiconductor device of the embodiment of the present invention four.
Fig. 7 A～7G is the cross-sectional view of device corresponding to each step in the manufacturing method of semiconductor device of the embodiment of the present invention five.
Embodiment
In background technology, mention, although redundancy metal line and auxiliary pattern redundancy metal line have improved the uniformity of pattern density, but introduced in extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by following formula:
Wherein, ε
0for permittivity of vacuum; ε
rfor medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.As can be seen here, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.In view of this, the present invention makes the degree of depth of redundancy metal groove and auxiliary pattern redundancy metal groove be less than the degree of depth of metallic channel, therefore the height of the final redundancy metal line forming and auxiliary pattern redundancy metal line is less than the height of plain conductor, compared with prior art reduce the thickness (highly) of redundancy metal line and auxiliary pattern redundancy metal line, can effectively expand lithographic process window and minimizing redundancy metal line and auxiliary pattern redundancy metal line and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
The manufacturing method of semiconductor device respectively the present invention being proposed below in conjunction with generalized section is described in further detail.
Embodiment mono-
Introduce in detail the manufacturing process of single Damascus metal interconnect structure below in conjunction with Fig. 3 A～3F, the redundancy metal groove that the present embodiment forms is identical with the degree of depth of auxiliary pattern redundancy metal groove, thereby makes the redundancy metal line of formation identical with the height of auxiliary pattern redundancy metal line.
As shown in Figure 3A, first, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 comprises redundancy metal district 302, auxiliary pattern redundancy metal district 303 and nonredundancy metal area 301,, the semiconductor substrate region except redundancy metal district 302 and auxiliary pattern redundancy metal district 303 is nonredundancy metal area 301.Wherein, in described Semiconductor substrate 300, be formed with metal line, because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that forms metal line in Semiconductor substrate 300, but those skilled in the art are still this and know.
As shown in Figure 3 B, then, in described Semiconductor substrate 300, form dielectric layer 310, described dielectric layer 310 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, meets the requirement of Quick conductive.Preferably, it is black diamond (black diamond that described dielectric layer 310 adopts the trade mark of application material (Applied Materials) company, BD) silicon oxide carbide, or adopt the Coral material of Novellus company, again or adopt utilize spin coating process make, the Silk advanced low-k materials of Dow Corning Corporation etc.
In other embodiments of the invention, form dielectric layer 310 in described Semiconductor substrate 300 before, also can first form etching stop layer (not shown), described etching stop layer can be used for preventing that the metal in metal line is diffused in dielectric layer 310, and described etching stop layer also can prevent that the metal line in Semiconductor substrate 300 is etched in follow-up etching process of carrying out in addition.The material of described etching stop layer is for example silicon nitride, and the dielectric layer of itself and follow-up formation has good adhesiveness.
As shown in Figure 3 C, in described redundancy metal district 302 and auxiliary pattern redundancy metal district 303, form hard mask layer 330.Detailed, can utilize photoetching process on dielectric layer 310, to form the photoresist layer of patterning, carry out etching technics taking the photoresist layer of described patterning as mask subsequently, can remove the hard mask layer on described nonredundancy metal area 301, and only retain the hard mask layer in described redundancy metal district 302 and auxiliary pattern redundancy metal district 303, remove again subsequently the photoresist layer of patterning.In the present embodiment, the hard mask layer thickness in described auxiliary pattern redundancy metal district 303 is identical with the hard mask layer thickness in redundancy metal district 302, so, can make the degree of depth of auxiliary pattern redundancy metal groove of follow-up formation identical with the degree of depth of redundancy metal groove.
As shown in Figure 3 D, taking hard mask layer 330 as mask etching dielectric layer 310, to form redundancy metal groove 312a in redundancy metal district 302, in auxiliary pattern redundancy metal district 303, form auxiliary pattern redundancy metal groove 313a, and correspondence position on nonredundancy metal area 301 forms metallic channel 311a, owing to having formed hard mask layer 330 in redundancy metal district 302 and auxiliary pattern redundancy metal district 303, therefore after passing through same etch step, the auxiliary pattern redundancy metal groove 313a forming and the degree of depth of redundancy metal groove 312a are less than the degree of depth of metallic channel 311a.In the present embodiment, the degree of depth of auxiliary pattern redundancy metal groove 313a is identical with the degree of depth of redundancy metal groove 312a, particularly, the height of described redundancy metal groove 312a and auxiliary pattern redundancy metal groove 313a can change accordingly according to concrete technology, and the present invention also will not limit this.
As shown in Fig. 3 E, then, depositing metal layers 320 in described redundancy metal groove 312a, auxiliary pattern redundancy metal groove 313a and metallic channel 311a, due to the characteristic of depositing operation, on this process medium layer 310, also can deposit metal, the material of wherein said metal level 320 is copper.
As shown in Fig. 3 F, then, carry out cmp (CMP) technique until expose the surface of described dielectric layer 310, to form redundancy metal line 322 in redundancy metal groove 312a, form auxiliary pattern redundancy metal line 323 in auxiliary pattern redundancy metal groove 313a, form plain conductor 321 in metallic channel 311a, the height of described redundancy metal line 322 and auxiliary pattern redundancy metal line 323 is less than the height 321 of plain conductor, and redundancy metal line 322 is identical with the height of auxiliary pattern redundancy metal line 323.
Compared with prior art, the present invention has reduced the height (thickness) of redundancy metal line 322 and auxiliary pattern redundancy metal line 323, fills in the metal level of introducing and the coupling capacitance of metal interlevel thereby effectively expand lithographic process window and minimizing redundancy metal line and auxiliary pattern redundancy metal line.
Embodiment bis-
The present embodiment is introduced the manufacturing process of single Damascus metal interconnect structure in detail in conjunction with Fig. 4 A～4F, wherein, the degree of depth (highly) of redundancy metal groove and auxiliary pattern redundancy metal groove is not identical, thereby makes the height of the final redundancy metal line forming and auxiliary pattern redundancy metal line not identical yet.
As shown in Figure 4 A, first, Semiconductor substrate 400 is provided, described Semiconductor substrate 400 comprises redundancy metal district 402, auxiliary pattern redundancy metal district 403 and nonredundancy metal area 401, and wherein the semiconductor substrate region except redundancy metal district 402 and auxiliary pattern redundancy metal district 403 is nonredundancy metal area 401.
As shown in Figure 4 B, then, in described Semiconductor substrate 400, form dielectric layer 410.
As shown in Figure 4 C, then, in described redundancy metal district 402 and auxiliary pattern redundancy metal district 403, form hard mask layer 430.In the present embodiment, the hard mask layer thickness in auxiliary pattern redundancy metal district 403 is not identical with the hard mask layer thickness in redundancy metal district 402, so, can make the degree of depth of auxiliary pattern redundancy metal groove of follow-up formation not identical with the degree of depth of redundancy metal groove.For example, can first on dielectric layer 410, form hard mask film, then utilize etching technics to remove the hard mask film on nonredundancy metal area 401, recycle another etching technics, the hard mask layer film of removing segment thickness in redundancy metal district 402, can make the hard mask layer thickness in auxiliary pattern redundancy metal district 403 be greater than the hard mask layer thickness in redundancy metal district 402.
As shown in Figure 4 D, taking hard mask layer 430 as mask etching dielectric layer 410, to form redundancy metal groove 412a in redundancy metal district 402, in auxiliary pattern redundancy metal district 403, form auxiliary pattern redundancy metal groove 413a, and correspondence position on nonredundancy metal area 401 forms metallic channel 411a, owing to having formed hard mask layer 430 in redundancy metal district 402 and auxiliary pattern redundancy metal district 403, therefore, through after same etch step, the auxiliary pattern redundancy metal groove 413a forming and the degree of depth of redundancy metal groove 412a are less than the degree of depth of metallic channel 411a, and, the degree of depth of auxiliary pattern redundancy metal groove 413a is less than the degree of depth of redundancy metal groove 412a.
As shown in Figure 4 E, then, on described redundancy metal groove 412a, auxiliary pattern redundancy metal groove 413a and metallic channel 411a and dielectric layer 410 in depositing metal layers 420.
As shown in Fig. 4 F, then, carry out cmp (CMP) technique until expose the surface of described dielectric layer 410, to form redundancy metal line 422 in redundancy metal groove 412a, form auxiliary pattern redundancy metal line 423 in auxiliary pattern redundancy metal groove 413a, form plain conductor 421 in metallic channel 411a, the height of described redundancy metal line 422 and auxiliary pattern redundancy metal line 423 is less than the height 421 of plain conductor, and the height of redundancy metal line 422 is less than the height of auxiliary pattern redundancy metal line 423.
Compared with embodiment mono-, the degree of depth (highly) of the redundancy metal groove 412a forming in the present embodiment and auxiliary pattern redundancy metal groove 413a is not identical, thereby make the redundancy metal line 422 of formation also not identical with the height of auxiliary pattern redundancy metal line 423, further reduce redundancy metal line and auxiliary pattern redundancy metal line and filled in the metal level of introducing and the coupling capacitance of metal interlevel, and expanded lithographic process window.
Embodiment tri-
The present embodiment is introduced the manufacturing process of the dual damascene metal interconnect structure of the first etching of through hole in detail in conjunction with Fig. 5 A～5G, wherein, the degree of depth (highly) of redundancy metal groove and auxiliary pattern redundancy metal groove is identical, thereby makes the height of the final redundancy metal line forming and auxiliary pattern redundancy metal line also identical.
As shown in Figure 5A, first, Semiconductor substrate 500 is provided, described Semiconductor substrate 500 comprises redundancy metal district 502, auxiliary pattern redundancy metal district 503 and nonredundancy metal area 501, and wherein the semiconductor substrate region except redundancy metal district 502 and auxiliary pattern redundancy metal district 503 is nonredundancy metal area 501.
As shown in Figure 5 B, then, in described Semiconductor substrate 500, form dielectric layer 510.
As shown in Figure 5 C, then, in described redundancy metal district 502 and auxiliary pattern redundancy metal district 503, form hard mask layer 530.
As shown in Figure 5 D, then, the dielectric layer described in etching on nonredundancy metal area 501, forms through hole 511b in the position of metallic channel to be formed.
As shown in Fig. 5 E, then, taking hard mask layer 530 as mask etching dielectric layer 510, to form redundancy metal groove 512a and auxiliary pattern redundancy metal groove 513a, form metallic channel 511a at the correspondence position of described through hole 511b simultaneously, the degree of depth of described auxiliary pattern redundancy metal groove 513a equals the degree of depth of redundancy metal groove 512a, and the degree of depth of described auxiliary pattern redundancy metal groove 513a and redundancy metal groove 512a is less than the degree of depth of metallic channel 511a.
As shown in Fig. 5 F, then, depositing metal layers 520 in described redundancy metal groove 512a, auxiliary pattern redundancy metal groove 513a, metallic channel 511a and through hole 511b and on dielectric layer 510.
As shown in Fig. 5 G, carry out chemical mechanical milling tech until expose the surface of described dielectric layer 520, to form redundancy metal line 522, auxiliary pattern redundancy metal line 523 and plain conductor 521, described auxiliary pattern redundancy metal line 523 is identical with the height of redundancy metal line 522, and the height of described auxiliary pattern redundancy metal line 523 and redundancy metal line 522 is less than the height of described plain conductor 521.
Compared with previous embodiment, the present embodiment first forms through hole 511b and then forms redundancy metal groove 512a, auxiliary pattern redundancy metal groove 513a and metallic channel 511a, and the degree of depth of auxiliary pattern redundancy metal groove 513a and redundancy metal groove 512a is less than the degree of depth of metallic channel 511a, thereby the height that makes auxiliary pattern redundancy metal line 523 and redundancy metal line 522 is all less than the height of plain conductor 521, reduce the height (thickness) of redundancy metal line 522 and auxiliary pattern redundancy metal line 523, thereby effectively reducing redundancy metal line and auxiliary pattern redundancy metal line fills in the metal level of introducing and the coupling capacitance of metal interlevel, and expand lithographic process window.
Embodiment tetra-
The present embodiment is introduced the manufacturing process of the hard mask list of self-alignment type Damascus metal interconnect structure in detail in conjunction with Fig. 6 A～6F, wherein, the degree of depth (highly) of redundancy metal groove and auxiliary pattern redundancy metal groove can identical can be not identical yet.
As shown in Figure 6A, first, provide Semiconductor substrate 600, described Semiconductor substrate 600 comprises redundancy metal district 602, auxiliary pattern redundancy metal district 603 and nonredundancy metal area 601.
As shown in Figure 6B, then, in described Semiconductor substrate 600, form successively dielectric layer 610.
As shown in Figure 6 C, subsequently, on dielectric layer 610, form hard mask layer, and etching hard mask layer, to form hard mask redundancy groove 632a in redundancy metal district 602, in auxiliary pattern redundancy metal district 603, form hard mask auxiliary pattern groove 633a, on nonredundancy metal area 601, form hard mask metallic channel 631a, described hard mask metallic channel 631a exposes the surface of dielectric layer 610, and the degree of depth of hard mask metallic channel 631a is greater than the degree of depth of hard mask redundancy groove 632a and hard mask auxiliary pattern groove 633a, , hard mask redundancy groove 632a and hard mask auxiliary pattern groove 633a do not expose the surface of dielectric layer 610.
As shown in Figure 6 D, then, the remaining hard mask layer of etching and dielectric layer 610, form redundancy metal groove 612a, auxiliary pattern redundancy metal groove 613a and metallic channel 611a, the degree of depth of described auxiliary pattern redundancy metal groove 613a and redundancy metal groove 612a is less than the degree of depth of described metallic channel 611a.
As shown in Fig. 6 E, then, depositing metal layers 620 in described redundancy metal groove 612a, auxiliary pattern redundancy metal groove 613a and metallic channel 611a and on dielectric layer.
As shown in Fig. 6 F, then, carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal line 622, auxiliary pattern redundancy metal line 623 and plain conductor 621, the height of described auxiliary pattern redundancy metal line 623 is less than the height of described redundancy metal line 622, and the height of described redundancy metal line 622 is less than the height of described plain conductor 621.
The present embodiment is by making the degree of depth of hard mask metallic channel 631a be greater than the degree of depth of hard mask redundancy groove 632a and hard mask auxiliary pattern groove 633a, thereby the height that makes auxiliary pattern redundancy metal line 623 and redundancy metal line 622 is all less than the height of plain conductor 621, reduce the height (thickness) of redundancy metal line 622 and auxiliary pattern redundancy metal line 623, reduce redundancy metal line and auxiliary pattern redundancy metal line and filled in the metal level of introducing and the coupling capacitance of metal interlevel, and expanded lithographic process window.
Embodiment five
The present embodiment is introduced the manufacturing process of the hard mask dual damascene of self-alignment type metal interconnect structure in detail in conjunction with Fig. 7 A～7G, wherein, the degree of depth (highly) of redundancy metal groove and auxiliary pattern redundancy metal groove is identical, thereby makes the redundancy metal line of formation not identical with the height of auxiliary pattern redundancy metal line.
As shown in Figure 7 A, first, provide Semiconductor substrate 700, described Semiconductor substrate 700 comprises redundancy metal district 702, auxiliary pattern redundancy metal district 703 and nonredundancy metal area 701.
As shown in Figure 7 B, in described Semiconductor substrate 700, form dielectric layer 710.
As shown in Fig. 7 C, subsequently, on dielectric layer 710, form hard mask layer, and etching hard mask layer, to form hard mask redundancy groove 732a in redundancy metal district 702, in auxiliary pattern redundancy metal district 703, form hard mask auxiliary pattern groove 733a, on the correspondence position of nonredundancy metal area 701, form hard mask metallic channel 731a, described hard mask metallic channel 731a exposes the surface of dielectric layer 710, and the degree of depth of hard mask metallic channel 731a is greater than the degree of depth of hard mask redundancy groove 732a and hard mask auxiliary pattern groove 733a.
As shown in Fig. 7 D, the dielectric layer described in etching on nonredundancy metal area 701 forms through hole 711b with the correspondence position at described hard mask metallic channel 731a.
As shown in Fig. 7 E, then, taking described hard mask layer as mask etching dielectric layer 710, to form redundancy metal groove 712a and auxiliary pattern redundancy metal groove 713a, while is at the correspondence position metallic channel 711a of through hole 711b, the degree of depth of auxiliary pattern redundancy metal groove 713a equals the degree of depth of redundancy metal groove 712a, and the degree of depth of described auxiliary pattern redundancy metal groove 713a and redundancy metal groove 712a is all less than the degree of depth of metallic channel 711a.
As shown in Figure 7 F, then, depositing metal layers 720 in described redundancy metal groove 712a, auxiliary pattern redundancy metal groove 713a, metallic channel 711 and through hole 711b and on dielectric layer 710.
As shown in Figure 7 G, carry out chemical mechanical milling tech until expose the surface of described dielectric layer 720, to form redundancy metal line 722, auxiliary pattern redundancy metal line 723 and plain conductor 721, described auxiliary pattern redundancy metal line 723 is identical with the height of redundancy metal line 722, and the height of described auxiliary pattern redundancy metal line 723 and redundancy metal line 722 is less than the height of described plain conductor 721.
Compared with embodiment tetra-, the present embodiment first forms through hole 711b and then forms redundancy metal groove 712a, auxiliary pattern redundancy metal groove 713a and metallic channel 711a, and reduce the height (thickness) of redundancy metal line 722 and auxiliary pattern redundancy metal line 723, fill in the metal level of introducing and the coupling capacitance of metal interlevel thereby effectively reduce redundancy metal line and auxiliary pattern redundancy metal line, expanded lithographic process window.
It should be noted that, in this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment, the reference mutually of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only for object convenient, each embodiment of aid illustration the present invention lucidly.
In addition,, although describe the present invention in detail with multiple embodiment respectively above, those skilled in the art can also carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (8)
1. a manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district, auxiliary pattern redundancy metal district and nonredundancy metal area;
In described Semiconductor substrate, form dielectric layer;
In described redundancy metal district and auxiliary pattern redundancy metal district, form hard mask layer;
Taking described hard mask layer as dielectric layer described in mask etching, to form redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, the degree of depth of described auxiliary pattern redundancy metal groove and redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel and on dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal line, auxiliary pattern redundancy metal line and plain conductor, the height of described auxiliary pattern redundancy metal line and redundancy metal line is less than the height of described plain conductor.
2. manufacturing method of semiconductor device as claimed in claim 1, is characterized in that, the hard mask layer thickness in described auxiliary pattern redundancy metal district is identical with the hard mask layer thickness in described redundancy metal district.
3. manufacturing method of semiconductor device as claimed in claim 2, is characterized in that, the degree of depth of described auxiliary pattern redundancy metal groove is identical with the degree of depth of described redundancy metal groove.
4. manufacturing method of semiconductor device as claimed in claim 1, is characterized in that, the hard mask layer thickness in described auxiliary pattern redundancy metal district is not identical with the hard mask layer thickness in described redundancy metal district.
5. manufacturing method of semiconductor device as claimed in claim 4, is characterized in that, the degree of depth of described auxiliary pattern redundancy metal groove is not identical with the degree of depth of described redundancy metal groove.
6. the manufacturing method of semiconductor device as described in any one in claim 1 to 5, is characterized in that, before forming redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, also comprises: the correspondence position at described metallic channel forms through hole.
7. a manufacturing method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district, auxiliary pattern redundancy metal district and nonredundancy metal area;
In described Semiconductor substrate, form dielectric layer;
On described dielectric layer, form hard mask layer, and hard mask layer described in etching, to form hard mask redundancy groove in redundancy metal district, in auxiliary pattern redundancy metal district, form hard mask auxiliary pattern groove, on nonredundancy metal area, form hard mask metallic channel, described hard mask metallic channel exposes described dielectric layer, and the degree of depth of described hard mask metallic channel is greater than the degree of depth of hard mask redundancy groove and hard mask auxiliary pattern groove;
The remaining hard mask layer of etching and dielectric layer, form redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, and the degree of depth of described auxiliary pattern redundancy metal groove and redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel and on dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal line, auxiliary pattern redundancy metal line and plain conductor, the height of described auxiliary pattern redundancy metal line and redundancy metal line is less than the height of described plain conductor.
8. manufacturing method of semiconductor device as claimed in claim 7, is characterized in that, before forming redundancy metal groove, auxiliary pattern redundancy metal groove and metallic channel, also comprises: the correspondence position at described metallic channel forms through hole.
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
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| JP5650878B2 (en) * | 2007-06-20 | 2015-01-07 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Dummy pattern design method, exposure mask, semiconductor device, semiconductor device manufacturing method, and dummy pattern design program |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
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| US6001733A (en) * | 1998-06-26 | 1999-12-14 | United Microelectronics Corp. | Method of forming a dual damascene with dummy metal lines |
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