CN102324399B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102324399B CN102324399B CN 201110298520 CN201110298520A CN102324399B CN 102324399 B CN102324399 B CN 102324399B CN 201110298520 CN201110298520 CN 201110298520 CN 201110298520 A CN201110298520 A CN 201110298520A CN 102324399 B CN102324399 B CN 102324399B
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The depth of a redundant metal trough and the depth of an auxiliary picture redundant metal trough are shallower than that of a metal lead trough, therefore, the heights of the finally formed redundant metal wire and auxiliary picture redundant metal wire are lower than that of the metal lead, and the thickness of a redundant metal wire and the thickness of an auxiliary picture redundant metal wire are reduced compared with the prior art, thus being capable of effectively expanding a photoetching process window, and reducing coupling capacitors which are in metal layers and among metal layers during filling of the redundant metal wire and the auxiliary picture redundant metal wire.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of semiconductor device and preparation method thereof.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, be subjected to the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain by etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts is the embedding technique that is called Damascus technics now.This Damascus technics comprises single Damascus technics of only making plain conductor and makes the dual damascene process of through hole (also claiming contact hole) and plain conductor simultaneously.Specifically, single damascene structure (also claiming single inlay structure) only is that the production method of single-layer metal lead is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled), dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half via-first method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; In dielectric layer 110, form metallic channel by photoetching and etching technics then; Depositing metal layers subsequently, described metal level are filled in the metallic channel and on described dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technology and remove metal on the described dielectric layer 110, thereby in described metallic channel, made plain conductor 140.
As mentioned above, in Damascus technics, need to utilize chemical mechanical milling tech, be embedded in plain conductor 140 in the dielectric layer 110 with final formation.Yet, because the rate that removes of metal and dielectric layer material is generally inequality, therefore can causes the depression of not expecting (dishing) and corrode (erosion) phenomenon the selectivity of grinding.Depression occurs in metal often and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is thin excessively.Depression and erosion are subject to the structure of figure and the density influence of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, the method for solution is to fill the pattern density homogenizing that redundant metal line pattern makes domain at the white space of domain, thereby also forms redundant metal wire (dummy metal) 150 when forming plain conductor 140 in dielectric layer 110, as shown in Figure 2.But, though redundant metal wire has improved the uniformity of pattern density, but introduced in the extra metal level inevitably and the coupling capacitance of metal interlevel.
In order to reduce the negative effect that extra coupling capacitance brings device, when the redundant metal of design, to reduce the filling quantity of redundant metal as far as possible, and make main graphic (plain conductor figure) big as far as possible with redundant intermetallic distance.Yet the excessive pattern density of regional area that can cause again of the spacing of main graphic and redundant metal is inhomogeneous, influences the regional area flatness of chemical mechanical milling tech.Under given live width condition, the depth of focus of various bargraphss (DOF) process window has following relationship: intensive lines＞half intensive lines＞isolated lines.Utilize this relation, increase the process window that auxiliary pattern can enlarge half intensive lines and isolated lines at half intensive lines and isolated lines side.That is, auxiliary pattern can enlarge the lithographic process window of half intensive lines and isolated lines, improves the regional area flatness of the cmp of metal, but also can cause in the bigger metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The invention provides a kind of semiconductor device and preparation method thereof, to enlarge lithographic process window effectively and to reduce redundant metal wire and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
For solving the problems of the technologies described above, the invention provides a kind of manufacturing method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area; Form dielectric layer in described Semiconductor substrate; Dielectric layer on the described nonredundancy metal area of attenuate; The described dielectric layer of etching is to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel; Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer; Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area; Form dielectric layer and hard mask layer in described Semiconductor substrate; Remove the hard mask layer on described redundant metal area and the nonredundancy metal area; Dielectric layer on the described nonredundancy metal area of attenuate and the redundant metal area makes on the described redundant metal area remaining thickness of dielectric layers greater than remaining thickness of dielectric layers on the described nonredundancy metal area; The described dielectric layer of etching is to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel simultaneously, the degree of depth of the redundant metallic channel of described auxiliary pattern is less than the degree of depth of described redundant metallic channel, and the degree of depth of described redundant metallic channel is less than the degree of depth of described metallic channel; Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer; Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described auxiliary pattern is less than the height of described redundant metal wire, and the height of described redundant metal wire is less than the height of described plain conductor.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area; Form dielectric layer in described Semiconductor substrate; Dielectric layer on the described nonredundancy metal area of attenuate; Dielectric layer on the described nonredundancy metal area of etching forms through hole; The described dielectric layer of etching to be forming the redundant metallic channel of redundant metallic channel and auxiliary pattern, and forms metallic channel at described through hole correspondence position, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel; Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer; Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of plain conductor.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area; On described Semiconductor substrate, form dielectric layer and hard mask layer successively; Remove the hard mask layer on described redundant metal area and the nonredundancy metal area; Dielectric layer on the described nonredundancy metal area of attenuate and the redundant metal area, remaining thickness of dielectric layers is greater than remaining thickness of dielectric layers on the described nonredundancy metal area on the described redundant metal area; Dielectric layer on the described nonredundancy metal area of etching forms through hole; The described dielectric layer of etching is to form the redundant metallic channel of redundant metallic channel and auxiliary pattern, and at described through hole correspondence position formation metallic channel, the degree of depth of the redundant metallic channel of described auxiliary pattern is less than the degree of depth of described redundant metallic channel, and the degree of depth of described redundant metallic channel is less than the degree of depth of described metallic channel; Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer; Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described auxiliary pattern is less than the height of described redundant metal wire, and the height of described redundant metal wire is less than the height of described plain conductor.
The present invention also provides another kind of manufacturing method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area; Form dielectric layer in described Semiconductor substrate; Dielectric layer on the described nonredundancy metal area of attenuate; Form the autoregistration hard mask layer at described dielectric layer; The described autoregistration hard mask layer of etching form hard mask metallic channel and remove described redundant metal area and the redundant metal area of auxiliary pattern on the autoregistration hard mask layer; Dielectric layer on the described nonredundancy metal area of etching forms through hole with the position at described hard mask metallic channel; The described dielectric layer of etching to be forming the redundant metallic channel of redundant metallic channel and auxiliary pattern, and forms metallic channel at described through hole correspondence position, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel; Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer; Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
According to another side of the present invention, a kind of semiconductor device also is provided, comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; And being formed at redundant metal wire in the described dielectric layer, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
Optionally, in described semiconductor device, the height of the redundant metal wire of described auxiliary pattern equals the height of described redundant metal wire.
Optionally, in described semiconductor device, the height of the redundant metal wire of described auxiliary pattern is less than the height of described redundant metal wire.
The present invention makes the degree of depth of redundant metallic channel and the redundant metallic channel of auxiliary pattern less than the degree of depth of metallic channel, therefore the height of the final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern, can enlarge lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.Further, the present invention makes the degree of depth of redundant metallic channel less than the degree of depth of the redundant metallic channel of auxiliary pattern, thereby make the height of redundant metal wire of formation less than the height of the redundant metal wire of auxiliary pattern, further reduce the redundant metal wire of auxiliary pattern and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 A～3F is the cross-sectional view of the device of each step correspondence in the manufacturing method of semiconductor device of the embodiment of the invention one;
Fig. 4 A～4G is the cross-sectional view of the device of each step correspondence in the manufacturing method of semiconductor device of the embodiment of the invention two;
Fig. 5 A～5G is the cross-sectional view of the device of each step correspondence in the manufacturing method of semiconductor device of the embodiment of the invention three;
Fig. 6 A～6H is the cross-sectional view of the device of each step correspondence in the manufacturing method of semiconductor device of the embodiment of the invention four.
Fig. 7 A～7I is the cross-sectional view of the device of each step correspondence in the manufacturing method of semiconductor device of the embodiment of the invention five.
Embodiment
Mention that in background technology though the redundant metal wire of redundant metal wire and auxiliary pattern has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by following formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.In view of this, the present invention makes the degree of depth of redundant metallic channel and the redundant metallic channel of auxiliary pattern less than the degree of depth of metallic channel, therefore the height of the final redundant metal wire that forms and the redundant metal wire of auxiliary pattern is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of the redundant metal wire of redundant metal wire and auxiliary pattern, can enlarge lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Semiconductor device that respectively the present invention is proposed below in conjunction with generalized section and preparation method thereof is described in further detail.
Embodiment one
Introduce the manufacturing process of single Damascus metal interconnect structure in detail below in conjunction with Fig. 3 A～3F, the redundant metallic channel that present embodiment forms is identical with the degree of depth of the redundant metallic channel of auxiliary pattern, thereby makes the redundant metal wire of formation identical with the height of the redundant metal wire of auxiliary pattern.
As shown in Figure 3A, at first, Semiconductor substrate 300 is provided, described Semiconductor substrate 300 comprises redundant metal area 302, the redundant metal area 303 of auxiliary pattern and nonredundancy metal area 301, that is, the semiconductor substrate region except redundant metal area 302 and the redundant metal area 303 of auxiliary pattern is nonredundancy metal area 301.Wherein, be formed with metal line in the described Semiconductor substrate 300, because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 300, forms metal line, but those skilled in the art are still this and know.
Shown in Fig. 3 B, then, form dielectric layer 310 in described Semiconductor substrate 300, the thickness of described dielectric layer 310 is the required thickness of dielectric layers of the plain conductor degree of depth and the thickness of dielectric layers sum of wanting attenuate in subsequent step.Wherein, described dielectric layer 310 is preferably low-k (K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of conduction fast.Preferable, it is black diamond (black diamond that described dielectric layer 310 adopts the trade mark of Material Used (Applied Materials) company, BD) silicon oxide carbide, perhaps adopt the Coral material of Novellus company, again or adopt and to utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.
In other embodiments of the invention, before described Semiconductor substrate 300 forms dielectric layer 310, also can form etching stop layer (not shown) earlier, described etching stop layer can be used for preventing that the metal in the metal line is diffused in the dielectric layer 310, and described etching stop layer can prevent that also the metal line in the Semiconductor substrate 300 is etched in follow-up etching process of carrying out in addition.The material of described etching stop layer for example is silicon nitride, and the dielectric layer of itself and follow-up formation has good adhesive force.
Shown in Fig. 3 C, then, the dielectric layer on the attenuate nonredundancy metal area 301.Detailed, can utilize photoetching process to form first mask layer at dielectric layer 310, described first mask layer exposes described nonredundancy metal area 301, be that mask carries out etching technics with described first mask layer subsequently, can remove the dielectric layer on the described nonredundancy metal area 301, and the dielectric layer on the redundant metal area 303 of described redundant metal area 302 and auxiliary pattern is not thinned, and can utilize the mode of dry method or wet method to remove described first mask layer then.
Shown in Fig. 3 D, thereafter, utilize photoetching process to form at dielectric layer 310 and have redundant metallic channel pattern, second mask layer of the redundant metallic channel pattern of auxiliary pattern and metallic channel pattern, and be mask with described second mask layer, the described dielectric layer of etching, to form redundant metallic channel 312a at described redundant metal area 302, form the redundant metallic channel 313a of auxiliary pattern at the redundant metal area 303 of auxiliary pattern, and the correspondence position on nonredundancy metal area 301 forms metallic channel 311a, because the thickness of dielectric layers on the redundant metal area 303 of redundant metal area 302 and auxiliary pattern greater than the thickness of dielectric layers on the nonredundancy metal area 301, therefore utilizes the degree of depth of redundant metallic channel 312a that same etch step forms and the redundant metallic channel 313a of auxiliary pattern less than the degree of depth 311a of metallic channel.In the present embodiment, owing to the thickness of dielectric layers on the redundant metal area 303 of redundant metal area 302 and auxiliary pattern is identical, therefore redundant metallic channel 312a is identical with the degree of depth of the redundant metallic channel 313a of auxiliary pattern, and the thickness that previous step medium layer is thinned is the poor of metallic channel 311a and the redundant metallic channel 312a degree of depth (highly).Then can utilize the mode of dry method or wet method to remove described second mask layer.Wherein, the height of the redundant metallic channel 313a of described redundant metallic channel 312a and auxiliary pattern can change accordingly according to concrete technology, the thickness that dielectric layer on the described nonredundancy metal area 301 is thinned can determine that also the present invention also will not limit this according to concrete technology.
Shown in Fig. 3 E, then, depositing metal layers 320 in described redundant metallic channel 312a, the redundant metallic channel 313a of auxiliary pattern and metallic channel 311a is because the characteristic of depositing operation, also can deposit metal on this process medium layer 310, the material of wherein said metal level 320 is copper.
Shown in Fig. 3 F, then, carry out cmp (CMP) technology until the surface that exposes described dielectric layer 310, in redundant metallic channel 312a, to form redundant metal wire 322, in the redundant metallic channel 313a of auxiliary pattern, form the redundant metal wire 323 of auxiliary pattern, in metallic channel 311a, to form plain conductor 321, the height of the redundant metal wire 323 of described redundant metal wire 322 and auxiliary pattern is less than the height 321 of described plain conductor, and redundant metal wire 322 is identical with the height of the redundant metal wire 323 of auxiliary pattern.
Compared with prior art, the present invention has reduced the height (thickness) of the redundant metal wire 323 of redundant metal wire 322 and auxiliary pattern, thereby enlarges lithographic process window effectively and reduce redundant metal wire and the redundant metal wire of auxiliary pattern is filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment two
Present embodiment is introduced the manufacturing process of single Damascus metal interconnect structure in detail in conjunction with Fig. 4 A～4G, wherein, the degree of depth (highly) of the redundant metallic channel of redundant metallic channel and auxiliary pattern is inequality, thereby makes the height of the redundant metal wire of formation and the redundant metal wire of auxiliary pattern also inequality.
Shown in Fig. 4 A, at first, Semiconductor substrate 400 is provided, described Semiconductor substrate 400 comprises redundant metal area 402, the redundant metal area 403 of auxiliary pattern and nonredundancy metal area 401, and wherein the semiconductor substrate region except redundant metal area 402 and the redundant metal area 403 of auxiliary pattern is nonredundancy metal area 401.
Shown in Fig. 4 B, then, on described Semiconductor substrate 400, form dielectric layer 410 and hard mask layer (hard mask layer) 430 successively.
Shown in Fig. 4 C, then, remove the hard mask layer on described redundant metal area 402 and the nonredundancy metal area 401, and only keep the hard mask layer on the redundant metal area 403 of described auxiliary pattern.
Shown in Fig. 4 D, then, dielectric layer on attenuate nonredundancy metal area 401 and the redundant metal area 402, in this step, because blocking of remaining hard mask layer, dielectric layer on the redundant metal area 403 of described auxiliary pattern does not have attenuate fully, and, the thickness that the thickness that dielectric layer on the described nonredundancy metal area 401 is removed is removed greater than dielectric layer on the redundant metal area 402, namely, remaining thickness of dielectric layers is greater than remaining thickness of dielectric layers on the nonredundancy metal area 401 on the described redundant metal area 402, and on the redundant metal area 402 remaining thickness of dielectric layers less than the thickness of dielectric layers on the redundant metal area 403 of auxiliary pattern.
Shown in Fig. 4 E, then, the etching dielectric layer is to form redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern and metallic channel 411a, the degree of depth of the redundant metallic channel 413a of described auxiliary pattern is less than the degree of depth of redundant metallic channel 412a, and the degree of depth of described redundant metallic channel 412a is less than the degree of depth of metallic channel 411a.
Shown in Fig. 4 F, then, depositing metal layers 420 in described redundant metallic channel 412a, the redundant metallic channel 413a of auxiliary pattern and metallic channel 411a and on the dielectric layer 410.
Shown in Fig. 4 G, then, carry out chemical mechanical milling tech until the surface that exposes dielectric layer 420, to form redundant metal wire 422, the redundant metal wire 423 of auxiliary pattern and plain conductor 421, the height of the redundant metal wire 423 of described auxiliary pattern is less than the height of redundant metal wire 422, and the height of described redundant metal wire 422 is less than the height of described plain conductor 421.
Compare with embodiment one, the degree of depth (highly) of the redundant metallic channel 413a of the surplus metal raceway 412a that forms in the present embodiment and auxiliary pattern is inequality, thereby the height of the feasible redundant metal wire 422 that forms and the redundant metal wire 423 of auxiliary pattern is also inequality, further reduce the redundant metal wire of redundant metal wire and auxiliary pattern and filled in the metal level of introducing and the coupling capacitance of metal interlevel, and enlarged lithographic process window.
Embodiment three
Present embodiment is introduced the manufacturing process of the dual damascene metal interconnect structure of through hole elder generation etching in detail in conjunction with Fig. 5 A～5G, wherein, redundant metallic channel is identical with the degree of depth (highly) of the redundant metallic channel of auxiliary pattern, thereby makes the final redundant metal wire that forms also identical with the height of the redundant metal wire of auxiliary pattern.
Shown in Fig. 5 A, at first, Semiconductor substrate 500 is provided, described Semiconductor substrate 500 comprises redundant metal area 502, the redundant metal area 503 of auxiliary pattern and nonredundancy metal area 501, and wherein the semiconductor substrate region except redundant metal area 502 and the redundant metal area 503 of auxiliary pattern is nonredundancy metal area 501.
Shown in Fig. 5 B, then, form dielectric layer 510 in described Semiconductor substrate 500.
Shown in Fig. 5 C, then, the dielectric layer on the described nonredundancy metal area 501 of attenuate.
Shown in Fig. 5 D, then, the dielectric layer on the described nonredundancy metal area 501 of etching forms through hole 511b.
Shown in Fig. 5 E, then, the described dielectric layer 510 of etching, to form the redundant metallic channel 513a of redundant metallic channel 512a and auxiliary pattern, while is at the correspondence position metallic channel 511a of described through hole 511b, the degree of depth of the redundant metallic channel 513a of described auxiliary pattern equals the degree of depth of described redundant metallic channel 512a, and the degree of depth of the redundant metallic channel 513a of described auxiliary pattern and redundant metallic channel 512a is less than the degree of depth of metallic channel 511a.
Shown in Fig. 5 F, then, depositing metal layers 520 in described redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern and metallic channel 511a and on the dielectric layer 510.
Shown in Fig. 5 G, carry out chemical mechanical milling tech until the surface that exposes described dielectric layer 520, to form redundant metal wire 522, the redundant metal wire 523 of auxiliary pattern and plain conductor 521, the redundant metal wire 523 of described auxiliary pattern is identical with the height of redundant metal wire 522, and the height of the redundant metal wire 523 of described auxiliary pattern and redundant metal wire 522 is less than the height of described plain conductor 521.
Compare with previous embodiment, present embodiment forms through hole 511b earlier and then forms redundant metallic channel 512a, the redundant metallic channel 513a of auxiliary pattern and metallic channel 511a, the degree of depth of the redundant metallic channel 513a of described auxiliary pattern is identical with the degree of depth of redundant metallic channel 512a, and the degree of depth of the redundant metallic channel 513a of auxiliary pattern and redundant metallic channel 512a is less than the degree of depth of metallic channel 511a, thereby make the redundant metal wire 522 of formation identical with the height of the redundant metal wire 523 of auxiliary pattern, and the height of the redundant metal wire 523 of auxiliary pattern and redundant metal wire 522 is all less than the height of plain conductor 521, reduced the height (thickness) of the redundant metal wire 523 of redundant metal wire 522 and auxiliary pattern, fill in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduce the redundant metal wire of redundant metal wire and auxiliary pattern effectively, and enlarged lithographic process window.
Embodiment four
Present embodiment is introduced the manufacturing process of the dual damascene metal interconnect structure of through hole elder generation etching in detail in conjunction with Fig. 6 A～6H, wherein, the degree of depth (highly) of the redundant metallic channel of redundant metallic channel and auxiliary pattern is inequality, thereby makes the height of the redundant metal wire of formation and the redundant metal wire of auxiliary pattern also inequality.
As shown in Figure 6A, at first, provide Semiconductor substrate 600, described Semiconductor substrate 600 comprises redundant metal area 602, the redundant metal area 603 of auxiliary pattern and nonredundancy metal area 601.
Shown in Fig. 6 B, then, on described Semiconductor substrate 600, form dielectric layer 610 and hard mask layer 630 successively.
Shown in Fig. 6 C, subsequently, remove the hard mask layer on described redundant metal area 602 and the nonredundancy metal area 601, only keep the hard mask layer on the redundant metal area 603 of auxiliary pattern.
Shown in Fig. 6 D, then, the dielectric layer on the described nonredundancy metal area 601 of attenuate and the redundant metal area 602, remaining thickness of dielectric layers is greater than remaining thickness of dielectric layers on the nonredundancy metal area 601 on the described redundant metal area 602.
Shown in Fig. 6 E, then, the dielectric layer on the described nonredundancy metal area 601 of etching forms through hole 611b.
Shown in Fig. 6 F, then, the described dielectric layer of etching is to form redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a simultaneously, the degree of depth of the redundant metallic channel 613a of described auxiliary pattern is less than the degree of depth of described redundant metallic channel 612a, and the degree of depth of described redundant metallic channel 612a is less than the degree of depth of described metallic channel 611a.
Shown in Fig. 6 G, then, depositing metal layers 620 in described redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a and on the dielectric layer.
Shown in Fig. 6 H, then, carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire 622, the redundant metal wire 623 of auxiliary pattern and plain conductor 621, the height of the redundant metal wire 623 of described auxiliary pattern is less than the height of described redundant metal wire 622, and the height of described redundant metal wire 622 is less than the height of described plain conductor 621.
Compare with embodiment four, present embodiment forms through hole 611b earlier and then forms redundant metallic channel 612a, the redundant metallic channel 613a of auxiliary pattern and metallic channel 611a, the degree of depth of the redundant metallic channel 613a of described auxiliary pattern is less than the degree of depth of redundant metallic channel 612a, thereby make the height of the redundant metal wire 623 of the redundant metal wire 622 of formation and auxiliary pattern inequality, and the height of the redundant metal wire 623 of auxiliary pattern and redundant metal wire 622 is all less than the height of plain conductor 621, reduced the height (thickness) of the redundant metal wire 623 of redundant metal wire 622 and auxiliary pattern, reduce the redundant metal wire of redundant metal wire and auxiliary pattern further and fill in the metal level of introducing and the coupling capacitance of metal interlevel, and enlarged lithographic process window.
Embodiment five
Present embodiment is introduced the manufacturing process of the hard mask dual damascene of autoregistration formula metal interconnect structure in detail in conjunction with Fig. 7 A～7I, wherein, redundant metallic channel is identical with the degree of depth (highly) of the redundant metallic channel of auxiliary pattern, thereby the height of the feasible redundant metal wire that forms and the redundant metal wire of auxiliary pattern is inequality.
Shown in Fig. 7 A, at first, provide Semiconductor substrate 700, described Semiconductor substrate 700 comprises redundant metal area 702, the redundant metal area 703 of auxiliary pattern and nonredundancy metal area 701.
Shown in Fig. 7 B, form dielectric layer 710 in described Semiconductor substrate 700.
Shown in Fig. 7 C, the dielectric layer on the described nonredundancy metal area 701 of attenuate.
Shown in Fig. 7 D, form autoregistration hard mask layer 730 at described dielectric layer 710.
Shown in Fig. 7 E, the described autoregistration hard mask layer of etching 730 form hard mask metallic channel 730a and remove described redundant metal area 702 and the redundant metal area 703 of auxiliary pattern on the autoregistration hard mask layer, described hard mask metallic channel 730a can play self aligned effect in subsequent step.
Shown in Fig. 7 F, the dielectric layer on the described nonredundancy metal area 701 of etching forms through hole 711b with the correspondence position at described hard mask metallic channel 730a.
Shown in Fig. 7 G, the described dielectric layer of etching is to form redundant metallic channel 712a, the redundant metallic channel 713a of auxiliary pattern and metallic channel 711a, the degree of depth of the redundant metallic channel 713a of described auxiliary pattern is identical with the degree of depth of described redundant metallic channel 712a, and the degree of depth of the redundant metallic channel 713a of described auxiliary pattern and redundant metallic channel 712a is less than the degree of depth of described metallic channel 711a.
Shown in Fig. 7 H, depositing metal layers 720 in described redundant metallic channel 712a, the redundant metallic channel 713a of auxiliary pattern and metallic channel 711a and on the dielectric layer.
Shown in Fig. 7 I, carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire 722, the redundant metal wire 723 of auxiliary pattern and plain conductor 721, the height of the redundant metal wire 723 of described auxiliary pattern is identical with the height of described redundant metal wire 722, and the height of described redundant metal wire 722 is less than the height of described plain conductor 721.
Compare with above-described embodiment, present embodiment has formed autoregistration hard mask layer 730, and the hard mask metallic channel 730a of described autoregistration hard mask layer 730 formation of etching, described hard mask metallic channel 730a has played self aligned effect, can control dimension of picture more accurately.And the height of the redundant metal wire 723 of auxiliary pattern and redundant metal wire 722 is all less than the height of plain conductor 721, reduced the height (thickness) of the redundant metal wire 723 of redundant metal wire 722 and auxiliary pattern, fill in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduce the redundant metal wire of redundant metal wire and auxiliary pattern effectively, and enlarged lithographic process window.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses is difference with other embodiment, the reference mutually of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for purpose convenient, each embodiment of aid illustration the present invention lucidly.
In addition, although abovely describe the present invention in detail with a plurality of embodiment respectively, those skilled in the art can also carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
Form dielectric layer in described Semiconductor substrate;
Dielectric layer on the described nonredundancy metal area of attenuate;
The described dielectric layer of etching is to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
2. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, before described Semiconductor substrate forms dielectric layer, also comprises: form etching stop layer in described Semiconductor substrate.
3. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
Form dielectric layer and hard mask layer in described Semiconductor substrate;
Remove the hard mask layer on described redundant metal area and the nonredundancy metal area;
Dielectric layer on the described nonredundancy metal area of attenuate and the redundant metal area makes on the described redundant metal area remaining thickness of dielectric layers greater than remaining thickness of dielectric layers on the described nonredundancy metal area;
The described dielectric layer of etching is to form redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel simultaneously, the degree of depth of the redundant metallic channel of described auxiliary pattern is less than the degree of depth of described redundant metallic channel, and the degree of depth of described redundant metallic channel is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described auxiliary pattern is less than the height of described redundant metal wire, and the height of described redundant metal wire is less than the height of described plain conductor.
4. manufacturing method of semiconductor device as claimed in claim 3 is characterized in that, before described Semiconductor substrate forms dielectric layer, also comprises: form etching stop layer in described Semiconductor substrate.
5. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
Form dielectric layer in described Semiconductor substrate;
Dielectric layer on the described nonredundancy metal area of attenuate;
Dielectric layer on the described nonredundancy metal area of etching forms through hole;
The described dielectric layer of etching to be forming the redundant metallic channel of redundant metallic channel and auxiliary pattern, and forms metallic channel at described through hole correspondence position, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
6. manufacturing method of semiconductor device as claimed in claim 5 is characterized in that, before described Semiconductor substrate forms dielectric layer, also comprises: form etching stop layer in described Semiconductor substrate.
7. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
On described Semiconductor substrate, form dielectric layer and hard mask layer successively;
Remove the hard mask layer on described redundant metal area and the nonredundancy metal area;
Dielectric layer on the described nonredundancy metal area of attenuate and the redundant metal area, remaining thickness of dielectric layers is greater than remaining thickness of dielectric layers on the described nonredundancy metal area on the described redundant metal area;
Dielectric layer on the described nonredundancy metal area of etching forms through hole;
The described dielectric layer of etching is to form the redundant metallic channel of redundant metallic channel and auxiliary pattern, and at described through hole correspondence position formation metallic channel, the degree of depth of the redundant metallic channel of described auxiliary pattern is less than the degree of depth of described redundant metallic channel, and the degree of depth of described redundant metallic channel is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described auxiliary pattern is less than the height of described redundant metal wire, and the height of described redundant metal wire is less than the height of described plain conductor.
8. manufacturing method of semiconductor device as claimed in claim 7 is characterized in that, before described Semiconductor substrate forms dielectric layer, also comprises: form etching stop layer in described Semiconductor substrate.
9. manufacturing method of semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundant metal area, the redundant metal area of auxiliary pattern and nonredundancy metal area;
Form dielectric layer in described Semiconductor substrate;
Dielectric layer on the described nonredundancy metal area of attenuate;
Form the autoregistration hard mask layer at described dielectric layer;
The described autoregistration hard mask layer of etching form hard mask metallic channel and remove described redundant metal area and the redundant metal area of auxiliary pattern on the autoregistration hard mask layer;
Dielectric layer on the described nonredundancy metal area of etching forms through hole with the position at described hard mask metallic channel;
The described dielectric layer of etching to be forming the redundant metallic channel of redundant metallic channel and auxiliary pattern, and forms metallic channel at described through hole correspondence position, and the degree of depth of the redundant metallic channel of described redundant metallic channel and auxiliary pattern is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundant metallic channel, the redundant metallic channel of auxiliary pattern and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until the surface that exposes described dielectric layer, to form redundant metal wire, the redundant metal wire of auxiliary pattern and plain conductor, the height of the redundant metal wire of described redundant metal wire and auxiliary pattern is less than the height of described plain conductor.
10. manufacturing method of semiconductor device as claimed in claim 9 is characterized in that, before described Semiconductor substrate forms dielectric layer, also comprises: form etching stop layer in described Semiconductor substrate.
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| CN111564422A (en) * | 2020-04-08 | 2020-08-21 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof, semiconductor device and chip |
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| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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| CN101231667A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of filling redundancy for semiconductor manufacturing process and semiconductor device |
| CN102130043A (en) * | 2010-12-30 | 2011-07-20 | 中国科学院微电子研究所 | Method for filling redundancy metal |
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