CN102339791A - Manufacture method of semiconductor device - Google Patents
Manufacture method of semiconductor device Download PDFInfo
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- CN102339791A CN102339791A CN2011103353815A CN201110335381A CN102339791A CN 102339791 A CN102339791 A CN 102339791A CN 2011103353815 A CN2011103353815 A CN 2011103353815A CN 201110335381 A CN201110335381 A CN 201110335381A CN 102339791 A CN102339791 A CN 102339791A
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Abstract
The invention discloses a manufacture method of a semiconductor device, which leads the depth of a redundant metal groove to be less than that of a metal conductor groove, so that the height of a finally formed redundant metal wire is less than the thickness of a metal conductor. In comparison with the prior art, the thickness of the redundant metal wire is reduced, and the coupling capacitance in a metal layer and among metal layers filled and introduced by the redundant metal wire is reduced.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of manufacturing method of semiconductor device.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper interconnecting line substitution of Al interconnection line gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain through etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes the dual damascene process of through hole (also claiming contact hole) and plain conductor simultaneously.Specifically; Single damascene structure (also claiming single inlay structure) only is to change the production method of single-layer metal lead into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layers fills); Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together.
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, dielectric layer 110 at first on Semiconductor substrate 100; In dielectric layer 110, form metallic channel through photoetching and etching technics then; Depositing metal layers subsequently, said metal level are filled in the metallic channel and on said dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technology and remove the metal on the said dielectric layer 110, thereby in said metallic channel, processed plain conductor 140.
As stated, in Damascus technics, need utilize chemical mechanical milling tech, be embedded in the plain conductor 140 in the dielectric layer 110 with final formation.Yet,, therefore can cause the depression of not expecting (dishing) and corrode (erosion) phenomenon the selectivity of grinding because the rate that removes of metal and dielectric layer material is generally inequality.Depression occurs in metal often and goes down to the plane of adjacent dielectric layers or exceed more than the plane of adjacent dielectric layers, and corroding then is that the part of dielectric layer is thin excessively.Depression and erosion are subject to the structure of figure and the density influence of figure.In order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, the method for solution is to fill the pattern density homogenizing that redundant metal line pattern makes domain at the white space of domain, thereby also forms redundant metal wire (dummy metal) 150 when in dielectric layer 110, forming plain conductor 140, and is as shown in Figure 2.But,, but introduced in the extra metal level inevitably and the coupling capacitance of metal interlevel though redundant metal wire has improved the uniformity of pattern density.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor device, fills in the metal level of introducing and the coupling capacitance of metal interlevel to reduce redundant metal wire.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing method of semiconductor device, comprising:
Dielectric layer, dielectric protection layer and metal hard mask layer successively on Semiconductor substrate;
On said metal hard mask layer, form the first patterning photoresist layer;
With the said first patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the original metal metallic channel;
Remove the said first patterning photoresist layer;
On said metal hard mask layer, form the second patterning photoresist layer;
With the said second patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the initial redundancy metallic channel, and the degree of depth of said initial redundancy metallic channel is less than the degree of depth of said original metal metallic channel;
Remove the said second patterning photoresist layer;
On said metal hard mask layer, form the 3rd patterning photoresist layer;
With said the 3rd patterning photoresist layer is mask, and the dielectric protection layer of the said original metal metallic channel of dry etching below and the dielectric layer of segment thickness form initial access hole;
Remove said the 3rd patterning photoresist layer;
Said dielectric protection layer of dry etching and dielectric layer form metallic channel, redundant metallic channel and through hole, and said through hole and said metallic channel are communicated with and expose the surface of said Semiconductor substrate;
On metal hard mask layer and in metallic channel, redundant metallic channel and the through hole, form copper metal layer;
Carry out chemical mechanical milling tech, until the surface that exposes said dielectric layer, in said metallic channel and through hole, forming plain conductor, and in said redundant metallic channel the redundant metal wire of formation.
Optional, in described manufacturing method of semiconductor device, the material of said metal hard mask layer is one or more in titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
Optional, in described manufacturing method of semiconductor device, the thickness of said metal hard mask layer is 1 nanometer～1000 nanometers.
Optional, in described manufacturing method of semiconductor device, form the original metal metallic channel earlier, and then form the initial redundancy metallic channel.
Optional, in described manufacturing method of semiconductor device, form the initial redundancy metallic channel earlier, and then form the original metal metallic channel.
Optional, in described manufacturing method of semiconductor device, before dielectric layer on the said Semiconductor substrate, deposition-etch barrier layer on said Semiconductor substrate.
The present invention makes the degree of depth of the degree of depth of redundant metallic channel less than metallic channel; Therefore the height of the final redundant metal wire that forms is less than the thickness (highly) of plain conductor; Compared with prior art reduced the thickness of redundant metal wire, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduced redundant metal wire.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 is the schematic flow sheet of the manufacturing method of semiconductor device of one embodiment of the invention;
Fig. 4 A～4M is the cross-sectional view of the corresponding device of each step in the manufacturing method of semiconductor device of one embodiment of the invention.
Embodiment
Mention that in background technology though redundant metal has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, capacitor C can be calculated by formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the dielectric dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows that the relative area that reduces metal can reduce electric capacity with increase intermetallic distance.That is to say that the volume that reduces redundant metal can reduce owing to adding the extra intermetallic coupling capacitance that redundant metal is introduced.For this reason, the present invention makes the degree of depth of the degree of depth of redundant metallic channel less than metallic channel, has compared with prior art reduced the thickness (highly) of redundant metal, thereby reduces in the metal level of redundant metal filled introducing the coupling capacitance with metal interlevel effectively.
Cross-sectional view below in conjunction with the corresponding device of each step in the schematic flow sheet of manufacturing method of semiconductor device shown in Figure 3 and the manufacturing method of semiconductor device shown in Fig. 4 A～4M is explained in detail the above-mentioned semiconductor device manufacture method.
Step S300: dielectric layer, dielectric protection layer and metal hard mask layer successively on Semiconductor substrate.
Shown in Fig. 4 A, dielectric layer 410, dielectric protection layer 411 and metal hard mask layer 412 successively on Semiconductor substrate 400.Be formed with metal line (not shown) in the said Semiconductor substrate 400; Because the present invention relates generally to the manufacture craft of metal damascene structure; So the process in Semiconductor substrate 400, forming metal line will not be introduced, but those skilled in the art are still this and know.
The material of said dielectric layer 410 is preferably low-k (Low-K) dielectric layer, postpones with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfies the requirement of conduction fast.Preferable; It is black diamond (black diamond that said dielectric layer 410 adopts the trade mark of Material Used (Applied Materials) company; BD) silicon oxide carbide; Perhaps adopt the Coral material of Novellus company, perhaps adopt again and utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.The material of said dielectric protection layer 411 is preferably silica.The material of said metal hard mask layer 412 is preferably one or more in titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide, and the thickness of said metal hard mask layer 412 is preferably between 1 nanometer to 1000 nanometer.
In other embodiments of the invention; Before forming dielectric layer 410 on the said Semiconductor substrate 400; Also can form etching barrier layer 401 earlier; Said etching barrier layer 401 can be used for preventing metal diffusing in the metal line in dielectric layer 410, and said in addition etching barrier layer 401 can prevent that also the metal line in the Semiconductor substrate 400 is etched in follow-up etching process of carrying out.The material of said etching barrier layer 401 for example is silicon nitride or carbonitride of silicium (SiCN), and the dielectric layer 410 of itself and follow-up formation has good adhesive force property.
Step S301: on said metal hard mask layer, form the first patterning photoresist layer.
Shown in Fig. 4 B, utilize the mode of spin coating on said metal hard mask layer 412, to form the first patterning photoresist layer 421, the said first patterning photoresist layer 421 has the metallic channel pattern.
Step S302: with the first patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the original metal metallic channel.
Shown in Fig. 4 C, be mask with the first patterning photoresist layer 421, the dielectric protection layer 411 of said metal hard mask layer 412 of dry etching and segment thickness forms original metal metallic channel 420a.
Step S303: remove the said first patterning photoresist layer.
Shown in Fig. 4 D, the mode of plasma ashing capable of using or wet method is removed the said first patterning photoresist layer 421.
Step S304: on said metal hard mask layer, form the second patterning photoresist layer.
Shown in Fig. 4 E, utilize the mode of spin coating on metal hard mask layer 412, to form the second patterning photoresist layer 422, the said second patterning photoresist layer 422 has redundant metallic channel pattern.
Step S305: with the second patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the initial redundancy metallic channel, and the degree of depth of said initial redundancy metallic channel is less than the degree of depth of said original metal metallic channel.
Shown in Fig. 4 F; With the second patterning photoresist layer 422 is mask; The dielectric protection layer 411 of said metal hard mask layer 412 of dry etching and segment thickness; Form initial redundancy metallic channel 420b, the degree of depth of said initial redundancy metallic channel 420b is less than the degree of depth of said original metal metallic channel 420a.
Step S306: remove the said second patterning photoresist layer.
Shown in Fig. 4 G, the mode of plasma ashing capable of using or wet method is removed the said second patterning photoresist layer 422.
Step S307: on said metal hard mask layer, form the 3rd patterning photoresist layer.
Shown in Fig. 4 H, utilize the mode of spin coating on metal hard mask layer 412, to form the 3rd patterning photoresist layer 423, said the 3rd patterning photoresist layer 423 has through-hole pattern.
Step S308: with said the 3rd patterning photoresist layer is mask, and the dielectric protection layer of the said metallic channel of dry etching below and the dielectric layer of segment thickness form initial access hole.
Shown in Fig. 4 I, be mask with said the 3rd patterning photoresist layer 423, the dielectric protection layer 411 of the said original metal metallic channel of dry etching 420a below and the dielectric layer 410 of segment thickness are to form initial access hole 420c below metallic channel 420a.
Step S309: remove said the 3rd patterning photoresist layer.
Shown in Fig. 4 J, the mode of plasma ashing capable of using or wet method is removed said the 3rd patterning photoresist layer 423.
Step S310: said dielectric protection layer of dry etching and dielectric layer, form metallic channel, redundant metallic channel and through hole, said through hole and said metallic channel are communicated with and expose the surface of said Semiconductor substrate.
Shown in Fig. 4 K; Said dielectric protection layer 411 of dry etching and dielectric layer 410; Form metallic channel 420a ', redundant metallic channel 420b ' and through hole 420c ', said through hole 420c ' and said metallic channel 420a ' are communicated with and expose the surface of said Semiconductor substrate 400.
Step S311: on said metal hard mask layer and in metallic channel, redundant metallic channel and the through hole, form copper metal layer.
Shown in Fig. 4 L; Form copper metal layer 430 on metal hard mask layer 412 and in metallic channel 420a ', redundant metallic channel 420b ' and the through hole 420c '; Can first depositing metal barrier layer (not shown) before forming said copper metal layer 430; The material of said metal barrier for example is tantalum nitride or carbon, and then the cement copper inculating crystal layer, afterwards re-plating copper.
Step S312: carry out chemical mechanical milling tech, until the surface that exposes said dielectric layer, in said metallic channel and through hole, forming plain conductor, and in redundant metallic channel the redundant metal wire of formation.
Shown in Fig. 4 M; At last; Carry out chemical mechanical milling tech until the surface that exposes dielectric layer 410; Thereby in metallic channel 420a ' and through hole 420c ', form plain conductor 431, and in redundant metallic channel 420b ', form redundant metal wire 432, because the degree of depth of the redundant metallic channel 420b ' that abovementioned steps forms is less than the degree of depth of metallic channel 420a '; Therefore compared with prior art reduced the thickness of redundant metal wire, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduced redundant metal wire.
Need to prove; Above-mentioned is to be that example has been introduced the present invention in detail to form earlier original metal metallic channel 420a and then to form initial redundancy metallic channel 420b, yet will be appreciated that, in other specific embodiment; Also can form initial redundancy metallic channel 420b earlier; And then form original metal metallic channel 420a, only need first execution in step S304, S305 and S306, and then execution in step S301, S302 and S303 get final product.
In addition, those skilled in the art can also carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. a manufacturing method of semiconductor device is characterized in that, comprising:
Dielectric layer, dielectric protection layer and metal hard mask layer successively on Semiconductor substrate;
On said metal hard mask layer, form the first patterning photoresist layer;
With the said first patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the original metal metallic channel;
Remove the said first patterning photoresist layer;
On said metal hard mask layer, form the second patterning photoresist layer;
With the said second patterning photoresist layer is mask, and the dielectric protection layer of said metal hard mask layer of dry etching and segment thickness forms the initial redundancy metallic channel, and the degree of depth of said initial redundancy metallic channel is less than the degree of depth of said original metal metallic channel;
Remove the said second patterning photoresist layer;
On said metal hard mask layer, form the 3rd patterning photoresist layer;
With said the 3rd patterning photoresist layer is mask, and the dielectric protection layer of the said original metal metallic channel of dry etching below and the dielectric layer of segment thickness form initial access hole;
Remove said the 3rd patterning photoresist layer;
Said dielectric protection layer of dry etching and dielectric layer form metallic channel, redundant metallic channel and through hole, and said through hole and said metallic channel are communicated with and expose the surface of said Semiconductor substrate;
On metal hard mask layer and in metallic channel, redundant metallic channel and the through hole, form copper metal layer;
Carry out chemical mechanical milling tech, until the surface that exposes said dielectric layer, in said metallic channel and through hole, forming plain conductor, and in said redundant metallic channel the redundant metal wire of formation.
2. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the material of said metal hard mask layer is one or more in titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
3. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the thickness of said metal hard mask layer is 1 nanometer～1000 nanometers.
4. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, forms the original metal metallic channel earlier, and then forms the initial redundancy metallic channel.
5. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, forms the initial redundancy metallic channel earlier, and then forms the original metal metallic channel.
6. like any described manufacturing method of semiconductor device in the claim 1 to 5, it is characterized in that, before dielectric layer on the said Semiconductor substrate, deposition-etch barrier layer on said Semiconductor substrate.
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| CN 201110335381 CN102339791B (en) | 2011-10-29 | 2011-10-29 | Manufacture method of semiconductor device |
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| CN 201110335381 CN102339791B (en) | 2011-10-29 | 2011-10-29 | Manufacture method of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826333A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN108959800A (en) * | 2018-07-20 | 2018-12-07 | 上海华虹宏力半导体制造有限公司 | The fill method of redundancy metal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040089924A1 (en) * | 2002-10-25 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method for fabricating the same |
| US20100178771A1 (en) * | 2009-01-09 | 2010-07-15 | Samsung Electronics Co., Ltd. | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040089924A1 (en) * | 2002-10-25 | 2004-05-13 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method for fabricating the same |
| US20100178771A1 (en) * | 2009-01-09 | 2010-07-15 | Samsung Electronics Co., Ltd. | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105826333A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105826333B (en) * | 2015-01-09 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN108959800A (en) * | 2018-07-20 | 2018-12-07 | 上海华虹宏力半导体制造有限公司 | The fill method of redundancy metal |
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