CN105826333A - Method for forming semiconductor structure - Google Patents
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- CN105826333A CN105826333A CN201510012082.6A CN201510012082A CN105826333A CN 105826333 A CN105826333 A CN 105826333A CN 201510012082 A CN201510012082 A CN 201510012082A CN 105826333 A CN105826333 A CN 105826333A
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Abstract
The present invention provides a method for forming a semiconductor structure. The method comprises a step of providing a substrate, a step of orderly forming a buffer layer, a first insulating layer and a hard mask layer on the substrate, a step of etching the first insulating layer, the buffer layer and the substrate with the hard mask layer as a mask, and forming grooves in the substrate, the buffer layer, the first insulating layer and the hard mask layer, a step of filling an electrode material layer in the grooves to cover the surface of the hard mask layer, a step of carrying out chemical mechanical polishing on the electrode material layer and hard mask layer, removing the electrode material layer on the hard mask layer, and forming an electrode layer in the remaining electrode material layer in the grooves. According to the method, firstly the grooves are filled with the electrode material layer, and then the chemical mechanical polishing of the electrode material layer and the hard mask layer are carried out. The buffer layer is not affected substantially by the chemical mechanical polishing. After the electrode layer is formed, the good shape of the buffer layer is maintained, and thus the semiconductor capacitor formed by the invention has good performance.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to the forming method of a kind of semiconductor structure.
Background technology
Cmos image sensor is the most common semiconductor transducer, is widely used in the fields such as mobile phone, panel computer, fingerprint recognition.3DIC fabrication techniques cmos image sensor is used to have become as the focus of this area research.Use 3DIC fabrication techniques cmos image sensor, need to form semiconductor capacitor in bottom wafers.The generally battery lead plate of semiconductor capacitor is both formed in the deep trench in substrate.
Refer to Fig. 1 and Fig. 2, be the schematic diagram of prior art a kind of semiconductor capacitor manufacture method.With reference first to Fig. 1, wherein substrate 01 is the active substrates after overdoping, is formed with cushion 02, insulating barrier 03 and hard mask layer 04 on substrate 01.Described insulating barrier 03 is for protecting the battery lead plate in substrate 01 and substrate 01; and make the battery lead plate in substrate 01 and substrate 01 and the device isolation on substrate 01; described cushion 02 is for the associativity between reinforced insulation layer 03 and substrate 01; with described hard mask layer 04 as mask; etch described insulating barrier 03, cushion 02 and substrate 01, described insulating barrier 03, cushion 02 and substrate 01 are formed groove 05.Described groove is used for filling electrode material, to form battery lead plate.
With reference to Fig. 2, after forming groove 05, needing to remove described hard mask layer 04, usual described hard mask layer 04 and described cushion 02 are silica material and constitute.As in figure 2 it is shown, prior art commonly uses wet etching removes hard mask layer 04, to guarantee that the hard mask layer 04 at the uneven place of insulating barrier 03 upper surface is removed clean.But during removing hard mask layer 04, described groove 05 exposes the sidewall of cushion 02, and described cushion 02 is the most easily etched so that the sidewall of groove 05 forms the breach as shown in circle.After forming electrode layer in described groove 05, described breach also form electrode layer, electrode layer is made to produce rough defect at gap position, the capacitance between battery lead plate may be affected, even cause the open circuit of battery lead plate, it is likely to reduce the associativity between substrate 01 and insulating barrier 03 simultaneously, makes semiconductor capacitor produce defect.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, improves the pattern of cushion in semiconductor capacitor, and then improves the performance of semiconductor capacitor.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including:
Substrate is provided；
Sequentially form cushion, the first insulating barrier and hard mask layer over the substrate；
With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, described substrate, cushion, the first insulating barrier and hard mask layer are formed groove；
Electrode material layer is filled, to covering described hard mask layer surface in described groove；
Described electrode material layer and hard mask layer carrying out cmp, removes the electrode material layer on hard mask layer, remaining electrode material layer in the grooves is used for forming electrode layer.
Optionally, the step at described cmp includes: use KOH or NH4OH is as lapping liquid.
Optionally, in the step of described cmp, the rotating speed of grinding head is more than 60 rpms.
Optionally, cmp also removes the hard mask layer of segment thickness, and described forming method the most also includes at cmp: remove remaining hard mask layer by dry etching.
Optionally, described semiconductor structure is used for forming capacitor, after providing substrate, before forming cushion over the substrate, is doped described substrate, makes the subregion of described substrate form doped region；
Being formed in described substrate, cushion, the first insulating barrier and hard mask layer in the step of groove, described groove is positioned in the doped region of described substrate.
Optionally, described first insulating barrier is formed in the step of hard mask layer, described hard mask layer is formed the opening exposing the first insulating barrier；
With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, formed in described substrate, cushion, the first insulating barrier and hard mask layer in the step of groove, etch the first insulating barrier, cushion and substrate that described opening exposes.
Optionally, after forming groove in described substrate, cushion, the first insulating barrier and hard mask layer, before filling electrode material layer in described groove, described forming method also includes:
Described groove inner surface and described hard mask layer form the second insulating barrier；
The step filling electrode material layer in described groove includes: fill electrode material layer in the groove being formed with the second insulating barrier.
Optionally, described second insulating barrier includes: the silicon oxide layer sequentially formed and silicon nitride layer.
Optionally, the material of described cushion is silicon oxide.
Optionally, the thickness of described cushion is in the range of 25 to 150 angstroms.
Optionally, the material of described hard mask layer is silicon oxide.
Optionally, the thickness of described hard mask layer is in the range of 7000 to 17000 angstroms.
Optionally, the material of described electrode layer is polysilicon.
Optionally, the degree of depth of described groove is in the range of 5.7 microns to 9 microns.
Optionally, etching described first insulating barrier, cushion and substrate, to be formed in the step of groove, the method etching described first insulating barrier, cushion and substrate is dry etch process.
Compared with prior art, technical scheme has the advantage that the present invention sequentially forms cushion, the first insulating barrier and hard mask layer over the substrate；With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, in described substrate, cushion, the first insulating barrier and hard mask layer, form groove, after described groove fills electrode material layer, described hard mask layer and electrode material layer are carried out cmp.During cmp, the first insulating barrier is had as stop between cushion and described hard mask layer, the top of cushion and sidewall are respectively under the covering of the first insulating barrier and electrode material layer, and cmp impacts substantially without to described cushion.After forming described electrode layer, cushion still keeps preferable pattern, and therefore, the associativity between substrate and the first insulating barrier is preferable, and described electrode layer will not produce rough defect near cushion, the semiconductor capacitor that this sample embodiment is formed has preferable performance.
Accompanying drawing explanation
Fig. 1 to Fig. 2 is the schematic diagram of prior art a kind of semiconductor capacitor manufacture method；
Fig. 3 to Figure 11 is the schematic diagram of forming method one embodiment of semiconductor structure of the present invention.
Detailed description of the invention
In prior art semiconductor capacitor manufacture method, the step removing hard mask layer easily damages cushion, reduces the performance of semiconductor capacitor.
In order to solve above-mentioned technical problem, the present invention proposes the forming method of a kind of semiconductor structure, including: substrate is provided；Sequentially form cushion, the first insulating barrier and hard mask layer over the substrate；With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, described substrate, cushion, the first insulating barrier and hard mask layer are formed groove；Electrode material layer is filled, to covering described hard mask layer surface in described groove；Described electrode material layer and hard mask layer carrying out cmp, removes the electrode material layer on hard mask layer, remaining electrode material layer in the grooves is used for forming electrode layer.
The present invention first fills electrode material layer in described groove, to covering described hard mask layer surface；Described electrode material layer and hard mask layer are carried out cmp, during described electrode material layer and hard mask layer are carried out cmp, the sidewall of cushion and top are under the covering of electrode material layer and the first insulating barrier, and cmp impacts substantially without to described cushion.After forming described electrode layer, cushion still keeps preferable pattern, therefore, associativity between substrate and the first insulating barrier is preferable, further, described electrode layer will not produce the defect of projection near cushion, and the semiconductor capacitor that this sample embodiment is formed has preferable performance.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
With reference to Fig. 3 to Figure 11, it is shown that the schematic diagram of forming method one embodiment of semiconductor structure.
With reference to Fig. 3, it is provided that substrate 100.
In the present embodiment, described substrate 100 is positioned on wafer, and described substrate 100 is monocrystalline substrate, in other embodiments, described substrate can also be other Semiconductor substrate such as multicrystalline silicon substrate, amorphous silicon substrate, germanium silicon substrate or silicon-on-insulator substrate, and this present invention is not done any restriction.
In the present embodiment, with reference to Fig. 4, after providing substrate 100, multiple fleet plough groove isolation structure 101 is formed in described substrate 100, for substrate 100 being separated into multiple region, then multiple regions of substrate 100 are doped, substrate 100 is formed multiple doped region.It is a doped region between two adjacent fleet plough groove isolation structures 101, as the plate of semiconductor capacitor.But the present invention does not limits whether forming described fleet plough groove isolation structure.
With reference to Fig. 4, described substrate 100 sequentially forms cushion the 102, first insulating barrier 103 and hard mask layer 104.
Described first insulating barrier 103, for being insulated by other semiconductor structures above substrate 100 and the first insulating barrier 103, using guarantee as the doped region of semiconductor capacitor plate, electric leakage is less likely to occur.
Described cushion 102, for strengthening the adhesion between the first insulating barrier 103 and substrate 100, makes other semiconductor structures of the first insulating barrier 103 and top thereof be stably formed on substrate 100.Additionally, the first insulating barrier 103 is generally of bigger stress, between the first insulating barrier 103 and substrate 100, forms cushion 102 can also buffer the stress between described first insulating barrier 103 and substrate 100, to protect substrate 100.
It should be noted that, if the thickness of described cushion 102 is excessive, the thickness of the semiconductor structure then formed also can increase accordingly, if the thickness of described cushion 102 is too small, is then difficult to play at the bottom of reinforcing line the effect of 100 and first adhesions between insulating barrier 103.Therefore, in the present embodiment, the thickness of described cushion 102 is in the range of 25 to 150 angstroms.
Described hard mask layer 104 is used as to etch described first insulating barrier 103, cushion 102 and the mask of substrate 100, the depth of groove formed in described first insulating barrier 103, cushion 102 and substrate 100 is bigger, it is thus desirable to the slower hard mask layer 104 of the etching speed of etching speed counter substrate 100 is as mask, additionally, use hard mask layer 104 can improve the pattern of formed recess sidewall as mask.
If the thickness of described hard mask layer 104 is excessive, the difficulty of follow-up removal hard mask layer 104 is bigger, if the thickness of described hard mask layer 104 is too small, then may be when subsequent etching forms groove, when depth of groove is also not reaching to predetermined value, depleted the carrying out affecting etching process of hard mask layer 104.Therefore, in the present embodiment, the thickness of described hard mask layer 104 is in the range of 7000 to 17000 angstroms.
In the present embodiment, chemical vapour deposition technique is used to form described cushion the 102, first insulating barrier 103 and hard mask layer 104.The material of described cushion 102 is silicon oxide, and the material of described first insulating barrier 103 is silicon nitride, and the material of described hard mask layer 104 is silicon oxide.But the concrete material of described cushion the 102, first insulating barrier 103 and hard mask layer 104 is not limited by the present invention.
In conjunction with reference to Fig. 5, Fig. 6, Fig. 7, with the hard mask layer 104 after described etching as mask, etch described first insulating barrier 103, cushion 102 and substrate 100, described substrate 100, cushion the 102, first insulating barrier 103 and hard mask layer 104 are formed groove 107.
It should be noted that described groove 107 is for forming the electrode layer of semiconductor capacitor, described electrode layer for respectively constituting two electrodes of semiconductor capacitor with the doped region in substrate 100, and the most described groove 107 is formed in the doped region of described substrate 100.
In the present embodiment, with reference first to Fig. 5, described hard mask layer 104 sequentially forms polysilicon layer 105 and photoresist layer 106, described photoresist layer 106 has the figure of respective slot shape.
Described polysilicon layer 105 is used as figure and transfers to the mask layer of hard mask layer 104, it is possible to increase the precision of figure transfer.But the present invention does not limits whether forming described polysilicon layer 105.
With reference to Fig. 6, with described photoresist layer 106 as mask, etch described polysilicon layer 105, the figure of described respective slot shape is transferred on polysilicon layer 105, again with described polysilicon layer 105 as mask, etch described hard mask layer 104, the figure of described respective slot shape is transferred on hard mask layer 104.
In conjunction with reference to Fig. 6, Fig. 7, with described hard mask layer 104 as mask, etch described first insulating barrier 103, cushion 102 and substrate 100, described substrate 100, cushion the 102, first insulating barrier 103 and hard mask layer 104 are formed groove 107.During etching described first insulating barrier 103, cushion 102 and substrate 100, polysilicon layer 105 is etched totally, and hard mask layer 104 is also etched and gets rid of certain thickness.
In the present embodiment, the method etching described first insulating barrier 103, cushion 102 and substrate 100 is dry etch process.
In the present embodiment, the depth H 1 of described groove 107 is in the range of 5.7 microns to 9 microns.But the degree of depth of described groove 107 is not limited by the present invention.It should be noted that the depth H 2 that described groove 107 is in substrate 100 is in the range of 5 microns to 8 microns.
With reference to Fig. 8, described groove 107 inner surface and described hard mask layer 104 form the second insulating barrier 108.
The dielectric layer functioning as semiconductor capacitor of described second insulating barrier 108, it is therefore desirable to the material that dielectric constant is higher is formed.In the present embodiment, described second insulating barrier 108 includes: the silicon oxide layer sequentially formed and silicon nitride layer, such composite bed has higher dielectric constant and preferable insulating properties simultaneously, but the structure of described second insulating barrier 108 is not limited by the present invention, in other embodiments, described second insulating barrier 108 can also be single layer structure, and the most described second insulating barrier 108 is silicon oxide layer or silicon nitride layer.
With reference to Fig. 9, described groove 107 is filled electrode material layer 109, to covering described hard mask layer 104 surface.
In the present embodiment, owing to being also formed with the second insulating barrier 108 on described hard mask layer 104, described electrode material layer 109 covers described second insulating barrier 108 surface.
In the present embodiment, the material of described electrode material layer 109 is polysilicon, but the invention is not limited in this regard, and in other embodiments, the material of described electrode material layer 109 can also be metal.
It should be noted that in the present embodiment, the described electrode material layer 109 thickness on described hard mask layer 104 surface is in the range of 2000 to 3000 angstroms.
In conjunction with reference to Figure 10, Figure 11, described electrode material layer 109 and hard mask layer 104 are carried out cmp, removing the electrode material layer 109 on hard mask layer 104 and the hard mask layer 104 of segment thickness, the remaining electrode material layer 109 being positioned in groove 107 forms electrode layer 110.Described electrode layer 110 is used as the cathode plate of semiconductor capacitor, with two electrodes that the doped region in described substrate 100 is used separately as semiconductor capacitor.
During cmp, cover the electrode material layer 109 on hard mask layer 104 surface and removed described in cmp.The material of the first insulating barrier 103 is silicon nitride, it is difficult to removed by cmp, and therefore the first insulating barrier 103 is used as the stop-layer of cmp.The first insulating barrier 103 is had to stop between cushion 102 and described hard mask layer 104, groove 107 is also filled full electrode material layer 109, therefore the top of cushion 102 and sidewall are respectively under the covering with electrode material layer 109 of described first insulating barrier 103, cmp impacts substantially without to described cushion 102, and the position that cushion 102 contacts with electrode layer 110 also will not produce breach.After forming described electrode layer 110, cushion 102 still keeps preferable pattern.
Specifically, in the present embodiment, the wafer at described substrate 100 place is positioned on grinding plate, the second insulating barrier 108 on electrode material layer 109 on described hard mask layer 104, hard mask layer 104 and hard mask layer 104 is carried out cmp, removes the second insulating barrier 108 on the electrode material layer 109 on described hard mask layer 104, hard mask layer 104 and the hard mask layer 104 of segment thickness.
During cmp, the technological parameter of described cmp includes: the lapping liquid of employing is KOH or NH4OH.The rotating speed of grinding head is more than 60 rpms.But the process conditions of cmp are not limited by the present invention.
It should be noted that in the present embodiment cmp, cmp removes the speed of the second insulating barrier 108 on electrode material layer 109, hard mask layer 104 and hard mask layer 104 in the range of 40～5500 angstroms/min.Wherein, KOH or NH4The hard mask layer 104 of silicon oxide is removed speed by the lapping liquid of OH, the electrode material layer 109 of polysilicon is removed speed slower.And the thickness of hard mask layer 104 is bigger than electrode material layer 109 thickness covered on hard mask layer 104 surface in the present embodiment, therefore, the present embodiment have employed KOH or NH4OH is as lapping liquid, to improve the efficiency of cmp.
In the present embodiment, the process duration of cmp was at 2 to 10 minutes.But the invention is not limited in this regard, in other embodiments, it is also possible to be respectively directed to electrode material layer the 109, second insulating barrier 108 and hard mask layer 104 uses the lapping liquid being suitable for, to accelerate grinding rate.
It should be noted that, due to the more difficult control of the amount of grinding of cmp, therefore in the present embodiment, after cmp removes the hard mask layer 104 of segment thickness, remaining hard mask layer 104, as buffering, is possible to prevent the substrate 100 below cmp damage hard mask layer 104.In the present embodiment, remaining hard mask layer 104 thickness is in the range of 500 to 1000 angstroms.But the present invention is without limitation, in other embodiments, during cmp, described hard mask layer 104 all can be removed.
In conjunction with reference to Figure 11, the surface after described cmp is carried out dry etching, to remove remaining hard mask layer 104.
The remaining hard mask layer 104 as buffering is removed totally by described dry etching, and will be located in the segment electrode layer 110 on the first insulating barrier 103 and the second insulating barrier 108 is removed.
To sum up, in the present embodiment, after filling electrode material layer 109 in described groove 107, the electrode material layer 109 on hard mask layer 104 and the electrode material layer 109 of segment thickness are removed by the method for cmp.During cmp, having the first insulating barrier 103 to stop between cushion 102 and described hard mask layer 104, the sidewall of cushion 102 is also covered by electrode material layer 109, and cmp impacts substantially without to described cushion 102.During dry etching removes remaining hard mask layer 104, the sidewall of cushion 102 is covered by electrode layer 110, described cushion 102 also will not be affected by dry etching, after forming described electrode layer 110, cushion 102 still keeps preferable pattern, will not produce breach in the part contacted with electrode layer 110.So, the forming method of the present embodiment semiconductor structure avoids in prior art, and owing to groove exposes the sidewall of cushion, wet etching is removed hard mask layer and caused cushion to damage.Therefore, associativity between substrate 100 and the first insulating barrier 103 is preferable, and, described electrode layer 110 will not produce rough defect near cushion 102, not interfering with the capacitance of semiconductor capacitor, the semiconductor capacitor that this sample embodiment is formed has preferable performance.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. the forming method of a semiconductor structure, it is characterised in that including:
Substrate is provided；
Sequentially form cushion, the first insulating barrier and hard mask layer over the substrate；
With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, described substrate, cushion, the first insulating barrier and hard mask layer are formed groove；
Electrode material layer is filled, to covering described hard mask layer surface in described groove；
Described electrode material layer and hard mask layer carrying out cmp, removes the electrode material layer on hard mask layer, remaining electrode material layer in the grooves is used for forming electrode layer.
2. forming method as claimed in claim 1, it is characterised in that the step at described cmp includes: use KOH or NH4OH is as lapping liquid.
3. forming method as claimed in claim 1, it is characterised in that in the step of described cmp, the rotating speed of grinding head is more than 60 rpms.
4. forming method as claimed in claim 1, it is characterised in that cmp also removes the hard mask layer of segment thickness, and described forming method the most also includes at cmp: remove remaining hard mask layer by dry etching.
5. forming method as claimed in claim 1, it is characterised in that described semiconductor structure is used for forming capacitor, after providing substrate, before forming cushion over the substrate, is doped described substrate, makes the subregion of described substrate form doped region；
Being formed in described substrate, cushion, the first insulating barrier and hard mask layer in the step of groove, described groove is positioned in the doped region of described substrate.
6. forming method as claimed in claim 1, it is characterised in that formed in the step of hard mask layer on described first insulating barrier, forms the opening exposing the first insulating barrier in described hard mask layer；
With described hard mask layer as mask, etch described first insulating barrier, cushion and substrate, formed in described substrate, cushion, the first insulating barrier and hard mask layer in the step of groove, etch the first insulating barrier, cushion and substrate that described opening exposes.
7. forming method as claimed in claim 1, it is characterised in that after forming groove in described substrate, cushion, the first insulating barrier and hard mask layer, before filling electrode material layer in described groove, described forming method also includes:
Described groove inner surface and described hard mask layer form the second insulating barrier；
The step filling electrode material layer in described groove includes: fill electrode material layer in the groove being formed with the second insulating barrier.
8. the forming method stated such as claim 7, it is characterised in that described second insulating barrier includes: the silicon oxide layer sequentially formed and silicon nitride layer.
9. forming method as claimed in claim 1, it is characterised in that the material of described cushion is silicon oxide.
10. forming method as claimed in claim 1, it is characterised in that the thickness of described cushion is in the range of 25 to 150 angstroms.
11. forming methods as claimed in claim 1, it is characterised in that the material of described hard mask layer is silicon oxide.
12. forming methods as claimed in claim 1, it is characterised in that the thickness of described hard mask layer is in the range of 7000 to 17000 angstroms.
13. forming methods as claimed in claim 1, it is characterised in that the material of described electrode layer is polysilicon.
14. forming methods as claimed in claim 1, it is characterised in that the degree of depth of described groove is in the range of 5.7 microns to 9 microns.
15. forming methods as claimed in claim 1, it is characterised in that etch described first insulating barrier, cushion and substrate, to be formed in the step of groove, the method etching described first insulating barrier, cushion and substrate is dry etch process.
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| CN201510012082.6A CN105826333B (en) | 2015-01-09 | 2015-01-09 | The forming method of semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108121933A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
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| KR20050052878A (en) * | 2003-12-01 | 2005-06-07 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| CN102339791A (en) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
| CN102903669A (en) * | 2011-04-21 | 2013-01-30 | 新加坡商格罗方德半导体私人有限公司 | Scheme for planarizing through-silicon vias |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050052878A (en) * | 2003-12-01 | 2005-06-07 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| CN102903669A (en) * | 2011-04-21 | 2013-01-30 | 新加坡商格罗方德半导体私人有限公司 | Scheme for planarizing through-silicon vias |
| CN102339791A (en) * | 2011-10-29 | 2012-02-01 | 上海华力微电子有限公司 | Manufacture method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108121933A (en) * | 2016-11-28 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
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