CN104078346A - Planarization method for semi-conductor device - Google Patents
Planarization method for semi-conductor device Download PDFInfo
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- CN104078346A CN104078346A CN201410352940.7A CN201410352940A CN104078346A CN 104078346 A CN104078346 A CN 104078346A CN 201410352940 A CN201410352940 A CN 201410352940A CN 104078346 A CN104078346 A CN 104078346A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
Abstract
The invention provides a planarization method for a semi-conductor device. The planarization method for the semi-conductor device comprises the following steps: a groove is internally formed in a liner and a semi-conductor material layer is internally formed in the groove, so as to enable the semi-conductor material layer to fill the groove and to cover on the liner; a first blocking layer is formed in the surface of the semi-conductor material layer inside the groove; thereafter, the first blocking layer serves as a stop layer; through the first planarization process, the semi-conductor material layer on the liner is removed and the first blocking layer is removed; after the semi-conductor material layer is internally formed in the groove, the first blocking layer is formed in the surface of the semi-conductor material layer inside the groove; when the first planarization process is adopted to remove the semi-conductor material layer on the semiconductor liner, the first blocking layer can effectively protect the semi-conductor material layer positioned inside the groove and avoid damages to the semi-conductor material layer positioned inside the groove; therefore, after the first blocking layer is removed, the flatness of the exposed semi-conductor material layer positioned inside the semi-conductor groove is ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of flattening method of semiconductor device.
Background technology
Along with the development of ic manufacturing technology, the integrated level of integrated circuit constantly increases, and the characteristic size of integrated circuit also constantly reduces, and in integrated circuit preparation technology, also strict all the more to the required precision of each electric elements.
The flatening process of preparing at semiconductor device is (as chemical mechanical milling tech, Chemical Mechanical Polishing, CMP) in, removing unnecessary semiconductor device material layer simultaneously, also need to guarantee the evenness of the semiconductor device surface after flatening process, to guarantee the precision of the semiconductor device forming.
Fig. 1, to the schematic diagram that Figure 3 shows that existing semiconductor device flatening process, comprising:
On substrate 10, form barrier layer 11, substrate 10 forms groove 12 described in etching; Afterwards, form the semiconductor material layer 13 of filling groove 12 on the surface of substrate 10, and adopt flatening process, taking described barrier layer 11 as stop-layer, remove the semiconductor material layer 13 of the described substrate 10 unnecessary thickness in top, to exposing described barrier layer 11, thereby at the semiconductor material layer 14 of the interior formation surfacing of groove 12.
But, continue with reference to shown in figure 3, after actual flatening process, in groove 12, semiconductor material layer 14 (as the polysilicon layer) surface of meeting after planarization forms the depression (dishing) 141 of camber line.Especially in the groove that opening is larger, large-area semiconductor material layer depression in the surface 141 phenomenons of formation are especially serious, and then seriously reduced the evenness of semiconductor material layer in groove.Described defect can affect the performance of the semiconductor device of follow-up formation.
, how to improve in semiconductor device fabrication processes, the surface smoothness of the semiconductor material layer after planarization is the problem that those skilled in the art need solution badly for this reason.
Summary of the invention
The problem that the present invention solves is to provide a kind of flattening method of semiconductor device, effectively improves the surface smoothness after planarization, to improve the performance of semiconductor device.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising:
Substrate is provided;
In described substrate, form groove;
Form semiconductor material layer, make described semiconductor material layer fill described groove and be covered on described substrate;
Semiconductor material layer surface in described groove forms the first barrier layer;
Using described the first barrier layer as stop-layer, remove the semiconductor material layer on substrate by the first flatening process;
Remove described the first barrier layer.
Alternatively, the step on the surface of the semiconductor material layer on described groove formation the first barrier layer comprises:
Semiconductor material layer surface on described substrate forms barrier material layer, and described barrier material layer covers described semiconductor material layer;
Removal is positioned at the barrier material layer on the semiconductor material layer surface on described substrate, using the barrier material layer that remaines in the semiconductor material layer surface in described groove as described the first barrier layer.
Alternatively, removing the step of barrier material layer that is positioned at the semiconductor material layer surface on described substrate comprises:
Adopt the second flatening process to remove the barrier material layer on the semiconductor material layer surface on described substrate, barrier material layer in described the second flatening process and the removal speed ratio of semiconductor material layer, be greater than the first barrier layer in the first flatening process and the removal speed ratio of semiconductor material layer.
Alternatively, the removal speed of described the first flatening process to described semiconductor material layer and the removal speed ratio on described the first barrier layer are more than or equal to 10.
Alternatively, described the first flatening process and the second flatening process are chemical mechanical milling tech; And the grinding pad hardness adopting in described the first flatening process is less than the grinding pad hardness adopting in described the second flatening process.
Alternatively, the thickness on described the first barrier layer is more than or equal to 100 dusts.
Alternatively, the formation technique on described the first barrier layer is chemical vapor deposition method.
Alternatively, the material on described the first barrier layer is silica or silicon nitride, and the material of described semiconductor material layer is polysilicon.
Alternatively, the step of removing described the first barrier layer comprises: adopt wet etching to remove described the first barrier layer;
If the material on described the first barrier layer is silica, the etching agent of described wet-etching technology is the hydrofluoric acid solution of dilution;
If the material on described the first barrier layer is silicon nitride, the etching agent of described wet-etching technology is phosphoric acid solution.
Alternatively, in described substrate, form before groove, the flattening method of described semiconductor device also comprises:
On described substrate, form the second barrier layer;
The step that forms groove in described substrate comprises:
The second barrier layer and described substrate described in etching form described groove in described substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
In substrate, form groove, and form semiconductor material layer in described groove, make described semiconductor material layer fill described groove and be covered on described substrate; Semiconductor material layer surface in described groove forms the first barrier layer, afterwards using described the first barrier layer as stop-layer, removes the semiconductor material layer on substrate by the first flatening process, removes described the first barrier layer.In described groove, form after semiconductor material layer; in described groove, the surface of semiconductor material layer forms the first barrier layer; in the time removing the semiconductor material layer in Semiconductor substrate with the first flatening process; the semiconductor material layer that is positioned at described groove can be effectively protected on described the first barrier layer; avoid the semiconductor material layer that is positioned at described groove to sustain damage; thereby guarantee to remove behind described the first barrier layer the evenness on the semiconductor material layer surface that is positioned at described groove of exposing.
Brief description of the drawings
Fig. 1 to Fig. 3 is the structural representation of a kind of semiconductor device flattening method in prior art;
Fig. 4 to Fig. 9 is the structural representation of flattening method one embodiment of semiconductor device of the present invention;
Figure 10 to Figure 15 is the structural representation of another embodiment of flattening method of semiconductor device of the present invention.
Embodiment
As described in background, in semiconductor device flatening process, after planarization, the surface of semiconductor material layer can form depression defect, reduces the evenness on semiconductor material layer surface, and then affects the performance of the semiconductor device of follow-up formation.
Analyze its reason, in the flatening process of semiconductor device, the grinding pad of employing can affect semi-conducting material grinding effect, and the semiconductor material layer local height difference after grinding pad as larger in hardness grinds is less, evenness is better, but causes cut at semiconductor material surface.In the last part technology of flatening process, can select hardness less, the grinding pad that pliability is higher, to reduce the cut of semiconductor material surface, improves the smoothness on semiconductor material layer surface for this reason.
But the higher grinding pad of pliability, in process of lapping, easily forms larger deformation.Particularly, as shown in Figure 3, in semiconductor device flatening process, the grinding rate on the barrier layer 11 on substrate 10 surfaces is less than semiconductor material layer 13 grinding rates.When grinding pad touches barrier layer 11, slower based on barrier layer 11 grinding rates, grinding pad moves down speed obviously to be reduced, but the power still being pressed down based on grinding pad, and the reaction force that imposes on of barrier layer, there is larger deformation in grinding pad, now, still contact with the semi-conducting material in groove 12 in grinding pad middle part, and cause the semi-conducting material damage in groove 12 with larger speed, especially near groove 12 centres, be subject to grinding pad extruding degree maximum away from the semi-conducting material of barrier layer 11 parts, grinding rate is the fastest, thereby form depression (dishing) defect on the surface of semi-conducting material, and, the width of described groove 12 is larger, as width is greater than 10 microns, (μ m), the defect of above-mentioned depression is more obvious, performance impact for the semiconductor device of follow-up formation is larger.
For this reason, the invention provides a kind of flattening method of semiconductor device, comprising: in substrate, form groove, in described groove, form semiconductor material layer, described semiconductor material layer is filled described groove and is covered on described substrate; Semiconductor material layer surface in described groove forms the first barrier layer, afterwards using described the first barrier layer as stop-layer, remove the semiconductor material layer on substrate by the first flatening process, wherein, during removing the semiconductor material layer in Semiconductor substrate with the first flatening process, the semiconductor material layer that is positioned at described groove can be effectively protected on described the first barrier layer, avoid the semiconductor material layer that is positioned at described groove to sustain damage, thereby guarantee to be positioned at the semiconductor material layer surface smoothness of described groove; Remove again afterwards described the first barrier layer, expose the semiconductor material layer in groove.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 4 to Fig. 9 is the structural representation of flattening method one embodiment of semiconductor device of the present invention.
First, with reference to shown in figure 4, provide substrate 20.
Described substrate 20 can be silicon substrate, can be also silica, silicon nitride, germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, and common substrate all can be used as the substrate in the present embodiment.
Substrate 20 in the present embodiment is silicon substrate.
On described substrate 20, form the second barrier layer 21, the second barrier layer 21 and substrate 20 described in etching, at the interior formation groove 22 of described substrate 20.
In the present embodiment; the material on described the second barrier layer 21 can be silicon nitride or silica; form technique and comprise chemical vapour deposition (CVD) (Chemical Vapor Deposition; CVD); ald (Atomic layer deposition; ADL) etc., the formation technique on described the second barrier layer 21 does not limit protection of the present invention.
Described in etching, the method for the second barrier layer 21 and substrate 20 is chosen as dry etch process.Described dry etch process comprises, first on described the second barrier layer 21, form photoresist mask, afterwards taking described photoresist mask as mask, and adopt gases such as fluorine base gas, oxygen, chlorine as etching agent the second barrier layer 21 and substrate 20 described in etching.The formation technique of described groove 22 does not limit in protection scope of the present invention.
In the present embodiment, described groove 22 has larger size, and particularly, the width of described groove 22 is more than or equal to 10 microns, particularly, and as 10～100 microns.
Alternatively, the degree of depth of described groove 22 is more than or equal to 10 microns, particularly, and as 10～100 microns.
Follow-up formation on described substrate 20 after the semiconductor material layer of filling described groove 22, described the second barrier layer 21 is as the grinding stop-layer of grinding semiconductor material layer, if the thickness on described the second barrier layer 21 is excessively thin, the too fast consumption of meeting, even approach exhaustion, cannot play and grind stop-layer effect, cause semi-conducting material to consume excessively, and can cause substrate 20 to damage; When to the interior filling semiconductor material layer of groove 22, meeting filling semiconductor material layer in the opening on the second barrier layer 21 equally, and be positioned at the semiconductor material layer top of described groove 22, after grinding semiconductor material layer technique, semiconductor material layer in the opening on the second barrier layer 21 is retained, if described the second barrier layer 21 is blocked up, can cause final residue semiconductor material layer blocked up, cause the thickness of semiconductor material layer larger with expectation thickness deviation.
In the present embodiment, the thickness on described the second barrier layer 21 is more than or equal to 100 dusts
alternatively, the thickness on described the second barrier layer 21 is
Shown in figure 5, at the interior formation semiconductor material layer 23 of described groove 22, make described semiconductor material layer 23 fill described groove 22, and be covered on described the second barrier layer 21 (being described substrate 20).
In the present embodiment, described semiconductor material layer 23 is polysilicon layer, and described semiconductor material layer 23 guarantor's types cover 21 tops, described the second barrier layer.Described semiconductor material layer 23 comprises and is positioned at the Part I 231 of described groove 22 and is positioned at the Part II 232 on described the second barrier layer 21, and described Part II 232 surfaces are close with the degree of depth of described groove 22 to the distance on described Part I 231 surfaces.
The formation technique of described semiconductor material layer 23 comprises chemical vapour deposition (CVD) (Chemical Vapor Deposition, and ald (Atomic Layer Deposition CVD), ALD) surface that, is positioned at the semiconductor material layer 23 of described groove 22 has good evenness.
In the present embodiment, the surface of the semiconductor material layer in described groove 22 (being also the surface of described Part I 231) is ± 1000 dusts with the difference in height on described substrate 20 surfaces.Optionally, surface and described substrate 20 flush of the semiconductor material layer in described groove 22.
The surface of the semiconductor material layer in described groove 22 (as shown in Figure 5 the surface of semiconductor material layer Part I 231) forms the first barrier layer.
In the present embodiment, the step that forms described the first barrier layer 241 comprises:
First with reference to shown in figure 6, on described semiconductor material layer 23, form barrier material layer 24, described barrier material layer 24 comprises the first layer 241 that is covered in the semiconductor material layer surface in described groove 22, and is covered in second layering 242 on semiconductor material layer surface on described the second barrier layer 21 (as shown in Figure 5 semiconductor material layer Part II 232 surfaces).
In the present embodiment, the formation method of described barrier material layer 24 is chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD).Be chosen as plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD), thereby reduce the damage that causes described semiconductor material layer 23 while forming described barrier material layer 24.
Then with reference to shown in figure 7, remove the second layering 242 that is covered in the semiconductor material layer surface on described the second barrier layer 21 with the second flatening process, retain the first layer 241 that is covered in the semiconductor material layer surface in described groove 22, and using described first layer 241 as described the first barrier layer.
In the present embodiment, described the second flatening process is cmp (CMP), and described CMP technique can adopt the grinding pad that hardness is larger (hard pad), and to adopt silica dioxide granule be mask particle, taking pH value as 11 left and right, the solution that contains potassium hydroxide (KOH) is ground slurry, to remove rapidly second layering 242 on described the first barrier layer 24.
Alternatively, in described the second flatening process, if the material of described barrier material layer 24 is silicon nitride, controlling grinding rate is 500～1000 A/min of clocks, if the material of described barrier material layer 24 is silica, controlling grinding rate is 2000～3000 A/min of clocks.
Continue with reference to shown in figure 7, after described the second flatening process, above described the second barrier layer 21, retained the semiconductor material layer 233 of segment thickness.
Afterwards, shown in figure 8, carry out the first flatening process, to remove the remaining semiconductor material layer 233 in described substrate 20 surfaces (being 21 surfaces, described the second barrier layer), expose described the second barrier layer 21.
In described the first flatening process; described the second barrier layer 21 and described the first barrier layer 241 are as grinding stop-layer; semiconductor material layer in the groove 22 of the described substrate 20 of described first barrier layer 241 effective protection is avoided damage, and described the second barrier layer 21 protects described substrate 20 to avoid damage.
In the present embodiment; the first barrier layer 241 in described the first flatening process and the removal speed ratio of semiconductor material layer 233; be less than barrier material layer in above-mentioned the second flatening process and the removal speed ratio of semiconductor material layer; make described the first barrier layer 241 as grinding stop-layer; protect the semiconductor material layer in described groove 22 to avoid damage; and then guarantee in the surperficial evenness of removing the polysilicon layer (being described Part I 231) exposing after described first layer 241, and smoothness.
Alternatively, in described the first flatening process, the grinding rate ratio on the grinding rate of described semiconductor material layer 233 and described the first barrier layer 241 is more than or equal to 10.
Further alternatively, in the first flatening process, the grinding rate of controlling described semiconductor material layer 233 is
if the material on described the first barrier layer 241 is silicon nitride, the grinding rate on described the first barrier layer 241 is
if the material on described the first barrier layer 241 is silica, the grinding rate on described the first barrier layer 241 is
In the present embodiment, particularly, described the first flatening process is CMP, compare with above-mentioned the second flatening process in adopt the grinding pad that hardness is larger, described the first flatening process adopts the grinding pad (soft pad) that hardness is less, comparatively soft, and can to adopt silica dioxide granule be mask particle, pH value is that the organic solvent of 11 left and right is as ground slurry, to remove the semiconductor material layer 233 on described substrate 20 surfaces.
In described the first flatening process, described the first barrier layer 241 is as grinding the stop-layer of removing the semiconductor material layer 233 on described the second barrier layer 21, to protect the polysilicon of 241 belows, described the first barrier layer.But in described the first flatening process process, described the first barrier layer 24 can be subject to loss, if described the first barrier layer 241 is excessively thin, approach exhaustion can cause the polysilicon damage of its below; If but blocked up, be unfavorable for removing rapidly the polysilicon of 241 both sides, described the first barrier layer.
In the present embodiment, the thickness on described the first barrier layer 241 is more than or equal to
injury-free to guarantee the protecting polysilicon of 241 belows, described the first barrier layer.Alternatively, the thickness on described the first barrier layer 241 is close with described the second barrier layer 21 thickness, for
Shown in figure 9, exposing behind described the second barrier layer 21, adopt wet-etching technology to remove described the second barrier layer 21 and described the first barrier layer 241.
In the present embodiment, alternatively, described the first barrier layer 241 and described the second barrier layer 21 adopt identical material, and thickness is close.Thereby can in same step, remove described the first barrier layer 241 and the second barrier layer 21, expose the polysilicon layer in described substrate 20 and groove 22.
In the present embodiment, if when the material on described the second barrier layer 21 (with first layer 241) is silicon nitride, the etching agent that described wet-etching technology adopts is hot phosphoric acid; If when the material on described the second barrier layer 21 (with the first barrier layer 241) is silica, the etching agent that described wet-etching technology adopts is the hydrofluoric acid solution (DHF) of dilution.Thereby in the time removing described the first barrier layer 241 and the second barrier layer 21, avoid polysilicon layer to be subject to poly-injury, to guarantee evenness and the smoothness on polysilicon layer surface of the groove 22 that is positioned at described substrate 20.
In the present embodiment, in described substrate, form after groove, in described groove, fill polysilicon layer, described polysilicon layer covers the surface of described substrate simultaneously; Polysilicon layer in described groove surface forms the first barrier layer afterwards, and taking described the first barrier layer as stop-layer, removes the semiconductor material layer on substrate by the first flatening process.During removing the semiconductor material layer in Semiconductor substrate with the first flatening process; the semiconductor material layer that is positioned at described groove can be effectively protected on described the first barrier layer; avoid the semiconductor material layer that is positioned at described groove to sustain damage; thereby expose after the semiconductor material layer in groove on described the first barrier layer of removal, guarantee to be positioned at semiconductor material layer surface smoothness and the smoothness of described groove.
Figure 10 to Figure 13 is the schematic diagram of another embodiment of flattening method of semiconductor device of the present invention.
The present embodiment is roughly similar to the technical scheme of above-described embodiment, and its difference is,
Shown in Figure 10, in the present embodiment, the material of described substrate 30 is silica.
In above-described embodiment, on described substrate 30, do not form described the second barrier layer, form after groove 32 at substrate described in etching 30, shown in Figure 11, on described substrate 30, guarantor's type covers semiconductor material layer 33.
In the present embodiment, described groove 32 is similar to the groove structure in above-described embodiment, does not repeat them here.
In the present embodiment, described semiconductor material layer 33 is polysilicon layer.
Described polysilicon layer 33 comprises the Part I 331 that is positioned at described groove 32, and is positioned at the Part II 332 on substrate 30.Polysilicon layer 23 (shown in figure 5) structural similarity in the structure of described polysilicon layer 33 and described above-described embodiment, does not repeat them here.
Afterwards, upper first barrier layer that forms of the polysilicon layer 331 in described groove 32 (being Part I 331).
The formation step on described the first barrier layer comprises:
Shown in Figure 12, form barrier material layer 34 on described polysilicon layer 33 surfaces, described barrier material layer 34 comprises the barrier material layer 341 on the polysilicon layer 331 (being Part I 331) that is positioned at described groove 32, and is positioned at the barrier material layer 342 on the polysilicon layer 332 (being Part II 332) on described substrate 30 surfaces;
Then with reference to shown in Figure 13, adopt the second flatening process to remove the barrier material layer 342 being positioned on the polysilicon layer 332 (being Part II 332) on described substrate 30 surfaces, to remain in barrier material layer 341 on the polysilicon layer 331 (being Part I 331) in described groove 32 as the first barrier layer.
In the present embodiment, the material on described the first barrier layer is silicon nitride, different from the material of described substrate 30.The first barrier layer 241 (shown in figure 6) structural similarity in described the first barrier layer and above-described embodiment, does not repeat them here.
Continue with reference to shown in Figure 13, after described the second flatening process, the polysilicon layer 333 of reserve part thickness on described substrate 30; Then with reference to described in Figure 14, the polysilicon layer 333 that adopts the first flatening process to remove on described substrate 30 exposes described substrate 30.
In the present embodiment, described the first flatening process is similar with the second flatening process to the first flatening process in above-described embodiment with the second flatening process.In flatening process for the first time; control the grinding rate of described polysilicon layer 333 and the grinding rate ratio on described the first barrier layer 341 is more than or equal to 10, thereby described the first barrier layer 341 can protect the polysilicon layer 331 of the groove 32 that is positioned at described substrate 30 to avoid damage.In the present embodiment, described substrate 30 is silicon oxide substrate, thereby described substrate 30 can't be subject to compared with macrolesion.
Afterwards, shown in Figure 15, remove described the first barrier layer 341 with wet-etching technology, expose the polysilicon layer 331 in described groove 32.Above-mentioned wet-etching technology is similar to the wet-etching technology in above-described embodiment, does not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a flattening method for semiconductor device, is characterized in that, comprising:
Substrate is provided;
In described substrate, form groove;
Form semiconductor material layer, make described semiconductor material layer fill described groove and be covered on described substrate;
Semiconductor material layer surface in described groove forms the first barrier layer;
Using described the first barrier layer as stop-layer, remove the semiconductor material layer on substrate by the first flatening process;
Remove described the first barrier layer.
2. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, the step that the semiconductor material layer surface on described groove forms the first barrier layer comprises:
Semiconductor material layer surface on described substrate forms barrier material layer, and described barrier material layer covers described semiconductor material layer;
Removal is positioned at the barrier material layer on the semiconductor material layer surface on described substrate, using the barrier material layer that remaines in the semiconductor material layer surface in described groove as described the first barrier layer.
3. the flattening method of semiconductor device as claimed in claim 2, is characterized in that, the step of removing the barrier material layer that is positioned at the semiconductor material layer surface on described substrate comprises:
Adopt the second flatening process to remove the barrier material layer on the semiconductor material layer surface on described substrate, barrier material layer in described the second flatening process and the removal speed ratio of semiconductor material layer, be greater than the first barrier layer in the first flatening process and the removal speed ratio of semiconductor material layer.
4. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, the removal speed of described the first flatening process to described semiconductor material layer and the removal speed ratio on described the first barrier layer are more than or equal to 10.
5. the flattening method of semiconductor device as claimed in claim 3, is characterized in that, described the first flatening process and the second flatening process are chemical mechanical milling tech; And the grinding pad hardness adopting in described the first flatening process is less than the grinding pad hardness adopting in described the second flatening process.
6. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, the thickness on described the first barrier layer is more than or equal to 100 dusts.
7. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, the formation technique on described the first barrier layer is chemical vapor deposition method.
8. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, the material on described the first barrier layer is silica or silicon nitride, and the material of described semiconductor material layer is polysilicon.
9. the flattening method of semiconductor device as claimed in claim 8, is characterized in that, the step of removing described the first barrier layer comprises: adopt wet etching to remove described the first barrier layer;
If the material on described the first barrier layer is silica, the etching agent of described wet-etching technology is the hydrofluoric acid solution of dilution;
If the material on described the first barrier layer is silicon nitride, the etching agent of described wet-etching technology is phosphoric acid solution.
10. the flattening method of semiconductor device as claimed in claim 1, is characterized in that, in described substrate, forms before groove, and the flattening method of described semiconductor device also comprises:
On described substrate, form the second barrier layer;
The step that forms groove in described substrate comprises:
The second barrier layer and described substrate described in etching form described groove in described substrate.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105789131A (en) * | 2014-12-25 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN107507773A (en) * | 2016-06-14 | 2017-12-22 | 格科微电子（上海）有限公司 | The method of optimizing CMOS imaging sensor transistor arrangement |
| CN108133887A (en) * | 2017-12-04 | 2018-06-08 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
| CN110120342A (en) * | 2019-05-10 | 2019-08-13 | 珠海格力电器股份有限公司 | Semiconductor technology, the production method of semiconductor devices and semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105789131A (en) * | 2014-12-25 | 2016-07-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof and electronic device |
| CN107507773A (en) * | 2016-06-14 | 2017-12-22 | 格科微电子（上海）有限公司 | The method of optimizing CMOS imaging sensor transistor arrangement |
| CN107507773B (en) * | 2016-06-14 | 2021-09-17 | 格科微电子（上海）有限公司 | Method for optimizing transistor structure of CMOS image sensor |
| CN108133887A (en) * | 2017-12-04 | 2018-06-08 | 扬州国宇电子有限公司 | Flattening method based on deep etching |
| CN110120342A (en) * | 2019-05-10 | 2019-08-13 | 珠海格力电器股份有限公司 | Semiconductor technology, the production method of semiconductor devices and semiconductor devices |
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