CN106571294B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN106571294B CN106571294B CN201510669884.4A CN201510669884A CN106571294B CN 106571294 B CN106571294 B CN 106571294B CN 201510669884 A CN201510669884 A CN 201510669884A CN 106571294 B CN106571294 B CN 106571294B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 110
- 238000005498 polishing Methods 0.000 claims abstract description 81
- 239000000126 substance Substances 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 40
- 238000000227 grinding Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000004140 cleaning Methods 0.000 claims abstract description 18
- 239000007788 liquid Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000007800 oxidant agent Substances 0.000 claims abstract description 8
- 239000011241 protective layer Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 21
- 238000007517 polishing process Methods 0.000 abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 13
- 239000002002 slurry Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention provides a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, and forming a plurality of dummy gates on the semiconductor substrate; sequentially depositing a grinding stop layer and an interlayer dielectric layer to cover the semiconductor substrate and the plurality of dummy gates, wherein the top surface of the interlayer dielectric layer is higher than the top surfaces of the dummy gates; performing a first chemical mechanical polishing on the interlayer dielectric layer and stopping in the polishing stop layer; performing second chemical mechanical polishing on the interlayer dielectric layer and stopping on the top surface of the dummy gate; and carrying out third chemical mechanical polishing on the interlayer dielectric layer, wherein liquid including an oxidant is added in the third chemical mechanical polishing process so as to oxidize the top surface of the dummy gate to form a protective layer. According to the manufacturing method, in the third chemical grinding process, the top surface of the dummy gate is oxidized by using hydrogen peroxide to form the protective layer, so that the material of the dummy gate is protected from being lost in the subsequent cleaning step.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
With the continuous development of semiconductor technology, the size of semiconductor devices is continuously decreasing. High-k metal gates below 32nm are becoming the mainstream direction in current semiconductor technology development. Among them, aluminum gates are preferred due to their excellent characteristics.
The chemical-mechanical polishing (CMP) process of the Al gate is one of the most important processes for forming the Al gate, and the CMP process has two functions of mechanical polishing and chemical polishing, so that the entire wafer surface can be planarized, thereby precisely controlling the step of the Al gate.
However, in a conventional CMP process, many defects are often generated on the wafer surface, such defects mainly include scratches (scratches), particles, slurry residues, etc., and it is advantageous to minimize the defects during the CMP process to improve the yield since the defects may cause a loss of production yield.
CMP techniques are widely used in the fabrication of metal gate electrodes in high-k metal gates in 28nm technology nodes. In the process of replacing the metal gate, a chemical mechanical polishing process for opening the pseudo gate polysilicon and a chemical mechanical polishing process for the metal gate are required to be applied to manufacture high-k metal gate devices and products. The dummy gate polysilicon open cmp process precedes dummy gate removal, while the Al metal gate cmp process follows work function metal layer deposition.
The conventional chemical mechanical polishing process for opening the dummy gate polysilicon layer usually includes three times of chemical mechanical polishing, and a first chemical mechanical polishing is performed to remove most of the HARP oxide. Then, a second CMP is performed to stop on the polishing stop layer. And then, carrying out third chemical mechanical polishing to stop on the surface of the dummy gate, and then further comprising a cleaning step for the semiconductor device, wherein in the step, the problem that polycrystalline silicon is damaged in the edge area of the chip due to the fact that the surface of the dummy gate is directly exposed in a cleaning solution is found, and further the problem that the gate height is controlled inaccurately due to the loss of the polycrystalline silicon in the gate area occurs.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
step S1: providing a semiconductor substrate, and forming a plurality of dummy gates on the semiconductor substrate;
step S2: sequentially depositing a grinding stop layer and an interlayer dielectric layer to cover the semiconductor substrate and the plurality of dummy gates, wherein the top surface of the interlayer dielectric layer is higher than the top surfaces of the dummy gates;
step S3: performing a first chemical mechanical polishing on the interlayer dielectric layer and stopping in the polishing stopping layer;
step S4: performing second chemical mechanical polishing on the interlayer dielectric layer and stopping on the top surface of the dummy gate;
step S5: and carrying out third chemical mechanical polishing on the interlayer dielectric layer, wherein liquid including an oxidant is added in the third chemical mechanical polishing process so as to oxidize the top surface of the dummy gate to form a protective layer.
Optionally, in the step S2, the interlayer dielectric layer includes a HARP oxide and a TEOS oxide deposited in sequence.
Optionally, the oxidizing agent comprises hydrogen peroxide.
Optionally, the time of the third chemical mechanical polishing ranges from 10s to 50 s.
Optionally, the first chemical mechanical polishing, the second chemical mechanical polishing and the third chemical mechanical polishing are respectively performed on different polishing pads.
Optionally, the first chemical mechanical polishing is performed using a polishing slurry having a high selectivity ratio of the interlayer dielectric layer material to the polishing stop layer material.
Optionally, after the step S5, a step of cleaning the semiconductor device is further included.
Optionally, the cleaning is performed using a cleaning solution comprising ammonia or hydrofluoric acid.
Optionally, after the step S5, the method further includes the following steps:
removing the dummy gate to form a gate trench;
forming a work function metal layer at the bottom and the side wall in the grid groove;
and forming a metal layer on the work function metal layer to fill the gate groove so as to form a metal gate.
Optionally, a gapped wall is formed on a sidewall of each of the number of dummy gates.
In summary, in the manufacturing method of the present invention, in the third chemical polishing process, the top surface of the dummy gate is oxidized by hydrogen peroxide to form the protection layer, so as to protect the material of the dummy gate from being lost in the subsequent cleaning step, maintain the uniformity of the height of the dummy gate, and improve the yield and performance of the device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1A-1D illustrate cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device, in accordance with one embodiment of the present invention;
FIG. 2 shows a top view of a CMP apparatus used in accordance with an embodiment of the present invention;
FIG. 3 is a graph showing a comparison of the method of one embodiment of the present invention with prior art polysilicon thickness test data before and after cleaning;
fig. 4 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to an embodiment of the present invention is described below with reference to fig. 1A to 1D and fig. 2 to 4.
Illustratively, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of:
as shown in fig. 1A, a semiconductor substrate 100 is provided on which a number of dummy gates 101 are formed.
The semiconductor substrate 100 may be formed of undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, the constituent material of the semiconductor substrate 100 is monocrystalline silicon.
An isolation structure (not shown) is formed in the semiconductor substrate 100, and the isolation structure may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Illustratively, the isolation structure may divide the semiconductor substrate 100 into an NMOS region and a PMOS region. Various well structures are also formed in the semiconductor substrate 100, and are omitted from the drawings for simplicity.
The material of the dummy gate 101 includes polysilicon or amorphous carbon, preferably polysilicon.
In one example, the method for forming the dummy gate 101 is as follows: sequentially depositing a high-K dielectric layer (not shown) and a dummy gate material layer on a semiconductor substrate, forming a patterned photoresist layer on the dummy gate material layer, wherein the photoresist layer defines the shape of the dummy gate 101 and the size of the critical dimension, and etching the dummy gate material layer and the high-K dielectric layer by using the photoresist layer as a mask to form a dummy gate structure. The photoresist layer is then removed. The above method of forming the dummy gate 101 is only exemplary, and any other method of forming the dummy gate 101 may be applied to the present invention. Illustratively, the dummy gate material layer is a polysilicon layer. The polysilicon layer may be formed by any deposition method known to those skilled in the art, such as Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and generally similar methods such as sputtering and Physical Vapor Deposition (PVD) may also be used.
The high-k dielectric layer has a k value (dielectric constant) of usually 3.9 or more, and the constituent material thereof includes hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-K dielectric layer may be formed using a suitable process such as CVD, ALD, or PVD. The high-K dielectric layer has a thickness in the range of 10 angstroms to 30 angstroms.
Gapped walls are formed on sidewalls of each of the number of dummy gates. The spacer is made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the spacer is a stack of oxide and nitride. The process of forming the spacers may be any process known to those skilled in the art, such as chemical vapor deposition. Spacers are also inevitably formed above the dummy gate structure during spacer deposition, but are removed by chemical mechanical polishing or etching in subsequent processes.
Next, with continuing reference to fig. 1A, a polishing stop layer 102 and an interlayer dielectric layer 103 are sequentially deposited to cover the semiconductor substrate 100 and the dummy gates 101, wherein a top surface of the interlayer dielectric layer 103 is higher than a top surface of the dummy gates 101.
The polish stop layer 102 may be formed of SiCN, SiN, SiC, SiOF, SiON, or the like. In the present embodiment, the material of the polishing stop layer 102 preferably comprises silicon nitride. Any suitable deposition method such as CVD or PVD may be used.
The interlayer dielectric layer 103 may be formed by any suitable process known to those skilled in the art, such as a chemical vapor deposition process. The interlayer dielectric layer 102 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
In one example, the interlayer dielectric layer 103 may further include a High Aspect Ratio (HARP) oxide 103a and a TEOS oxide 103b deposited in sequence.
Next, referring to fig. 1B, a first cmp process is performed on the ild layer 103 to stop in the polish stop layer 102.
Illustratively, a first CMP process is performed to remove most of the IMD layer 103, which is a relatively fast polishing rate and a rough polishing method. The first chemical mechanical polishing is performed using a polishing slurry having a high selectivity ratio of the material of the interlayer dielectric layer 103 to the material of the polishing stop layer 102, for example, a selectivity ratio of 50:1 or higher. The polishing rate of the interlayer dielectric layer 103 by the polishing slurry is much higher than that of the polishing stop layer 102. For example, when the material of the interlayer dielectric layer is oxide and the material of the etch stop layer is silicon nitride, the polishing slurry may be a polishing slurry of CES333, model number of the asahi glass company (ASAHI GLASS co. ltd).
A general CMP apparatus is equipped with an end point detection device (EPD) to detect the polishing end point as needed. When the material is ground to a predetermined target thickness or target material (target position), the end point detection means signals that grinding is stopped. In one example, the polishing endpoint of the first chemical mechanical polishing is detected using optical endpoint detection or motor current endpoint detection.
Next, referring to fig. 1C, a second cmp process is performed on the ild layer 102 to stop on the top surface of the dummy gate 101.
The second chemical mechanical polishing is fine polishing, and the polishing speed of the second chemical mechanical polishing is lower than that of the first chemical mechanical polishing. In this step, the second cmp stops on the top surface of the dummy gate 101, thereby exposing the top surface of the dummy gate. In this embodiment, the second CMP is performed using a slurry having the same or similar selectivity of the material of the interlayer dielectric layer 103 to the material of the polish stop layer 102, while the slurry may also have a low selectivity to the dummy gate material, for example, a model PL6116 slurry from FUJIMI, Japan. Since the selectivity ratio is the same or similar, the polishing rate is the same or similar, and the polishing stop layer 102 can be polished simultaneously with the polishing of the interlayer dielectric layer 103. Illustratively, the second cmp stops on the top surface of the dummy gate 101 by detecting the endpoint of the second cmp using an endpoint detection technique based on a change in the drive motor current to completely remove the interlayer dielectric layer 103 over the dummy gate.
Next, referring to fig. 1D, a third cmp process is performed on the interlayer dielectric layer 103, wherein a liquid including an oxidant is added during the third cmp process to oxidize the top surface of the dummy gate 101 to form a protection layer 104.
Illustratively, the oxidizing agent comprises hydrogen peroxide. For example, in the third chemical mechanical polishing, a solution containing hydrogen peroxide is added to the polishing pad. The third chemical mechanical polishing can also be performed by using a mixed solution of hydrogen peroxide and a polishing solution. Further, the time range of the third chemical mechanical polishing is 10s to 50 s. The third cmp process has a low polishing rate, which is a chemical polishing process, and since a liquid including hydrogen peroxide is used in the polishing process, the top surface of the polysilicon dummy gate is oxidized to form a protective layer. The protective layer can avoid polysilicon damage and loss caused by the fact that cleaning liquid directly contacts the dummy gate in the subsequent cleaning process.
Further, as shown in fig. 2, the first cmp, the second cmp and the third cmp are performed on three different polishing pads, and the polishing rates are sequentially decreased. After the polishing head picks up the wafer 21 from the wafer carrier 22, the polishing head is moved to the first polishing pad by the polishing head transport device to perform a first chemical mechanical polishing on the wafer, wherein the first chemical mechanical polishing employs a higher polishing rate and a higher polishing force to planarize and polish most of the interlayer dielectric layer, and stops on the polishing stop layer. Most of the interlayer dielectric layer is removed after the first chemical mechanical polishing. After the first grinding is finished, the grinding head is moved to the position of the second grinding pad to carry out second chemical mechanical grinding on the wafer, and the second chemical mechanical grinding is carried out on the waferThe wafer is subjected to fine grinding, the grinding rate is lower than that of the first chemical mechanical grinding, the grinding stop layer and the interlayer dielectric layer above the pseudo grid electrode are removed through the second chemical mechanical grinding, and the top surface of the pseudo grid electrode is exposed; and finally, moving the grinding head to a third grinding pad to carry out third chemical mechanical grinding on the wafer, wherein the third chemical mechanical grinding adopts lower grinding speed and lower grinding force than the previous two chemical mechanical grindings, and the H is utilized to carry out chemical polishing on the wafer while the H is utilized2O2And oxidizing the top surface of the dummy gate to form a protective layer.
And then, a cleaning step is further included, and in this embodiment, the semiconductor device is cleaned by using a cleaning liquid including ammonia water or hydrofluoric acid.
Figure 3 is a graph comparing the method of one embodiment of the present invention to prior art polysilicon thickness test data before and after cleaning. As can be seen, the loss of polysilicon layer before and after the cleaning step is nearly zero using the method of the present invention, whereas the polysilicon thickness loss on the wafer is found to be nearly 50 angstroms using the prior art method.
The above steps are only some steps in the process of manufacturing the metal gate, and other steps are required for manufacturing the complete semiconductor device, for example, the following steps can be performed after: removing the dummy gate to form a gate trench; forming a work function metal layer at the bottom and the side wall in the grid groove; and forming a metal layer on the work function metal layer to fill the gate groove so as to form a metal gate.
Referring to fig. 4, a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown to schematically illustrate the flow of the entire manufacturing process.
Step S401: providing a semiconductor substrate, and forming a plurality of dummy gates on the semiconductor substrate;
step S402: sequentially depositing a grinding stop layer and an interlayer dielectric layer to cover the semiconductor substrate and the plurality of dummy gates, wherein the top surface of the interlayer dielectric layer is higher than the top surfaces of the dummy gates;
step S403: performing a first chemical mechanical polishing on the interlayer dielectric layer and stopping in the polishing stopping layer;
step S404: performing second chemical mechanical polishing on the interlayer dielectric layer and stopping on the top surface of the dummy gate;
step S405: and carrying out third chemical mechanical polishing on the interlayer dielectric layer, wherein liquid including an oxidant is added in the third chemical mechanical polishing process so as to oxidize the top surface of the dummy gate to form a protective layer.
In summary, in the manufacturing method of the present invention, in the third chemical polishing process, the top surface of the dummy gate is oxidized by hydrogen peroxide to form the protection layer, so as to protect the material of the dummy gate from being lost in the subsequent cleaning step, maintain the uniformity of the height of the dummy gate, and improve the yield and performance of the device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of manufacturing a semiconductor device, comprising:
step S1: providing a semiconductor substrate, and forming a plurality of dummy gates on the semiconductor substrate;
step S2: sequentially depositing a grinding stop layer and an interlayer dielectric layer to cover the semiconductor substrate and the plurality of dummy gates, wherein the top surface of the interlayer dielectric layer is higher than the top surfaces of the plurality of dummy gates;
step S3: performing a first chemical mechanical polishing on the interlayer dielectric layer and stopping in the polishing stopping layer;
step S4: performing second chemical mechanical polishing on the interlayer dielectric layer and stopping on the top surfaces of the plurality of dummy gates; and
step S5: performing a third CMP process on the interlayer dielectric layer, wherein a liquid containing an oxidant is added in the third CMP process to oxidize the top surfaces of the dummy gates to form a protective layer,
after the step S5, a step of cleaning the semiconductor device is further included.
2. The method of manufacturing of claim 1, wherein in the step S2, the interlayer dielectric layer comprises a high aspect ratio oxide and an ethyl silicate oxide deposited sequentially.
3. The method of manufacturing according to claim 1, wherein the oxidizing agent comprises hydrogen peroxide.
4. The manufacturing method according to claim 1, wherein the time period of the third chemical mechanical polishing is in a range of 10s to 50 s.
5. The manufacturing method according to claim 1, wherein the first chemical mechanical polishing, the second chemical mechanical polishing and the third chemical mechanical polishing are performed on different polishing pads respectively.
6. The manufacturing method according to claim 1, wherein the first chemical mechanical polishing is performed using a polishing liquid having a high selection ratio of the interlayer dielectric layer to the polishing stop layer.
7. The manufacturing method according to claim 1, wherein the cleaning is performed using a cleaning liquid including ammonia water or hydrofluoric acid.
8. The manufacturing method according to claim 1, characterized by further comprising, after the step S5, the steps of:
removing the plurality of dummy gates to form gate trenches;
forming a work function metal layer at the bottom and the side wall in the grid groove;
and forming a metal layer on the work function metal layer to fill the gate groove so as to form a metal gate.
9. The method of manufacturing according to claim 1, wherein a spacer is formed on a sidewall of each of the plurality of dummy gates.
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| CN108520865B (en) * | 2018-03-21 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for manufacturing grid |
| CN108493159A (en) * | 2018-04-13 | 2018-09-04 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
| CN109037053B (en) * | 2018-07-13 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for manufacturing grid |
| CN111081709B (en) * | 2018-10-22 | 2022-07-22 | 华邦电子股份有限公司 | Method of manufacturing nonvolatile memory device |
| CN110444470A (en) * | 2019-08-22 | 2019-11-12 | 上海华力集成电路制造有限公司 | A kind of method of different line width transistor gate height in improvement semiconductor devices |
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