CN104716035A - Chemical mechanical polishing method - Google Patents
Chemical mechanical polishing method Download PDFInfo
- Publication number
- CN104716035A CN104716035A CN201310681524.7A CN201310681524A CN104716035A CN 104716035 A CN104716035 A CN 104716035A CN 201310681524 A CN201310681524 A CN 201310681524A CN 104716035 A CN104716035 A CN 104716035A
- Authority
- CN
- China
- Prior art keywords
- layer
- mechanical polishing
- dummy grid
- stop layer
- etching stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005498 polishing Methods 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000126 substance Substances 0.000 title abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 133
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000006061 abrasive grain Substances 0.000 claims description 10
- 238000007596 consolidation process Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000002002 slurry Substances 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- -1 SiON Chemical compound 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a chemical mechanical polishing method. The method comprises steps: a semiconductor substrate is provided, and a pseudo grid is formed on the semiconductor substrate; an etch stop layer covering the pseudo grid and the semiconductor substrate, and an interlayer dielectric layer covering the etch stop layer are formed; primary chemical mechanical polishing is carried out until the etch stop layer at the top part of the pseudo grid is exposed; sacrificial layers are formed on the interlayer dielectric layer after polishing and the etch stop layer after polishing; and secondary chemical mechanical polishing is carried out until the pseudo grid is exposed. According to the chemical mechanical polishing method of the invention, the bridge connection problem is avoided, the polishing efficiency is high, the polished surface has good flatness and the like.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly, relate to a kind of method of chemico-mechanical polishing.
Background technology
Semiconductor device reduces further in its size, such as, when being less than 32nm technology node, metal gates can be used to replace polysilicon gate.But metal gates faces the test of interlayer dielectric layer flatening in preparation process.Such as, when adopting CMP (Chemical Mechanical Polishing) process to carry out planarization to interlayer dielectric layer, the interlayer dielectric layer after polishing is likely formed with darker cut and pit.In the process of follow-up formation metal gates, metal can fill up cut on interlayer dielectric layer and pit, and can cause bridge joint problem (bridge issue) thus and semiconductor device is scrapped, the yield of product reduces greatly.
Therefore, a kind of method proposing chemico-mechanical polishing is needed, to solve problems of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The invention provides a kind of method of chemico-mechanical polishing.Described method comprises: provide Semiconductor substrate, and described Semiconductor substrate is formed with dummy grid; Form the etching stop layer covering described dummy grid and described Semiconductor substrate and the interlayer dielectric layer covering described etching stop layer; Carry out the first chemico-mechanical polishing, to the etching stop layer exposing described dummy grid top; Etching stop layer on interlayer dielectric layer after a polish and after polishing forms sacrifice layer; And carry out the second chemico-mechanical polishing, to exposing described dummy grid.
Preferably, described first chemico-mechanical polishing is the glossing adopting consolidation abrasive polishing pad.
Preferably, the abrasive grains on described consolidation abrasive polishing pad has high grinding selectivity ratio.
Preferably, described abrasive grains is CeO
2and/or SiO
2.
Preferably, described second chemico-mechanical polishing is the glossing adopting non-selectivity ground slurry.
Preferably, the thickness of described sacrifice layer is
Preferably, described method also comprises: remove described dummy grid, to form opening; Metal gate structure is formed in described opening.
Preferably, the material of described etching stop layer is SiN layer.
Preferably, the material of described interlayer dielectric layer is silica.
Preferably, described method is also included in described dummy grid both sides formation side wall after the described dummy grid of formation and before forming described etching stop layer, and wherein said etching stop layer covers described dummy grid, described side wall and described Semiconductor substrate.
According to cmp method of the present invention, by one deck sacrifice layer redeposited on the interlayer dielectric layer after the first chemico-mechanical polishing and etching stop layer, to be filled in the cut and pit that produce on interlayer dielectric layer and etching stop layer in the first CMP (Chemical Mechanical Polishing) process, and carry out second time chemico-mechanical polishing, and then avoid bridge joint problem.Therefore, the method provided of the present invention also has the advantages such as polishing efficiency is high, polished surface flatness is good.
Below in conjunction with accompanying drawing, describe advantages and features of the invention in detail.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the flow chart of the method for chemico-mechanical polishing according to an embodiment of the invention; And
Fig. 2 A-2H adopts the method shown in Fig. 1 to carry out the cutaway view of the device that each step obtains in CMP (Chemical Mechanical Polishing) process.
Embodiment
Next, by reference to the accompanying drawings the present invention will more intactly be described, shown in the drawings of embodiments of the invention.But the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other elements or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.
According to an aspect of the present invention, a kind of method of chemico-mechanical polishing is provided.The present invention is described in detail below in conjunction with the semiconductor device structure schematic diagram shown in the flow chart of the method for the chemico-mechanical polishing according to an embodiment of the invention shown in Fig. 1 and Fig. 2 A-Fig. 2 H.
Perform step S110: Semiconductor substrate is provided, this Semiconductor substrate is formed with dummy grid.
As shown in Figure 2 A, there is provided Semiconductor substrate 210, this Semiconductor substrate 210 can be at least one on silicon, silicon-on-insulator (SOI), insulator on stacked silicon (SSOI), insulator in stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI).Can be formed with shallow trench isolation for isolating active area in Semiconductor substrate 210 from (STI) etc., shallow trench isolation is from being formed by silica, silicon nitride, silicon oxynitride, Fluorin doped glass and/or other existing dielectric materials.Certainly, dopant well (not shown) etc. can also be formed with in Semiconductor substrate 210.In order to illustrative simplicity, here only represent with square frame.
Semiconductor substrate 210 is formed with layer of gate dielectric material 220 '.Layer of gate dielectric material 220 ' can comprise traditional dielectric material and such as have dielectric constant from about 4 to oxide (the such as SiO of the silicon of about 20 (true aerial surveties)
2), nitride (such as Si
3n
4) and nitrogen oxide (such as SiON, SiON
2).Wherein the layer of gate dielectric material 220 ' of silica material can adopt oxidation technology such as furnace oxidation, the formation such as rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) etc. known by those skilled in the art.The layer of gate dielectric material 220 ' of silicon nitride material then can pass through the formation such as nitriding process such as high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize or pecvd nitride.The layer of gate dielectric material 220 ' that nitriding process then can form silicon oxynitride material is performed further to silica.
Or layer of gate dielectric material 220 ' also can comprise the usual comparatively hafnium with K from about 20 at least about 100.This comparatively hafnium can include but not limited to: hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium etc.It can adopt any applicable formation process to be formed.Such as chemical vapour deposition (CVD), physical vapour deposition (PVD) etc.
Layer of gate dielectric material 220 ' is formed with dummy grid material layer 230 '.Dummy grid material layer 230 ' can be such as polysilicon.The formation method of polysilicon can select low-pressure chemical vapor deposition (LPCVD) technique.
As shown in Figure 2 B, dummy grid material layer 230 ' and layer of gate dielectric material 220 ' are etched, to form dummy grid 230 and gate dielectric 220.Exemplarily, can be etched dummy grid material layer 230 ' and layer of gate dielectric material 220 ' by the method for photoetching.First, dummy grid material layer 230 ' forms photoresist, and alignment mask plate is to its exposure, development, forms the photoresist layer with dummy grid pattern.Wherein, in the reflection of the lower surface of photoresist layer in order to reduce light in exposure process, most of energy of exposure is all absorbed by photoresist, antireflecting coating can be set between photoresist layer and dummy grid material layer 230 '.In addition, in order to ensure that the pattern in photoresist layer can be transferred on dummy grid material layer 230 ' exactly, hard mask layer can also be set between dummy grid material layer 230 ' and antireflecting coating.This hard mask layer can be one or more in SiN, SiON, SiC and oxide.Hard mask layer can make the figure of formation more accurate in the process of etching.
Secondly, with the photoresist layer of patterning for mask, dummy grid material layer 230 ' and layer of gate dielectric material 220 ' are etched, to form dummy grid 230 and gate dielectric 220.Etching can be carried out by the etching technics such as using plasma etching.Wherein, when being provided with antireflecting coating and/or hard mask layer, can first by the design transfer in photoresist layer in antireflecting coating and/or hard mask layer, and with antireflecting coating and/or hard mask layer for mask etches dummy grid material layer 230 ' and layer of gate dielectric material 220 ', to form dummy grid 230 and gate dielectric 220.
In addition, according to one embodiment of present invention, side wall 240 can also be formed in the both sides of dummy grid 230 as shown in Figure 2 B.The material of side wall 240 can be such as at least one in oxide, nitride or nitrogen oxide.It can be formed by known deposition and etching.Side wall 240 can follow-up carry out etching or ion implantation time grill-protected electrode structure sidewall injury-free.It also can make to form the different region of doping content in source-drain electrode.
Perform step S120: form the etching stop layer covering dummy grid and Semiconductor substrate and the interlayer dielectric layer covering etching stop layer.
As shown in Figure 2 C, the etching stop layer 250 covering dummy grid 230 and Semiconductor substrate 210 is formed.Here be preferably contact hole etching stop-layer, material is silicon nitride.In the semiconductor device structure being formed with side wall 240, etching stop layer 250 also should cover side wall 240.Etching stop layer 250 can pass through the suitable depositing operation such as physical vapour deposition (PVD), chemical vapour deposition (CVD) or other nitriding processes are formed.At this, repeat no more.
Next, as shown in Figure 2 C, etching stop layer 250 is formed the interlayer dielectric layer 260 covering etching stop layer.Interlayer dielectric layer 260 can be silicon oxide layer, comprise the material layer having doping or unadulterated silica utilizing thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP) manufacturing process to be formed, the silex glass (USG) of such as undoped, phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).
Perform step S130: carry out the first chemico-mechanical polishing, to the etching stop layer exposing dummy grid top.
As shown in Figure 2 D, carry out the first chemico-mechanical polishing, to the etching stop layer 250 exposing dummy grid top.The principle of chemico-mechanical polishing comprises chemistry and the combination of mechanical effect, in material surface to be ground, generating certain layer, then mechanically this certain layer being removed because there is chemical reaction.Chemico-mechanical polishing can be carried out on consolidation abrasive polishing pad, and now, abrasive grains is fixed on polishing pad.Chemico-mechanical polishing also can be carried out on non-consolidation abrasive polishing pad (such as free ground slurry polishing pad), and now, abrasive grains can be graininess and be suspended in liquid carrier.Preferably, according to one embodiment of present invention, the first chemico-mechanical polishing adopts consolidation abrasive polishing pad to carry out.In this case, just have an effect with the position that contacts of polished surface in the outstanding position (abrasive grains) being only cemented in the slurry bed of material of polishing pad, for traditional non-consolidation abrasive polishing pad (such as free abrasive polishing pad), contact area reduces, small contact area produces the larger pressure in local, and polishing speed is greatly increased.In addition, its polishing speed has very high selectivity for the surface topography of polished surface, only needs less removal amount, namely can reach the object of planarization.
Preferably, the abrasive grains on consolidation abrasive polishing pad has high grinding selectivity ratio.Such as, according to one embodiment of present invention, this abrasive grains is to interlayer dielectric layer 260(such as silica) there is higher polishing speed, and to etching stop layer (such as SiN), there is extremely low polishing speed.Preferably, abrasive grains is CeO
2and/or SiO
2.Therefore, etching stop layer 250 can be terminated in relatively easily in the first chemico-mechanical polishing.
Perform step S140: the etching stop layer on interlayer dielectric layer after a polish and after polishing forms sacrifice layer.
After carrying out the first CMP (Chemical Mechanical Polishing) process, the etching stop layer 250 on the interlayer dielectric layer 260 after polishing and after polishing is likely formed with darker cut and/or pit.Such as, after employing consolidation abrasive polishing pad carries out chemico-mechanical polishing, interlayer dielectric layer 260 after a polish may form hundreds of
the cut of the degree of depth and/or pit.In interlayer dielectric layer 260 below the upper surface that this cut and/or pit may be deep into dummy grid 230, cause follow-up be polished to dummy grid 230 time still can leave cut and/or pit on the surface of interlayer dielectric layer 260.And in follow-up operation as shown in Fig. 2 G-2H, remove dummy grid 230 to form opening 280 ', and when forming metal gate structure 280 in opening 280 ', due to interlayer dielectric layer 260 still leaving cut and/or pit, when forming metal gate structure 280, metal can fill up cut and/or pit, can cause aforesaid bridge joint problem thus.
Therefore, can improve technique.As shown in Figure 2 E, the etching stop layer 250 on interlayer dielectric layer 260 after a polish and after polishing forms sacrifice layer 270.This sacrifice layer is preferably identical with the material of interlayer dielectric layer 260, such as, can be silica etc.This sacrifice layer 270 can be filled in the cut and/or pit that produce in the first CMP (Chemical Mechanical Polishing) process, and that thus can avoid in subsequent technique in metal gates is metal filled in cut and/or pit.The thickness of this sacrifice layer 270 can be
the thickness of sacrifice layer 270, within the scope of this, both can ensure to fill up cut and/or pit, was unlikely to again to cause needing longer polishing time because sacrifice layer 270 is too thick in the second CMP (Chemical Mechanical Polishing) process subsequently.
Perform step S150: carry out the second chemico-mechanical polishing, to exposing dummy grid.
As shown in Figure 2 F, carry out the second chemico-mechanical polishing, to exposing dummy grid 230.Preferably, the second chemico-mechanical polishing is the glossing adopting non-selectivity ground slurry.This ground slurry has substantially identical polishing speed to nitride and oxide.Use the ground slurry of non-selectivity that the surface after the second chemico-mechanical polishing can be made very smooth.
In practical operation, the polishing speed of nitride usually can lower than the polishing speed of oxide, and the surface of the nitride therefore after the first chemico-mechanical polishing and the second chemico-mechanical polishing can a little more than the surface of oxide.
Next, when interlayer dielectric layer 260 and dummy grid 230 are polished to smooth, metal gate structure 280 can be formed further.As shown in Figure 2 G, dummy grid 230 is removed, to form opening 280 '.Dummy grid 230 can be removed by the etching technics that those skilled in the art are known, repeats no more here.After formation opening 280 ', can also deposited barrier layer (not shown) on the gate dielectric 220 in opening 280 ', be diffused on gate dielectric 220 to prevent the follow-up metal gate material that will be formed on gate dielectric 220.Barrier layer can comprise such as TiN, TaN etc.Barrier layer can be formed by such as ald or other suitable modes.In addition, gate dielectric 220 in opening 280 ' or barrier layer can also form work-function layer (not shown), to provide high effective work function (EWF) value.This work-function layer can comprise in Ti, TaN, TiN, AlCO, TiAlN one or more.Work-function layer can be formed by atomic layer deposition method or other suitable modes.
As illustrated in figure 2h, in opening 280 ' (see Fig. 2 G), metal gate structure 280 is formed.Metal gate structure 280 can select the high-K metal material with low resistivity, such as aluminium gate, tungsten grid etc.It can adopt the suitable mode such as physical vapour deposition (PVD), chemical vapour deposition (CVD) to be formed.
In sum, according to cmp method of the present invention, by one deck sacrifice layer redeposited on the interlayer dielectric layer 260 after the first chemico-mechanical polishing and etching stop layer 250, to be filled in the cut and pit that produce on interlayer dielectric layer 260 and etching stop layer 250 in the first CMP (Chemical Mechanical Polishing) process, and carry out second time chemico-mechanical polishing, and then avoid aforesaid bridge joint problem.Therefore, the method provided of the present invention also has the advantages such as polishing efficiency is high, polished surface flatness is good.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a method for chemico-mechanical polishing, is characterized in that, described method comprises:
Semiconductor substrate is provided, described Semiconductor substrate is formed with dummy grid;
Form the etching stop layer covering described dummy grid and described Semiconductor substrate and the interlayer dielectric layer covering described etching stop layer;
Carry out the first chemico-mechanical polishing, to the etching stop layer exposing described dummy grid top;
Etching stop layer on interlayer dielectric layer after a polish and after polishing forms sacrifice layer; And
Carry out the second chemico-mechanical polishing, to exposing described dummy grid.
2. the method for claim 1, is characterized in that, described first chemico-mechanical polishing is the glossing adopting consolidation abrasive polishing pad.
3. method as claimed in claim 2, it is characterized in that, the abrasive grains on described consolidation abrasive polishing pad has high grinding selectivity ratio.
4. method as claimed in claim 3, it is characterized in that, described abrasive grains is CeO
2and/or SiO
2.
5. method as claimed in claim 2, is characterized in that, described second chemico-mechanical polishing is the glossing adopting non-selectivity ground slurry.
6. the method for claim 1, is characterized in that, the thickness of described sacrifice layer is
7. the method for claim 1, is characterized in that, described method also comprises:
Remove described dummy grid, to form opening;
Metal gate structure is formed in described opening.
8. the method for claim 1, is characterized in that, the material of described etching stop layer is SiN layer.
9. the method for claim 1, is characterized in that, the material of described interlayer dielectric layer is silica.
10. the method for claim 1, it is characterized in that, described method is also included in described dummy grid both sides formation side wall after the described dummy grid of formation and before forming described etching stop layer, and wherein said etching stop layer covers described dummy grid, described side wall and described Semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310681524.7A CN104716035A (en) | 2013-12-12 | 2013-12-12 | Chemical mechanical polishing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310681524.7A CN104716035A (en) | 2013-12-12 | 2013-12-12 | Chemical mechanical polishing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104716035A true CN104716035A (en) | 2015-06-17 |
Family
ID=53415245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310681524.7A Pending CN104716035A (en) | 2013-12-12 | 2013-12-12 | Chemical mechanical polishing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104716035A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571294A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN106783580A (en) * | 2016-12-29 | 2017-05-31 | 上海集成电路研发中心有限公司 | A kind of method of chemical mechanical polishing of metals |
| CN109980081A (en) * | 2017-12-28 | 2019-07-05 | 中电海康集团有限公司 | Can self-stopping technology polishing MRAM device production method and MRAM device |
| CN117790319A (en) * | 2024-02-27 | 2024-03-29 | 合肥晶合集成电路股份有限公司 | Method for forming semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314706A (en) * | 2000-03-21 | 2001-09-26 | 日本电气株式会社 | Method for forming element isolation zone |
| CN102569083A (en) * | 2010-12-23 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal-oxide semiconductor with high potassium (K) metal gate |
| CN102683189A (en) * | 2011-03-07 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate and MOS (Metal Oxide Semiconductor) transistor |
| CN103137452A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for controlling substitute gate structure height |
-
2013
- 2013-12-12 CN CN201310681524.7A patent/CN104716035A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314706A (en) * | 2000-03-21 | 2001-09-26 | 日本电气株式会社 | Method for forming element isolation zone |
| CN102569083A (en) * | 2010-12-23 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal-oxide semiconductor with high potassium (K) metal gate |
| CN102683189A (en) * | 2011-03-07 | 2012-09-19 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate and MOS (Metal Oxide Semiconductor) transistor |
| CN103137452A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for controlling substitute gate structure height |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571294A (en) * | 2015-10-13 | 2017-04-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN106571294B (en) * | 2015-10-13 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN106783580A (en) * | 2016-12-29 | 2017-05-31 | 上海集成电路研发中心有限公司 | A kind of method of chemical mechanical polishing of metals |
| CN109980081A (en) * | 2017-12-28 | 2019-07-05 | 中电海康集团有限公司 | Can self-stopping technology polishing MRAM device production method and MRAM device |
| CN109980081B (en) * | 2017-12-28 | 2023-10-20 | 中电海康集团有限公司 | Method for manufacturing MRAM device capable of stopping polishing automatically and MRAM device |
| CN117790319A (en) * | 2024-02-27 | 2024-03-29 | 合肥晶合集成电路股份有限公司 | Method for forming semiconductor device |
| CN117790319B (en) * | 2024-02-27 | 2024-05-24 | 合肥晶合集成电路股份有限公司 | Method for forming semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI689043B (en) | Transistor and methods of forming the same | |
| US7807532B2 (en) | Method and structure for self aligned formation of a gate polysilicon layer | |
| CN100565811C (en) | Semiconductor device with the metal gate electrode that on the height-k gate dielectric layer of annealing, forms | |
| CN102148236B (en) | Semiconductor device and method of manufacturing the same | |
| TWI520319B (en) | Semiconductor device and method for fabricating the same | |
| US8685859B2 (en) | Self-aligned semiconductor trench structures | |
| US7504287B2 (en) | Methods for fabricating an integrated circuit | |
| US8865595B2 (en) | Device and methods for forming partially self-aligned trenches | |
| CN101794711B (en) | Method of manufacturing semiconductor elements | |
| CN107799461B (en) | Method for manufacturing semiconductor device | |
| US10128304B2 (en) | Isolation for semiconductor devices | |
| CN106571294B (en) | Method for manufacturing semiconductor device | |
| JPH11176930A (en) | Semiconductor device, and forming of layer uniform in flatness and thickness | |
| CN104716035A (en) | Chemical mechanical polishing method | |
| CN107958840A (en) | The manufacture craft of semiconductor device | |
| KR101205066B1 (en) | Method for isolation in semiconductor device | |
| CN109037154B (en) | Method for manufacturing semiconductor device | |
| CN108735670B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| TWI240375B (en) | Integrated circuit structure and method of fabrication | |
| CN114093806A (en) | Manufacturing method of semiconductor structure | |
| CN101587862B (en) | Method for forming insulating structure and semiconductor structure | |
| JP2009060143A (en) | Semiconductor device | |
| CN104716030A (en) | Semiconductor device and manufacturing method thereof | |
| CN111435658A (en) | Method for forming dielectric layer | |
| US9391177B1 (en) | Method of fabricating semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150617 |
|
| RJ01 | Rejection of invention patent application after publication |