CN101587862B - Method for forming insulating structure and semiconductor structure - Google Patents

Abstract

The invention discloses a method for forming an insulating structure and a semiconductor structure, in particular a method for forming a self-alignment structure of a passing gate. The method for forming the insulating structure comprises: a first step of providing a substrate, in which deep trenches filled with a silicon material and shallow trench isolators adjoined with the deep trenches are arranged inside the substrate, and a patterned pad oxide layer and a hard mask which define openings of the deep trenches together are arranged on the substrate sequentially; a step of oxidization, in which first oxide layers are formed on the surfaces of the silicon material in the deep trenches to serve as the insulating structure of the passing gate; a step of forming first silicon layers in the openings to cover the first oxide layers; and a step of removing the hard mask.

Description

A kind of formation method and semiconductor structure of insulation system

Technical field

The present invention relates to a kind of method that forms insulation system.Particular it, the present invention relates to a kind of method of autoregistration insulation system of the grid (passing gate) that is formed for passing by on one's way.

Background technology

In the development of dynamic random access memory (DRAM) technology; In order to increase the component density on the chip; Can arrange word line (word line) " to pass by " deep groove capacity that other do not receive this word line control from the top, with effective raising integrated level (integration).Fig. 1 is that the illustration word line is passed by the deep groove capacity that other do not receive this word line control from the top.As shown in Figure 1; On layout patterns; Each individual word line 101 strides across from (STI) top from active region 102, deep groove capacity 103 and shallow trench isolation; Wherein when not making deep groove capacity 103 as yet, have only shallow trench isolation to leave (STI) and active region 102 in the substrate, therefore non-zone of leaving (STI) for shallow trench isolation is active region 102.Because word line 101 just can form grid element with active region 102 overlapping parts, the word line part of therefore " passing by " non-active region, " passing by " deep groove capacity from the top promptly is called as the grid 104 of passing by on one's way.

Grid will be passed by from other the top of deep groove capacity of memory cell (memory cell) because pass by on one's way; Pass by on one's way simultaneously grid and deep groove capacity all is electrical components; Therefore will be at the construction one deck insulation system between grid and the deep groove capacity of passing by on one's way, with the electric insulation of guaranteeing to pass by on one's way between grid and deep groove capacity.As shown in Figure 1, insulation system 105 is promptly as the usefulness of grid 104 with deep groove capacity 103 insulation of passing by on one's way.It should be noted that in Fig. 1, only to illustrate an insulation system 105 and omitted other incomplete insulation systems 105, but this does not represent other deep groove capacity top naked structure.

When the grid of passing by on one's way will be from shallow trench isolation from passing by with the top of deep groove capacity, on order, normally make earlier shallow trench isolation from, form deep groove capacity, the definition insulation system of grid of passing by on one's way again then.Fig. 2-8 is the step that illustration defines the insulation system of the grid of passing by on one's way traditionally.At first, as shown in Figure 2, the shallow trench isolation that in base material 201, completes forms deep groove capacity 203 again after 202.The step that forms deep groove capacity 203 can be the profile that etches the electric capacity groove earlier, enlarges the channel capacitor bottom then and becomes ampuliform to promote internal surface area, sets up other parts subsequently, for example neck oxide layer, backfill electric conducting material, for example silicon again.After forming deep groove capacity 203, begin to carry out the technology that various required ion trap is injected (figure does not show), cleaning, high tempering etc.Secondly, as shown in Figure 3, on base material 201, form cushion oxide layer 204 and silicon nitride layer 205 all sidedly in regular turn, so that use photoresistance to define the position of insulation system afterwards.Afterwards; As shown in Figure 4; Form anti-reflecting layer (BARC) 206; And the photoresistance 207 that uses a patterning defines the position of the insulation system of the grid of passing by on one's way, this moment photoresistance 207 should cover accurately shallow trench isolation from 202 with channel capacitor 203 on, have correct position with the insulation system of the grid of guaranteeing to pass by on one's way.

And then, as shown in Figure 5, utilize etching method to remove the anti-reflecting layer 206 and silicon nitride layer 205 of part.Then, as shown in Figure 6, remove remaining photoresistance 207 and stay required silicon nitride layer 205 and cushion oxide layer 204 with anti-reflecting layer 206, silicon nitride layer 205 is the usefulness as hard mask at this moment.Come again, as shown in Figure 7, utilize silicon nitride layer 205 as hard mask, remove the pad oxide 204 that is not covered by silicon nitride layer 205 via etching.Then, as shown in Figure 8, form a grid oxic horizon (figure does not show), and setting up grid 210 on the grid oxic horizon and on silicon nitride layer 205, setting up the grid 220 of passing by on one's way according to known mode.At this moment, in theory, grid 220 this moment of passing by on one's way promptly should the position on deep groove capacity 203.In other words, the silicon nitride layer 205 that is not removed among Fig. 7 is the insulation system 221 as the grid 220 of passing by on one's way with pad oxide 204.Grid 210 then is used for controlling channel capacitor 203 and constitutes a memory cell (memory cell).Grid 220 has good insulation performance with the irrelevant channel capacitor 203 in its below so insulation system 221 is promptly guaranteed to pass by on one's way, and avoids short circuit, in order to avoid influence the normal running of dynamic random access memory.

Yet; Aforesaid technology not only need use an extra photomask to define the position of insulation system 221; And will be with insulation system 221; That is silicon nitride layer 205 and pad oxide 204, the top that several nothings aligning deviations are defined in deep groove capacity 203 (misalignment) also is the very work of difficulty.In addition, before insulation system 221 is accomplished, can not produce enough protective effects, make the shallow trench isolation that exposes avoid the injury that technologies such as ion trap injection, cleaning, high tempering possibly cause with deep groove capacity 203 from 202.

So be badly in need of wanting a kind of novel method that forms insulation system; Not only can exempt use extra photomask define the insulation system position step, need not solve when setting up insulation system must with the problem of accurately aiming between the deep groove capacity that has existed; Before insulation system is accomplished, also can protect base material, shallow trench isolation from not coming out, avoid involving and injury when what setting up of other zones possibly receive in the process with deep groove capacity makes.

Summary of the invention

The present invention is in the novel method of the insulation system that provides a kind of grid that is formed for passing by on one's way; That is; Before the hard mask that removes definition deep trench opening, just directly use the opening conduct of groove to set up the foundation of first oxide layer and first silicon layer, and become insulation system in the future.So; Save the cost of using extra photomask to define the insulation system position on the one hand; On the other hand; First oxide layer and first silicon layer can be precisely defined on the deep trench with the mode of autoregistration (self-alignment) again, have automatically solved the problem of aiming between insulation system and channel capacitor, have ideally reached the requirement that insulation system can accurately cover deep groove capacity.Also have, before insulation system was accomplished, cushion oxide layer, first silicon layer made base material, shallow trench isolation from not coming out with deep trench with first oxide layer.So can also protect base material, shallow trench isolation from not receiving the injury possible in the process of setting up in other zones, can once solve aforesaid three problems with deep trench.

The method of formation autoregistration provided by the present invention (self-align) insulation system at first, provides a base material.Comprise the deep trench of filling up silicon in the base material and leave in abutting connection with the shallow trench isolation of deep trench.Comprise cushion oxide layer and hard mask on the base material in regular turn, wherein cushion oxide layer has defined the opening of deep trench with hard mask.Next carries out an oxidation step, makes the surface of silicon form first oxide layer, and wherein first oxide layer is promptly as required insulation system.Then, in opening, form first silicon layer to cover first oxide layer.Come again, remove hard mask.Afterwards, on insulation system, set up the grid of passing by on one's way.

The present invention provides a kind of semiconductor structure again; It comprises and is arranged in base material, fill up silicon deep trench, be positioned at silicon face and as first oxide layer of insulation system, be positioned at first silicon layer on first oxide layer, be positioned at the grid on first silicon layer and leave with the shallow trench isolation of deep trench adjacency.

Description of drawings

Fig. 1 illustration word line is passed by not by the deep groove capacity of its control from the top that shallow trench isolation leaves.

Fig. 2-8 illustration defines the step of the insulation system of the grid of passing by on one's way traditionally.

The present invention of Fig. 9-17 illustration forms a preferred embodiment of insulation system method.

One preferred embodiment of Figure 18 illustration semiconductor structure of the present invention.

Description of reference numerals

301 base materials, 310 deep trench

311 silicon, 312 composite layers

314 openings, 315 first oxide layers

316 second oxide layers, 317 insulation systems

320 shallow trench isolations are from 331 cushion oxide layer

332 hard mask 333 gate oxides

340 silicon layers, 341 first silicon layers

350A, 350B, 350C, 350D word line

351/354 grid

352,353 grids of passing by on one's way

400 semiconductor structures

Embodiment

The invention reside in the novel method of autoregistration (self-align) insulation system that a kind of grid that is formed for passing by on one's way is provided; Wherein both exempted and used extra photomask to define the position of insulation system, solve the problem of aiming between insulation system and deep groove capacity in the lump; Simultaneously shallow trench isolation leaves and also can not come out with deep groove capacity before insulation system is accomplished; The shallow trench isolation that can effectively protect exposure is from avoiding the injury of technologies such as ion trap injection, cleaning, high tempering with deep groove capacity, and then can significantly promote the yield of the technology of dynamic random access memory (DRAM) etc.

The present invention of Fig. 9-17 illustration forms a preferred embodiment of insulation system method.At first, as shown in Figure 9, a base material 301 is provided.Comprise the deep trench 310 of filling up silicon 311 usefulness in the base material 301 as electric capacity, and in abutting connection with the shallow trench isolation of deep trench 310 from 320.Comprise cushion oxide layer 331 and hard mask 332 on the base material 301 in regular turn.Depending on the circumstances or the needs of the situation, can further comprise a composite layer 312 between silicon 311 in the deep trench 310 and the base material 301, the composite layer of for example being made up of oxide-nitride thing-oxide (ONO) is used for being used as capacitance dielectric layer.In addition, can also comprise other structure in the deep trench 310, for example doleiform bottom (bottle bottom) or neck oxide layer.

Generally speaking, base material 301 can be semiconductor base material, for example silicon.Hard mask 332 can be made up of nitride, nitrogen oxide, carbide or its composite bed, for example silicon nitride, silicon oxynitride, carborundum etc.331 of cushion oxide layer comprise Si oxide.In a preferred embodiment of the invention, shallow trench isolation is formed on before the deep trench 310 from 320.For example, on base material 301, define shallow trench isolation from 320 earlier according to traditional trench isolation process.Then, utilize photoresistance and etching step to define the hard mask 332 of patterning, and the base material 301 of eating thrown part, cushion oxide layer 331 and shallow trench isolation form deep trench 310 from 320, make that having shallow trench isolation to leave 320 between the deep trench 310 is positioned at wherein.Deep trench 310 forms the back, can further enlarge the deep groove capacity bottom becomes ampuliform and sets up other parts, neck oxide layer for example, and backfill electric conducting material again, for example silicon 311, to accomplish the making of deep trench 310.So far, be all those skilled in the art and know, do not add to give unnecessary details at this.But it should be noted that from etching deep groove 310 1 until accomplish deep groove capacity the time, all do not remove hard mask 332.

Owing to be positioned at cushion oxide layer 331 and hard mask 332, the opening 314 that has definition deep trench 310 jointly on the base material 301.Therefore the present invention keeps the purpose of hard mask 332, is saving another step photomask reaching self aligned purpose, that is directly uses the opening 314 of deep trench 310 to define to be used to the position of insulation system of grid of passing by on one's way.

Secondly, shown in figure 10, if when being formed with composite layer 312 in the deep trench 310, remove the composite layer 312 that exposes in advance.For example, if composite layer 312 is made up of oxide-nitride thing-oxide, can use the condition of hot phosphoric acid to remove composite layer.

Next, please refer to Figure 11, carry out an oxidation step, the surface oxidation of silicon 311 in the deep trench 310 is formed first oxide layer 315.The usefulness that these first oxide layers 315 are about to as the SI semi-insulation structure.It can use thermal oxidation method to form first oxide layer 315, for example uses dry type thermal oxidation method or wet type thermal oxidation method to form first oxide layer 315.Preferred person, first oxide layer 315 protects base material 301, deep trench 310 to leave 320 with shallow trench isolation with contiguous cushion oxide layer 331.

Then, in opening 314, form silicon layer 340 to cover first oxide layer 315.Silicon layer 340 can be to use the formed amorphous silicon of chemical vapour deposition technique, polysilicon or its combination.The method that forms silicon layer 340 can be, and is shown in figure 12, for example uses chemical vapour deposition technique to make comprehensive conformal of silicon layer 340 cover on first oxide layer 315 and the hard mask 332.Then, shown in figure 13, the flatening process that re-uses chemico-mechanical polishing etc. removes unnecessary silicon layer 340, makes the silicon layer 341 of winning cover the hard mask 332 of first oxide layer 315 and part.After chemico-mechanical polishing, preferred person, first silicon layer 341 can from the side-looking angle, form asymmetric U-shaped structure on first oxide layer 315.The thickness of first silicon layer 341 can be between .

Because the inventive method is the hard mask 332 that keeps definition groove 310; And the opening 314 that directly uses groove 310 is set up first oxide layer 315 and first silicon layer 341; And as the insulation system of the required grid that is used to pass by on one's way in the future; So save on the one hand and re-used the step that an additional light mask defines the insulation system position, under the inducing of silicon 311, first oxide layer 315 can be precisely defined on the groove 310 with self aligned mode again on the other hand; Solved follow-up insulation system and the problem of before having aimed between deep groove capacity automatically, perfectly having reached insulation system needs the accurately requirement of covering groove electric capacity.

Come again, shown in figure 14, remove hard mask 332.If hard mask 332 is made up of nitride, can use hot phosphoric acid to remove hard mask 332.So stay 331 of cushion oxide layer on base material 301,315 of first silicon layer 341 and first oxide layers are on deep trench 310.

After removing hard mask 332, can look the needs of product technology, carry out the modification and the program in other logic element zones on the base material 301, for example steps such as high-temperature technology, cleaning, ion trap injection or annealing.Because pad oxide 331 also is retained on the base material 301; And first silicon layer 341 and first oxide layer 315 the position on deep trench 310; Therefore not only can make base material 301, deep trench 310 leave 320 respectively and can not come out, can also effectively protect base material 301, deep trench 310 can not receive possible the involving and injury in modification of other zones from 320 with shallow trench isolation with shallow trench isolation.But it should be noted that first silicon layer 341 after annealing of other regional modification such as well region or cleaning, may with injury the sacrifice of certain degree arranged and dwindle and oxidation because of involving.

And then, shown in figure 15, remove the original cushion oxide layer 331 in base material 301 surfaces, and expose base material 301.The method that removes cushion oxide layer 331 can be used fluorine-containing etchant, and for example hydrogen fluoride or oxide etching buffer solution (BOE, Buffer oxidation etchant) or the like remove cushion oxide layer 331.Removing the first oxidized silicon layer 341 and first oxide layer 315 that cushion oxide layer 331 also can remove part simultaneously, so first silicon layer 341 and first oxide layer 315 are dwindled.

Continue, shown in figure 16, carry out at least one high temperature oxidation process; On the base material 301 that exposes, form the preferred oxide 333 of another layer quality; In order to preparing required gate dielectric, and in the lump first silicon layer 341 is converted into second oxide layer 316, and becomes the part of insulation system 317.Because other logic element zones (figure does not show) or electrostatic protection element district (figure does not show) on base material 301 also need gate dielectric; For example; Use repeatedly step of thermal oxidation in different zones, to form thickness different oxidation thing layer respectively with the local step that removes repeatedly; So in other logic regions on the base material 301 or electrostatic protection element district when forming thickness different oxidation thing; Being used as the oxide 333 of the gate dielectric of the grid of controlling deep groove capacity just follows these step of thermal oxidation or is formed on the base material 301 at last again; First silicon layer 341 then is converted into second oxide layer 316 in the lump, and is completely integrated with the first previous oxide layer 315 and becomes the part of insulation system 317.After having considered that all can produce oxidation, can remove the processing step of oxidized silicon layer to first silicon layer; Can estimate the thickness of first silicon layer 341 in advance; In order to do making first silicon layer 341 before forming grid, can be converted into second oxide layer 316 fully; Or only have first silicon layer 341 of part to be converted into second oxide layer 316, and stayed first silicon layer 341 of part.If first silicon layer 341 is too thick, then before forming grid, have that most first silicon layer is not converted to second oxide layer 316 and the burden that causes subsequent etch; If first silicon layer 341 is too thin, then first silicon layer can too early be converted into second oxide layer 316 fully and can't be protected first oxide layer 315 of below.Figure 16 illustration first silicon layer be converted into the situation of second oxide layer fully.

Then, on base material 301, set up grid/word line, and arrange word line to pass by adjacent deep trench 310 from 320 top from shallow trench isolation.Can use known method to set up grid/word line.Shown in figure 17, each individual word line 350A, 350B, 350C, 350D just pass through from base material 301, deep trench 310 tops.On the one hand, the word line 350A/350D of part promptly becomes the grid 351/354 that is based upon on the gate oxide 333, and controls corresponding deep groove capacity 310 (deep groove capacities 310 of grid 352,353 belows of promptly passing by on one's way) respectively.On the other hand, from word line 350B, the 350C that deep trench 310 tops are passed by, promptly become and be based upon the so-called grid 352,353 of passing by on one's way on the insulation system 317.Because insulation system 317 is clipped in deep trench 310, the grid 352 of passing by on one's way, between 353; Add that insulation system 317 is made up of first oxide layer 315 and 316 of second oxide layers at least, so insulation system 317 becomes deep trench 310 and the grid 352 of passing by on one's way, the superior isolation structure between 353.

So the present invention provides a kind of semiconductor structure 400 again.Shown in figure 18, semiconductor structure 400 comprises base material 401, deep trench 410, first oxide layer 420, first silicon layer 430, grid 440 and shallow trench isolation from 450.Deep trench 410 is arranged in base material 401, and fills up silicon 411.Be positioned at first oxide layer 420 on silicon 411 surface, promptly as the usefulness of this insulation.First silicon layer 430 is positioned on first oxide layer 420.In addition, grid 440 is positioned on first silicon layer 430.Shallow trench isolation leaves 450 in abutting connection with deep trench 410.The mode that forms semiconductor structure 400 can be as previously mentioned, so no longer repetition.

Because the inventive method is deliberately to keep the hard mask that defines the deep trench opening, and before the hard mask that removes the definition deep trench, just directly uses the opening conduct of deep trench to set up the foundation of first oxide layer and first silicon layer, and become insulation system in the future.So; Save the cost of using extra photomask to define the insulation system position on the one hand; On the other hand; First oxide layer and first silicon layer can be precisely defined on the deep trench with self aligned mode again, have automatically solved between insulation system and deep groove capacity, the alignment issues between insulation system and active region, have ideally reached the requirement that insulation system can accurately cover deep groove capacity.Also have; Before insulation system is accomplished; Hard mask, cushion oxide layer, first silicon layer and first oxide layer make base material, shallow trench isolation from not coming out with deep trench, so can also protect base material, shallow trench isolation from not receiving possible injury in other regional modification with deep trench jointly.

The above is merely the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.

Claims (18)

1. the formation method of an insulation system comprises:

One base material is provided; Comprise the deep trench of filling up silicon in this base material and leave with a shallow trench isolation of this deep trench adjacency; Comprise the cushion oxide layer of a patterning and the hard mask of a patterning on this base material in regular turn, wherein the hard mask of the cushion oxide layer of this patterning and this patterning defines an opening of this deep trench jointly;

Carry out an oxidation step, make the surface that fills in this silicon in this deep trench form one first oxide layer, wherein this first oxide layer is as an insulation system;

In this opening, form one first silicon layer, it covers this first oxide layer; And

Remove this hard mask,

Wherein this first silicon layer is transformed into one second oxide layer that merges with this first oxide layer fully.

2. method as claimed in claim 1, wherein this hard mask comprises nitride, nitrogen oxide, carbide or above-mentioned person's combination in any.

3. method as claimed in claim 1, wherein this oxidation step is a step of thermal oxidation.

4. method as claimed in claim 1 wherein forms this first silicon layer and covers this first oxide layer and comprises in this opening:

This first silicon layer of comprehensive formation;

Carry out chemico-mechanical polishing to remove this first silicon layer on this hard mask, make this first silicon layer cover this first oxide layer.

5. method as claimed in claim 1, wherein this first silicon layer comprises amorphous silicon.

6. method as claimed in claim 1, wherein this first silicon layer comprises polysilicon.

7. method as claimed in claim 1, wherein the thickness of this first silicon layer be 50

-400

8. method as claimed in claim 1 wherein uses hot phosphoric acid to remove this hard mask.

9. method as claimed in claim 1 also comprises before removing this hard mask:

This base material is carried out high-temperature technology.

10. method as claimed in claim 1 also comprises:

Remove this first silicon layer that this cushion oxide layer removes part simultaneously, and expose this base material.

11., wherein use the fluorine containing etchant agent to remove this cushion oxide layer like the method for claim 10.

12., after removing this cushion oxide layer, also comprise like the method for claim 10:

Form a grid oxic horizon, it is positioned on the base material of this exposure.

13., wherein use step of thermal oxidation to form this grid oxic horizon like the method for claim 12.

14. method as claimed in claim 1 also comprises:

Form a grid, it is positioned on this first oxide layer.

15. method as claimed in claim 1, wherein this shallow trench isolation is before being formed at this deep trench.

16. method as claimed in claim 1 wherein also comprises a composite layer between this silicon in this base material and this deep trench.

17. method as claimed in claim 1, wherein this insulation system as one pass by on one's way grid insulation system.

18. the formation method of an insulation system comprises:

One base material is provided; Comprise the deep trench of filling up silicon in this base material and leave with a shallow trench isolation of this deep trench adjacency; Comprise the cushion oxide layer of a patterning and the hard mask of a patterning on this base material in regular turn, wherein the hard mask of the cushion oxide layer of this patterning and this patterning defines an opening of this deep trench jointly;

Carry out an oxidation step, make to fill in the surperficial oxidized of this silicon in this deep trench and form one first oxide layer that wherein this first oxide layer is as an insulation system;

In this opening, form one first silicon layer, it covers this first oxide layer; And

Remove this hard mask.

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