CN116110920A - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents
Method for manufacturing semiconductor structure and semiconductor structure Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure positioned between two adjacent active areas and an insulating layer positioned on the active areas, and the thickness of the isolation structure is different from that of the insulating layer; forming a buffer layer on a substrate; forming a first mask layer on the buffer layer; performing ion implantation treatment on the substrate by utilizing the first mask layer to form a deep well region; removing the first mask layer and the buffer layer; according to the method, the buffer layer is formed on the substrate, so that the buffer layer covers the isolation structure and the insulating layer simultaneously, reflection difference of the isolation structure and the insulating layer to light can be eliminated, namely, the influence of the reflection difference on exposure is eliminated, uniformity control of critical dimension of a photoetching process is realized, uniformity of ion implantation is guaranteed, uniformity of full well capacity of pixels is improved, and irregular noise is reduced.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the rapid development of ultra-large-scale integration technology, complementary metal oxide semiconductor image sensors (CMOS Image Sensor, CIS) have been developed rapidly in recent years because they can integrate a/D (analog/digital) conversion, signal processing, automatic gain control, precision amplification, and storage functions within a single chip, greatly reducing system complexity and cost.
However, in the related art, the CIS device has a problem in that the difference of the full well capacity between pixels is large and irregular noise is significant.
Disclosure of Invention
In view of the foregoing, a main object of the present application is to provide a method for manufacturing a semiconductor structure and a semiconductor structure, which are used for solving the technical problems of the semiconductor structure that the difference of full well capacity between pixels is large and irregular noise is obvious.
In order to achieve the above purpose, the technical scheme of the application is realized as follows:
the embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure positioned between two adjacent active areas and an insulating layer positioned on the active areas, and the thickness of the isolation structure is different from that of the insulating layer;
forming a buffer layer on the substrate;
forming a first mask layer on the buffer layer;
performing ion implantation treatment on the substrate by utilizing the first mask layer to form a deep well region;
and removing the first mask layer and the buffer layer.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, the material of the buffer layer is different from the material of the insulating layer and the material of the isolation structure, and the material of the buffer layer has a reflective capability.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, the material of the buffer layer includes silicon nitride or silicon oxynitride.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, the material of the buffer layer is different from the material of the insulating layer and the material of the isolation structure, and the material of the buffer layer does not have a reflective capability.
In the method for manufacturing the semiconductor structure provided by the embodiment of the application, the method further comprises the following steps:
forming a reflective layer on the buffer layer;
removing the reflecting layer after removing the first mask layer and before removing the buffer layer;
the forming a first mask layer on the buffer layer includes:
a first mask layer is formed over the reflective layer.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, the material of the buffer layer includes any one of epitaxial silicon, monocrystalline silicon, and polycrystalline silicon.
In the method for manufacturing a semiconductor structure provided in the embodiments of the present application, the thickness of the buffer layer is greater than or equal to 30 nm and less than or equal to 150 nm.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, before forming the first mask layer, the method further includes:
the surface of the buffer layer remote from the substrate is planarized.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, after removing the first mask layer and before removing the buffer layer, the method further includes:
forming a second mask layer on the buffer layer;
performing ion implantation treatment on the substrate by utilizing the second mask layer to form a first interval region;
and removing the second mask layer.
In the method for manufacturing a semiconductor structure provided in the embodiment of the present application, the conductivity type of the ions in the first spacer region is different from the conductivity type of the ions in the deep well region.
Embodiments of the present application also provide a semiconductor structure fabricated according to the above-described method.
According to the manufacturing method of the semiconductor structure, the buffer layer is formed on the substrate, so that the buffer layer covers the isolation structure and the insulating layer at the same time, reflection difference of the isolation structure and the insulating layer to light can be eliminated, namely, influence of the reflection difference on exposure is eliminated, uniformity control of critical dimensions of a photoetching process is achieved, uniformity of ion implantation is guaranteed, uniformity of full well capacity of pixels is improved, and irregular noise is reduced.
Drawings
FIG. 1a is a schematic diagram of a related art substrate;
FIG. 1b is a schematic diagram of a first mask layer according to the related art;
FIG. 1c is a schematic diagram of a related art stack of a first mask layer and a substrate;
fig. 2 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
FIG. 3a is a schematic diagram of the basic structure of each component in the manufacturing process of the substrate according to the embodiment of the present application;
FIG. 3b is a schematic diagram showing the basic structure of each component in the manufacturing process of the substrate according to the embodiment of the present application;
FIG. 3c is a schematic diagram of the basic structure of each component in the manufacturing process of the substrate according to the embodiment of the present application;
FIG. 3d is a schematic diagram of the basic structure of each component in the manufacturing process of the substrate according to the embodiment of the present application;
FIG. 4a is a schematic diagram of the basic structure of each component in the manufacturing process of the semiconductor structure according to the embodiment of the present application;
FIG. 4b is a schematic diagram showing a basic structure of each component in the manufacturing process of the semiconductor structure according to the embodiment of the present application;
fig. 4c is a schematic diagram of a basic structure of each component in the manufacturing flow of the semiconductor structure according to the embodiment of the present application;
fig. 4d is a schematic diagram of a basic structure of each component in the manufacturing flow of the semiconductor structure according to the embodiment of the present application;
FIG. 5a is a schematic diagram illustrating the basic structure of each component in another manufacturing process of a semiconductor structure according to an embodiment of the present disclosure;
FIG. 5b is a schematic diagram showing a basic structure of each component in another manufacturing process of the semiconductor structure according to the embodiment of the present application;
FIG. 5c is a schematic diagram of a basic structure of each component in another manufacturing process of the semiconductor structure according to the embodiment of the present application;
FIG. 5d is a schematic diagram of a basic structure of each component in another manufacturing process of the semiconductor structure according to the embodiment of the present application;
fig. 6 is another flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Detailed Description
The technical scheme of the application is further elaborated below with reference to the drawings in the specification and the specific embodiments. In the drawings, the dimensions and thicknesses of components depicted in the drawings are not to scale for clarity and ease of understanding and description.
With the rapid development of CIS devices, there is a need to increase the photosensitivity of CIS devices, i.e., to increase the full-well capacity (Full Well Capacity, FWC) of CIS devices, which refers to the ability of individual pixels to collect electrons. In order to effectively increase the full well capacity of the CIS device, high-energy deep well ions need to be implanted into the substrate 10 having a smaller implantation size, as shown in fig. 1a, which is a schematic view of a related art substrate, the substrate 10 includes a plurality of active regions A1, an isolation structure 105 located between two adjacent active regions A1, and an insulating layer 102 located on the active regions A1, wherein the thickness of the isolation structure 105 is different from the thickness of the insulating layer 102, such that the reflective capabilities of the isolation structure 105 and the insulating layer 102 for light are different.
As the energy of the implanted ions increases, the thickness of the first mask layer 20 used for blocking the non-implanted region in the implantation process is also higher and higher, as shown in fig. 1b, which is a schematic diagram of a first mask layer of the related art, the first mask layer 20 includes a plurality of first openings 201, and the first openings 201 correspond to the regions of ion implantation. To increase photosensitivity, the pitch of the pixels is getting smaller, which results in an aspect ratio of the first mask layer 20 as high as 15:1. In order to enhance the isolation capability between pixels, the CIS device may employ a shallow trench isolation technology, which results in that a portion of the first mask layer 20 is on the insulating layer 102 of the active area A1, and a portion of the first mask layer 20 is on the isolation structure 105 between two adjacent active areas A1, specifically, as shown in fig. 1c, which is a schematic diagram of stacking the first mask layer and the substrate in the related art, and in fig. 1c, only the first opening 201 on the first mask layer 20 is shown for clarity and understanding.
In one embodiment, during the formation of the plurality of openings 201 on the first mask layer 20, due to the difference in the reflective power of the light between the isolation structure 105 and the insulating layer 102, the widths of the adjacent first openings 201 formed on the isolation structure 105 and on the insulating layer 102 are different, with continued reference to fig. 1c, m representing the width of the adjacent first openings 201 on the insulating layer 102, m ranging from 195 nanometers to 200 nanometers, n representing the width of the adjacent first openings 201 on the isolation structure 105, and n ranging from 243 nanometers to 248 nanometers. That is, the width m of the first mask layer 20 on the insulating layer 102 may be smaller than the width n of the first mask layer 20 on the isolation structure 105, and there is a risk of peeling during high-energy ion implantation; and a larger deviation between the pitches of the adjacent first openings 201 may cause a difference in the ion implantation amounts of the adjacent pixels, and eventually may cause a larger difference in the full well capacities between the pixels, increasing irregular noise. Embodiments of the present application address the above-described deficiencies.
As shown in fig. 2, a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application is shown, where the method for manufacturing a semiconductor structure includes:
s1, providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure between two adjacent active areas and an insulating layer on the active areas, and the thickness of the isolation structure is different from that of the insulating layer;
s2, forming a buffer layer on the substrate;
s3, forming a first mask layer on the buffer layer;
s4, performing ion implantation treatment on the substrate by utilizing the first mask layer to form a deep well region;
s5, removing the first mask layer and the buffer layer.
It can be appreciated that, in the embodiment of the application, the buffer layer is formed on the substrate, so that the buffer layer covers the isolation structure and the insulating layer simultaneously, and the whole surface of the buffer layer is provided, so that the reflection difference of the isolation structure and the insulating layer to light can be eliminated, namely, the influence of the reflection difference on exposure is eliminated, thereby reducing the deviation between the intervals of adjacent first openings, realizing the uniformity control of the critical dimension of the photoetching process, ensuring the uniformity of ion implantation, improving the uniformity of the full well capacity of the pixels, and reducing irregular noise.
It can be appreciated that by adopting the manufacturing method provided by the embodiment of the application, the influence of the reflection difference of the isolation structure and the insulating layer on the pattern of the first mask layer can be eliminated, the process window of the yellow light process can be improved, the uniformity of distribution of a plurality of first openings on the first mask layer can be realized, and the manufacturing method is applicable to development of thick photoresist processes with smaller implantation size.
In one embodiment, the step S1 of providing a substrate includes:
providing a semiconductor substrate;
forming an insulating layer on the semiconductor substrate;
forming a sacrificial layer on the insulating layer;
forming a groove between two adjacent active areas, wherein the groove penetrates through the sacrificial layer, the insulating layer and part of the semiconductor substrate;
filling an isolation structure in the groove;
and removing the sacrificial layer.
Specifically, as shown in fig. 3a to 3d, referring to fig. 3a, which is a schematic diagram of a basic structure of each component in a manufacturing process of a substrate provided in an embodiment of the present application, an insulating layer 102 is formed on a semiconductor substrate 101 by using a deposition process, and then a sacrificial layer 103 is formed on the insulating layer 102 by using a deposition process; the material of the semiconductor substrate 101 is, for example, silicon, the material of the insulating layer 102 is, for example, silicon oxide, and the material of the sacrificial layer 103 is, for example, silicon nitride. Wherein, in the direction from the semiconductor substrate 101 to the insulating layer 102, the thickness h1 of the insulating layer 102 is greater than or equal to 4.5 nm and less than or equal to 6.0 nm, for example, the thickness h1 of the insulating layer 102 is 5.3 nm. Next, please refer to fig. 3b, which is a schematic diagram of a basic structure of each component in the manufacturing process of the substrate according to the embodiment of the present application, wherein a trench 104 is formed between two adjacent active areas A1 by using an etching process, wherein the trench 104 penetrates through the sacrificial layer 103, the insulating layer 102 and a portion of the semiconductor substrate 101; it should be noted that the trench 104 is formed herein to enhance the isolation capability between pixels.
Next, please refer to fig. 3c, which is a schematic diagram of a basic structure of each component in the manufacturing process of the substrate according to an embodiment of the present application, wherein the trench 104 is filled with the isolation structure 105; the material of the isolation structure 105 is, for example, silicon oxide. Wherein, in the direction from the semiconductor substrate 101 to the insulating layer 102, a vertical distance h2 from a side of the isolation structure 105 away from the semiconductor substrate 101 to a side of the semiconductor substrate 101 close to the insulating layer 102 is greater than or equal to 17.0 nm and less than or equal to 18.0 nm, for example, h2 is equal to 17.5 nm.
In one embodiment, the filling the isolation structure 105 in the trench 104 includes: the trench 104 is filled with an isolation structure 105 using a high aspect ratio process or a high density plasma process. In particular, in the conventional technology, a high-density plasma process is generally used for filling, but when an integrated circuit is developed to a 55 nm technology node, the high-density plasma process cannot meet the filling requirement of a small-sized trench, so when the trench size is smaller than 55 nm, the high-aspect ratio process needs to be used for filling instead of the high-density plasma process. The high aspect ratio process is a non-plasma chemical vapor deposition thermal oxidation process, which requires that the trench have a specific morphology, such as a U-shaped trench of a specific angle.
Next, referring to fig. 3d, a basic structure diagram of each component in the manufacturing process of the substrate provided in the embodiment of the present application is shown, and an etching process is used to remove the sacrificial layer 103, so as to obtain the substrate 10. The thickness h3 of the isolation structure 105 is different from the thickness h1 of the insulating layer 102, specifically, the thickness h3 of the isolation structure 105 is greater than the thickness h1 of the insulating layer 102, which is because a part of the isolation structure 105 is filled in the semiconductor substrate 101, resulting in different reflective capacities of the isolation structure 105 and the insulating layer 102 for light. In addition, the isolation structure 105 has a protrusion toward a side away from the semiconductor substrate 101 with respect to the insulating layer 102, because a portion of the redundant material needs to be reserved on the isolation structure 105 to prevent the isolation structure 105 in the trench 104 from being over etched in a subsequent etching process.
In one embodiment, the material of the buffer layer is different from the material of the insulating layer 102 and the material of the isolation structure 105, and the material of the buffer layer has a reflective capability. Specifically, the material of the buffer layer includes silicon nitride or silicon oxynitride, i.e., the material of the buffer layer may be silicon nitride or silicon oxynitride, or may be other materials with reflective capability.
It will be appreciated that the buffer layer material cannot be the same material as the insulating layer 102 or the isolation structure 105, since it is subsequently required to remove the buffer layer, otherwise the depth of removal is not well controlled.
Specifically, please refer to fig. 4a to fig. 4d, which are schematic diagrams of basic structures of components in the manufacturing process of the semiconductor structure provided in the embodiment of the present application, firstly refer to fig. 4a, which is a schematic diagram of basic structures of components in the manufacturing process of the semiconductor structure provided in the embodiment of the present application, a buffer layer 30 is formed on a substrate 10, that is, the buffer layer 30 is used to cover an isolation structure 105 and an insulating layer 102 of the substrate 10 at the same time, so as to eliminate the reflection difference of light by the isolation structure 105 and the insulating layer 102. The material of the buffer layer 30 in this embodiment is different from the material of the insulating layer 102 and the material of the isolation structure 105, and the material of the buffer layer 30 has a reflective capability. Wherein, in the direction from the semiconductor substrate 101 to the insulating layer 102, the thickness h4 of the buffer layer 30 is greater than or equal to 30 nm and less than or equal to 150 nm, for example, 85 nm. The buffer layer 30 may be prepared by a thermal oxidation process.
Next, please refer to fig. 4b, which is a schematic diagram of a basic structure of each component in the manufacturing process of the semiconductor structure according to the embodiment of the present application, a spin-coating or a doctor-blading process is adopted to form a first mask layer 20 on the buffer layer 30, the pattern of the first mask layer 20 may refer to fig. 1b, the first mask layer 20 includes a plurality of first openings 201, and the first openings 201 correspond to ion implantation regions; then, ion implantation is performed in the plurality of first openings 201 to form a deep well region C1 (fig. 4C), where the implanted ions are N-type ions, such as arsenic ions. Wherein, in the direction from the semiconductor substrate 101 to the insulating layer 102, the thickness of the first mask layer 20 is greater than or equal to 3000 nm and less than or equal to 3400 nm, for example 3200 nm.
It should be noted that, the plurality of first openings 201 on the first mask layer 20 are formed by an exposure process, and since the buffer layer 30 eliminates the reflection difference of the isolation structure 105 and the insulating layer 102 to light, that is, eliminates the influence of the reflection difference on exposure, thereby reducing the deviation between the pitches of adjacent first openings 201, realizing the uniformity control of the critical dimension of the photolithography process, ensuring the uniformity of ion implantation, improving the uniformity of the full well capacity of the pixels, and reducing the irregular noise.
Next, please refer to fig. 4c, which is a schematic diagram of a basic structure of each component in the manufacturing process of the semiconductor structure according to an embodiment of the present application, wherein the first mask layer 20 is stripped by an ashing process or the first mask layer 20 is removed by a wet etching process.
Next, please refer to fig. 4d, which is a schematic diagram illustrating a basic structure of each component in the manufacturing process of the semiconductor structure according to the embodiment of the present application, wherein the buffer layer 30 is removed by an etching process to restore the device structure. The subsequent thin photoresist process has less influence on the light reflection difference, so that the manufacturing method of the semiconductor structure provided by the embodiment of the application is not needed, and the subsequent process is not related to the invention point of the application and is not described in detail herein.
In one embodiment, the material of the buffer layer 30 is different from the material of the insulating layer 102 and the material of the isolation structure 105, and the material of the buffer layer 30 has no reflective capability, i.e. the buffer layer 30 may also be made of a material having no reflective capability to light, and in particular, please refer to fig. 5a to 5d, which are schematic basic structure diagrams of components in another manufacturing process of the semiconductor structure provided in the embodiments of the present application.
In this embodiment, the manufacturing method further includes: forming a reflective layer 40 on the buffer layer 30 (fig. 5a is a schematic view of the basic structure of each component in another manufacturing process of the semiconductor structure provided in the embodiment of the present application); after removing the first mask layer 20 and before removing the buffer layer 30, removing the reflective layer 40; the forming the first mask layer 20 on the buffer layer 30 includes: a first mask layer 20 is formed on the reflective layer 40. Specifically, since the buffer layer 30 of the present embodiment is made of a material that has no light reflection capability, the reflective layer 40 needs to be formed on the buffer layer 30 again, so that the light reflection capability of the buffer layer 30 is improved.
In this embodiment, the material of the buffer layer 30 includes any of epitaxial silicon, monocrystalline silicon, and polycrystalline silicon, i.e., the buffer layer 30 may be formed by epitaxial growth, such as Molecular Beam Epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV/CVD), and atmospheric pressure and reduced pressure epitaxy (ATM RP Epi). The material of the reflective layer 40 may be silicon oxide.
In the present embodiment, as shown in fig. 5a, the thickness h5 of the reflective layer 40 is greater than or equal to 4.5 nm and less than or equal to 6.0 nm, for example, 5.3 nm.
It should be noted that, referring to fig. 5a, the manufacturing process of the present embodiment first forms the buffer layer 30 on the substrate 10, that is, the buffer layer 30 is used to cover the isolation structure 105 and the insulating layer 102 of the substrate 10 at the same time, so as to eliminate the reflection difference of the light by the isolation structure 105 and the insulating layer 102; a reflective layer 40 is then formed on the buffer layer 30 to enhance the reflective power of the buffer layer 30 to light. The process for preparing the buffer layer 30 may be a thermal oxidation process, and the process for preparing the reflective layer 40 may be a thermal oxidation process.
Next, please refer to fig. 5b, which is a schematic diagram of a basic structure of each component in another manufacturing process of the semiconductor structure provided in the embodiment of the present application, a spin-coating or a doctor-blading process is adopted to form a first mask layer 20 on the reflective layer 40, the pattern of the first mask layer 20 may refer to fig. 1b, the first mask layer 20 includes a plurality of first openings 201, and the first openings 201 correspond to ion implanted regions; then, ion implantation is performed in the plurality of first openings 201 to form a deep well region C1 (fig. 5C), and the implanted ions are N-type ions, such as arsenic. Wherein, in the direction from the semiconductor substrate 101 to the insulating layer 102, the thickness of the first mask layer 20 is greater than or equal to 3000 nm and less than or equal to 3400 nm, for example 3200 nm.
It should be noted that, the plurality of first openings 201 on the first mask layer 20 are formed by an exposure process, and since the buffer layer 30 eliminates the reflection difference of the isolation structure 105 and the insulating layer 102 to light, that is, eliminates the influence of the reflection difference on exposure, thereby reducing the deviation between the pitches of adjacent first openings 201, realizing the uniformity control of the critical dimension of the photolithography process, ensuring the uniformity of ion implantation, improving the uniformity of the full well capacity of the pixels, and reducing the irregular noise.
Next, please refer to fig. 5c, which is a schematic diagram illustrating a basic structure of each component in another manufacturing process of the semiconductor structure according to an embodiment of the present application, wherein the first mask layer 20 is stripped by an ashing process or the first mask layer 20 is removed by a wet etching process.
Next, referring to fig. 5d, a basic structure diagram of each component in another manufacturing process of the semiconductor structure provided in the embodiment of the present application is shown, and an etching process is used to remove the reflective layer 40 and the buffer layer 30, so as to restore the device structure. The subsequent thin photoresist process has less influence on the light reflection difference, so that the manufacturing method of the semiconductor structure provided by the embodiment of the application is not needed, and the subsequent process is not related to the invention point of the application and is not described in detail herein.
In one embodiment, the method of removing the buffer layer 30 includes a dry etching process and/or a wet etching process. I.e., the buffer layer 30 may be removed by a dry etching process and then the residue after the dry etching may be removed by a wet etching process.
In one embodiment, before forming the first mask layer 20, the method further comprises: the surface of the buffer layer 30 remote from the substrate 10 is flattened. Specifically, the surface of the buffer layer 30 remote from the substrate 10 may be polished using a polishing process, so that the surface of the buffer layer 30 remote from the substrate 10 is flat.
It can be appreciated that, since the isolation structure 105 has a protrusion toward a side away from the semiconductor base 101 relative to the insulating layer 102, a side of the substrate 10 close to the buffer layer 30 is not flat, and an upper surface of the buffer layer 30 formed on the substrate 10 is also not flat, so that a height of the first mask layer 20 formed on the buffer layer 30 is uneven, and by flattening a surface of the buffer layer 30 away from the substrate 10, a height of the first mask layer 20 formed on the buffer layer 30 can be uniform, thereby avoiding an influence on a photolithography process.
In one embodiment, after removing the first mask layer 20 and before removing the buffer layer 30, the method further comprises: forming a second mask layer on the buffer layer, and performing ion implantation treatment on the substrate by using the second mask layer to form a first interval region; and removing the second mask layer. The thickness of the second mask layer is 3600 nm or 2000 nm in the direction from the semiconductor substrate to the insulating layer. The second mask layer comprises a plurality of second openings, the second openings correspond to ion implantation areas, orthographic projection of the second openings on the substrate and orthographic projection of the first openings on the substrate are not overlapped, namely, the first interval area and the deep well area are not overlapped.
It should be noted that, in the semiconductor substrate, not only deep well ions for collecting electrons but also deep well ions with other functions, such as ions with a spacer function, are required to be implanted, and the spacer ions also need to be used for shielding the non-implanted region by using a thick photoresist, so that a buffer layer is also required to eliminate the reflection difference between the isolation structure and the insulating layer, that is, a process of using a thick photoresist process should be performed before removing the buffer layer.
In one embodiment, the conductivity type of ions within the first spacer region is different from the conductivity type of ions within the deep well region C1. The conductivity type of the ions in the first spacer is P-type, and the ions in the first spacer are boron ions, for example.
In one embodiment, as shown in fig. 6, another flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application is provided, where the method for manufacturing a semiconductor structure includes:
s10, providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure between two adjacent active areas and an insulating layer on the active areas, and the thickness of the isolation structure is different from that of the insulating layer;
s11, forming a buffer layer on the substrate;
s12, forming a reflecting layer on the buffer layer;
s13, forming a first mask layer on the reflecting layer, and performing ion implantation treatment on the substrate by using the first mask layer to form a deep well region;
s14, removing the first mask layer;
s15, forming a second mask layer on the reflecting layer, and performing ion implantation treatment on the substrate by using the second mask layer to form a first interval region;
s16, removing the second mask layer;
s17, forming a third mask layer on the reflecting layer, and performing ion implantation treatment on the substrate by using the third mask layer to form a second interval region;
s18, removing the third mask layer;
s19, forming a fourth mask layer on the reflecting layer, and performing ion implantation treatment on the substrate by using the fourth mask layer to form a third interval region;
s20, removing the fourth mask layer;
s21, removing the reflecting layer and the buffer layer.
In steps S15, S17, and S19, different ions are implanted, and the implanted regions are also different. The thicknesses of the second mask layer and the third mask layer are 3600 nanometers, and the thickness of the fourth mask layer is 2000 nanometers.
In one embodiment, the materials of the fourth mask layer, the third mask layer, the second mask layer and the first mask layer are all photoresist.
The embodiment of the present application further provides a semiconductor structure manufactured by the above-mentioned manufacturing method of a semiconductor structure, for example, an image sensor, and the specific manufacturing method and flow are shown in fig. 2 to 6 and related description, which are not repeated here. In one embodiment, the semiconductor structure provided herein is, for example, a front-illuminated image sensor, i.e., a metal wiring layer is located between a color filter and a photodiode.
In summary, the method for manufacturing a semiconductor structure provided in the embodiments of the present application includes: providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure positioned between two adjacent active areas and an insulating layer positioned on the active areas, and the thickness of the isolation structure is different from that of the insulating layer; forming a buffer layer on a substrate; forming a first mask layer on the buffer layer; performing ion implantation treatment on the substrate by utilizing the first mask layer to form a deep well region; removing the first mask layer and the buffer layer; according to the method, the buffer layer is formed on the substrate, the buffer layer covers the isolation structure and the insulating layer simultaneously, reflection difference generated by the isolation structure and the insulating layer to light can be eliminated, namely, the influence of the reflection difference on exposure is eliminated, uniformity control of key dimensions of a photoetching process is achieved, uniformity of ion implantation is guaranteed, uniformity of full well capacity of pixels is improved, irregular noise is reduced, and the technical problems that the difference of the full well capacity among pixels is large and the irregular noise is obvious in a semiconductor structure are solved.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application.
Claims (11)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active areas, an isolation structure positioned between two adjacent active areas and an insulating layer positioned on the active areas, and the thickness of the isolation structure is different from that of the insulating layer;
forming a buffer layer on the substrate;
forming a first mask layer on the buffer layer;
performing ion implantation treatment on the substrate by utilizing the first mask layer to form a deep well region;
and removing the first mask layer and the buffer layer.
2. The method according to claim 1, wherein a material of the buffer layer is different from a material of the insulating layer and a material of the isolation structure, and wherein the material of the buffer layer has a reflective capability.
3. The method of claim 2, wherein the buffer layer comprises silicon nitride or silicon oxynitride.
4. The method according to claim 1, wherein a material of the buffer layer is different from a material of the insulating layer and a material of the isolation structure, and the material of the buffer layer has no reflective capability.
5. The method of manufacturing a semiconductor structure of claim 4, further comprising:
forming a reflective layer on the buffer layer;
removing the reflecting layer after removing the first mask layer and before removing the buffer layer;
the forming a first mask layer on the buffer layer includes:
a first mask layer is formed over the reflective layer.
6. The method according to claim 4, wherein the material of the buffer layer comprises any one of epitaxial silicon, single crystal silicon, and polycrystalline silicon.
7. The method of claim 1, wherein the buffer layer has a thickness greater than or equal to 30 nanometers and less than or equal to 150 nanometers.
8. The method of manufacturing a semiconductor structure of claim 1, wherein prior to forming the first mask layer, the method further comprises:
the surface of the buffer layer remote from the substrate is planarized.
9. The method of manufacturing a semiconductor structure of claim 1, wherein after removing the first mask layer and before removing the buffer layer, the method further comprises:
forming a second mask layer on the buffer layer;
performing ion implantation treatment on the substrate by utilizing the second mask layer to form a first interval region;
and removing the second mask layer.
10. The method of claim 9, wherein the conductivity type of ions in the first spacer region is different from the conductivity type of ions in the deep well region.
11. A semiconductor structure manufactured according to the method of any one of claims 1 to 10.
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