CN101656228A - Method for forming semiconductor structure and insulation structure - Google Patents
Method for forming semiconductor structure and insulation structure Download PDFInfo
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- CN101656228A CN101656228A CN200810131012A CN200810131012A CN101656228A CN 101656228 A CN101656228 A CN 101656228A CN 200810131012 A CN200810131012 A CN 200810131012A CN 200810131012 A CN200810131012 A CN 200810131012A CN 101656228 A CN101656228 A CN 101656228A
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Abstract
The invention provides a method for forming a semiconductor structure and an insulation structure. The method for forming the insulation structure comprises: firstly, providing a substrate the insideof which has shallow trench isolation; secondly, forming a patterned mask layer on the surface of the substrate; thirdly, etching the substrate through the patterned mask layer to form a first deep trench and a second deep trench as well as a first undercut and a second undercut on two oppositely sides of the shallow trench isolation respectively; fourthly, filling silicon in part of the first deep trench and the second deep trench respectively; and finally, filling up the first and second trenches with an insulating material to form the insulation structure.
Description
Technical field
The present invention relates to the formation method of a kind of semiconductor structure and insulation system wherein.Particularly relate to a kind of the have semiconductor structure of the grid of passing by on one's way and pass by on one's way gate insulator structure (passing gate isolation, formation method PGI).
Background technology
In the development of dynamic random access memory (DRAM) technology, in order to increase the component density on the chip, can arrange word line (word line) " to pass by " deep groove capacity that other are not subjected to this word line control from the top, with effective raising integrated level (integration).Fig. 1 is that the illustration word line is from other circuit layouts that not passed by by the deep groove capacity top of this word line control.As shown in Figure 1, on this layout patterns, each word line 101 strides across from (STI) top from active region 102, deep groove capacity 103 and shallow trench isolation, wherein when not making deep groove capacity 103 as yet, have only shallow trench isolation in the substrate from (STI) and active region 102, therefore non-shallow trench isolation is active region 102 from the zone of (STI).Because word line 101 and active region 102 overlapping parts just can form grid element, the word line part of therefore " passing by " non-active region, " passing by " deep groove capacity from the top promptly is called as the grid 104 of passing by on one's way.
Grid will be passed by from other the top of deep groove capacity of memory cell (memory cell) because pass by on one's way, pass by on one's way simultaneously grid and deep groove capacity all is electrical components, therefore will be at the construction one deck insulation system between grid and the deep groove capacity of passing by on one's way, with the electric insulation of guaranteeing to pass by on one's way between grid and deep groove capacity.As shown in Figure 1, insulation system 105 is promptly as the usefulness of grid 104 with deep groove capacity 103 insulation of passing by on one's way.It should be noted that in Fig. 1, only to illustrate insulation system 105 and omitted other incomplete insulation systems 105, but this does not represent other deep groove capacity top naked structure.
When the grid of passing by on one's way will be from shallow trench isolation from passing by with the top of deep groove capacity, on order, normally make earlier shallow trench isolation from, form deep groove capacity, the definition insulation system of grid of passing by on one's way again then.Fig. 2-8 is the step that illustration defines the insulation system of the grid of passing by on one's way traditionally.At first, as shown in Figure 2, in substrate 111, complete shallow trench isolation after 112, form deep groove capacity 113 again.The step that forms deep groove capacity 113 can be the profile that etches the electric capacity groove earlier, enlarges the channel capacitor bottom then and becomes ampuliform to promote internal surface area, sets up other parts subsequently, for example neck oxide layer, backfill electric conducting material, for example silicon again.Behind the deep groove capacity 113 to be formed, begin to carry out the technology that various required ion trap is injected (figure does not show), cleaning, high annealing etc. again.Secondly, as shown in Figure 3, in substrate 111, form cushion oxide layer 114 and silicon nitride layer 115 all sidedly in regular turn, so that use photoresist to define the position of insulation system afterwards.Afterwards, as shown in Figure 4, form anti-reflecting layer (BARC) 116, and the photoresist 117 that uses patterning defines the position of the insulation system of the grid of passing by on one's way, this moment photoresist 117 should cover accurately shallow trench isolation from 112 with channel capacitor 113 on, have correct position with the insulation system of the grid of guaranteeing to pass by on one's way.
And then, as shown in Figure 5, utilize etching method to remove the anti-reflecting layer 116 and silicon nitride layer 115 of part.Then, as shown in Figure 6, remove remaining photoresist 117 and stay required silicon nitride layer 115 and cushion oxide layer 114 with anti-reflecting layer 116, silicon nitride layer 115 is the usefulness as hard mask at this moment.Come again, as shown in Figure 7, utilize silicon nitride layer 115, remove the cushion oxide layer 114 that is not covered via etching by silicon nitride layer 115 as hard mask.Then, as shown in Figure 8, form grid oxic horizon (figure does not show), and setting up grid 110 on the grid oxic horizon and on silicon nitride layer 115, setting up the grid 120 of passing by on one's way according to known mode.At this moment, in theory, the grid of passing by on one's way promptly should be positioned on the deep groove capacity 113 for 120 this moments.In other words, silicon nitride layer 115 that is not removed among Fig. 7 and cushion oxide layer 114 are the insulation system 121 as the grid 120 of passing by on one's way.Grid 110 then is used for controlling channel capacitor 113 and constitutes memory cell (memory cell).Grid 120 has good insulation performance with the channel capacitor 113 that its below has nothing to do so insulation system 121 is promptly guaranteed to pass by on one's way, and avoids short circuit, in order to avoid influence the normal running of dynamic random access memory.
Yet, aforesaid technology not only needs to use extra photomask to define the position of insulation system 121, and will be with insulation system 121, that is silicon nitride layer 115 and cushion oxide layer 114, does not have almost that to aim at the top that deviation is defined in deep groove capacity 113 (misalignment) also be a very difficult job.In addition, before insulation system 121 is finished, can not produce enough protective effects, the shallow trench isolation that make to expose from 112 with deep groove capacity 113 avoid such as technologies such as ion trap injection, cleaning, high annealing the injury that may cause.
So be badly in need of wanting a kind of new method that forms insulation system; not only can exempt use extra photomask define the insulation system position step, need not solve when setting up insulation system must with the problem of accurately aiming between the deep groove capacity that has existed; at the bottom of also can protecting group before insulation system is finished, shallow trench isolation is from making it can not come out with deep groove capacity, avoid when involving and injury that setting up of other zones may be subjected in the process.
Summary of the invention
So the present invention proposes a kind of semiconductor structure and the formation method of insulation system wherein.Insulation system of the present invention is to be built in the deep trench with undercut feature; make remove protecting group at the bottom of, shallow trench isolation is when the patterned mask layer used with deep groove capacity; can the be further more extended formation of undercut feature cavity, and convenient directly as the be electrically connected opening of external contact plunger with the electric conducting material that is arranged in deep groove capacity.
The present invention at first proposes a kind of semiconductor structure, comprise substrate, wherein has first deep trench, second deep trench and be sandwiched in first deep trench and second deep trench between shallow trench isolation from, partially filled first electric conducting material in first deep trench, partially filled second electric conducting material in second deep trench, be positioned at first insulating barrier on first electric conducting material, it fills up first electric conducting material of first deep trench and exposed portion, and first insulating barrier wherein is as insulation system, be positioned at second insulating barrier on second electric conducting material, fill up second deep trench and exposed portion second electric conducting material, and second insulating barrier wherein is also as insulation system, be positioned at first insulating barrier and second insulating barrier one of at least on grid structure, cover substrate, first insulating barrier, the dielectric layer of second insulating barrier and grid structure, be arranged in dielectric layer and be electrically connected first contact plunger of first electric conducting material, and be arranged in dielectric layer and be electrically connected second contact plunger of second electric conducting material.
The present invention secondly propose a kind of in semiconductor structure the formation method of insulation system.Substrate at first is provided, and have in the substrate shallow trench isolation from.Secondly, form patterned mask layer at substrate surface.Then, by patterned mask layer etching substrate, forming first deep trench and second deep trench respectively from relative both sides in shallow trench isolation, and first undercutting of adjacent pattern mask layer and second undercutting.Continue the partially filled silicon of difference in first deep trench and second deep trench.Come again, fill up first deep trench and second deep trench formation insulation system with first insulating material.Afterwards, remove patterned mask layer, make the outstanding substrate surface of the insulating material of winning, and first undercutting and second undercutting are enlarged formation first cavity (void) and second cavity respectively.
Description of drawings
Fig. 1 illustration word line from shallow trench isolation from the top pass by not by the deep groove capacity of its control.
Fig. 2-8 is the step that illustration defines the insulation system of the grid of passing by on one's way traditionally.
The present invention of Fig. 9-16 illustration is arranged in the formation method of semiconductor structure insulation system.
Description of reference numerals
101 word lines, 102 active regions
103 deep groove capacities 104 grid of passing by on one's way
105 insulation systems, 110 grids
111 substrates, 112 shallow trench isolations from
113 deep groove capacities, 114 cushion oxide layer
115 silicon nitride layers, 116 anti-reflecting layers
117 photoresists 120 grid of passing by on one's way
121 insulation systems
201 substrates of 200 semiconductor structures
202/203 undercutting, 210 mask layers
211 first openings, 212 second openings
213 patterning layings, 214 patterned buffer layer
215 patterned oxide layer, 221 first deep trench
222 second deep trench, 230 shallow trench isolations from
240 electric conducting materials, 241 first electric conducting materials
242 second electric conducting materials, 250 insulating material
261 first cavities, the first deep trench extension area
262 second cavities, the second deep trench extension area
251 first insulation systems, 252 second insulation systems
270 grids 271/272 grid of passing by on one's way
280 contact plungers, 281 first contact plungers
282 second contact plungers, 290 dielectric layers
Embodiment
The invention provides a kind of semiconductor structure and form the wherein method of insulation system.When forming insulation system of the present invention; except need not use extra photomask define the step of this insulation system position, also need not solve when setting up insulation system must with the problem of accurately aiming between the deep groove capacity that has existed, also can protecting group before insulation system is finished at the bottom of, shallow trench isolation is from making it can not come out with deep groove capacity.In addition, insulation system of the present invention is to be built in the deep trench with undercut feature, make follow-up when setting up semiconductor element, can the be further more extended formation of undercut feature cavity, and convenient directly as the be electrically connected opening of external contact plunger with the electric conducting material that is arranged in deep groove capacity.
The present invention at first provides a kind of formation method that is used for the semiconductor structure insulation system.The present invention of Fig. 9-16 illustration is arranged in the formation method of semiconductor structure insulation system.At the beginning, as shown in Figure 9, provide substrate 201.Be coated with patterned mask layer 210 in the substrate 201.Patterned mask layer 210 also has first opening 211 and second opening 212.First opening 211 defines the position that is arranged in substrate 201 first deep trench 221, and similarly, second opening 212 defines the position that is arranged in substrate 201 second deep trench 222.In addition, between first deep trench 221 and second deep trench 222, accompany shallow trench isolation from 230.
The method that forms first deep trench 221 and second deep trench 222 in substrate 201 can be as described below.At first, in substrate 201, be pre-formed shallow trench isolation from 230.Secondly, form the position that patterned mask layer 210 define first deep trench 221 and second deep trench 222, be preferably and be arranged in shallow trench isolation from 230 both sides and overlapping from 230 parts with shallow trench isolation on substrate 201 surfaces.Afterwards, come etching substrate 201 and part shallow trench isolation from 230, can in 230 relative substrate on two sides 201, form first deep trench 221 and second deep trench 222 respectively at shallow trench isolation by patterned mask layer 210.In the etching process that carries out first deep trench 221 and second deep trench 222, can suitably regulate and control etch recipe, with in substrate 201 surfaces,, and be one of inventive features of this case near the position formation undercutting 202/203 of patterned mask layer 210.
In substrate 201, form after first deep trench 221 and second deep trench 222, can use electric conducting material and insulating material to fill up first deep trench 221 and second deep trench 222 respectively.For example, as shown in figure 10, at first with electric conducting material 240, silicon for example, comprehensive covering substrate 201 is also filled first deep trench 221 and second deep trench 222 simultaneously.Then, more as shown in figure 11, for example use chemico-mechanical polishing (CMP) to remove unnecessary electric conducting material 240, make difference filled conductive material 241/242 in the win deep trench 221 and second deep trench 222.Depending on the circumstances or the needs of the situation, remove unnecessary electric conducting material 240 and can also remove patterned oxide layer 215 in the lump simultaneously.Come again, more as shown in figure 12, carry out first etch-back, make the electric conducting material 241/242 of filling appropriate depth in the win deep trench 221 and second deep trench 222 respectively.
Subsequently, in first deep trench 221 and second deep trench 222, part forms first insulating material 250, to prepare required insulation system 251/252.And the preferred embodiment that forms insulation system 251/252 in first deep trench 221 and second deep trench 222 can be as described below.At first, as shown in figure 13, at first with first insulating material 250, Si oxide for example, use high density plasma CVD (High Density Plasma Chemical Vapor Deposition, HDP-CVD) or comprehensive covering substrate 201 such as plasma assist type chemical vapour deposition (CVD) (PECVD) deposition process of etc.ing also insert first deep trench 221 and second deep trench 222 simultaneously.Then, more as shown in figure 14, carry out second etch-back, remove first insulating material 250 partly, make the insulation system 251/252 of filling appropriate depth in the win deep trench 221 and second deep trench 222 respectively.So far, so the present invention is used for insulation system 251/252 shaping of semiconductor structure.
Next, just can remove remaining patterned mask layer 210, as shown in figure 15 patterning laying 213 and patterned buffer layer 214.Because the surface of insulation system 251/252 is high than substrate 201 surfaces, so after removing remaining patterned mask layer 210, promptly can make insulation system 251/252 give prominence to substrate 201 surfaces.
Then, can carry out suitable semiconductor technology, in substrate 201, setting up other semiconductor regions, for example logic region, or semiconductor element, grid for example is to finish required semiconductor structure.Suitable semiconductor technology can be ion trap technology, threshold voltage (threshold voltage) injection technology, delustering causes resist technology, cleaning, grid structure technology and metal silicide technology or the like.In addition, as shown in figure 16, can also use dielectric layer 290 to cover each semiconductor element, for example substrate 201, first insulation system 251, second insulation system 252 and grid 270 re-use contact plunger 280/281/282 and pass dielectric layer 290 to form the electrical connection of semiconductor element.
It should be noted that, when when carrying out above-mentioned semiconductor technology, technologies such as its various etching of following, cleaning are the further undercutting 202/203 in the expanded substrate 201 also, and first cavity 261 and second cavity 262 of formation self-aligned (self-alighment) in first deep trench 221 and second deep trench 222, also can be considered the first deep trench extension area 261 and the second deep trench extension area 262 that connect first deep trench 221 and second deep trench 222 respectively, it is again another inventive features of the application.Owing to enlarge the part surface that 261 and second cavity 262, first cavity that forms also can expose electric conducting material 241/242 by original undercutting 202/203, so first contact plunger 281 can directly be electrically connected with electric conducting material 241/242 smoothly with easily with second contact plunger 282.
Comprehensive above-mentioned explanation, the present invention will constitute the word line arrangement of grid and pass by the top of first deep trench 221 and second deep trench 222 and form the grid of passing by on one's way (passing gate) 271/272.Since insulation system 251/252 self-aligned (self-alighment) be arranged in first deep trench 221 and second deep trench, 222 electric conducting materials 241/242 above, so insulation system 251/252 can be as passing by on one's way gate insulator structure (passing gate isolation, PGI) usefulness is guaranteed the electric insulation of grid and electric conducting material 241/242.So, but the present invention just self-aligned form the required gate insulator structure (PGI) of passing by on one's way, and arrange word line " to pass by " deep groove capacity that other are not subjected to this word line control from the top, with the integrated level of effective raising memory.
Via the inventive method, can make a kind of semiconductor structure 200, as shown in figure 16.Semiconductor structure 200 of the present invention comprises substrate 201, first deep trench 221, second deep trench 222, shallow trench isolation from 230, first electric conducting material 241, second electric conducting material 242, first insulation system 251, second insulation system 252, the first deep trench extension area (extension region), 261, the second deep trench extension area 262, grid 270, pass by on one's way grid 271/272, first contact plunger 281, second contact plunger 282 and dielectric layer 290.
Shallow trench isolation is arranged in substrate 201 from 230, and is located between first deep trench 221 and second deep trench 222.Insert electric conducting material and insulation system in each deep trench 221/222, therefore when the grid 271/272 of passing by on one's way is passed by the top of first deep trench 221 and second deep trench 222, first insulation system 251 and second insulation system 252 can guarantee to pass by on one's way first electric conducting material 241 and second electric conducting material 242 of grid 271/272 and below kept good electric insulation.In addition, insulation system 251/252 is other also be connected with self-aligned in deep trench, be positioned at the first deep trench extension area 261 and the second deep trench extension area 262 above the electric conducting material, make first contact plunger 281 that passes dielectric layer 290 can directly be electrically connected with first electric conducting material 241 and 242 generations of second electric conducting material with second contact plunger 282.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (20)
1. the formation method of an insulation system comprises:
Substrate is provided, has patterned mask layer in this substrate, comprise in this substrate first deep trench, contiguous this first deep trench of partly filling up silicon and second deep trench of filling up silicon and the shallow trench isolation between this first deep trench and this second deep trench from, and this patterned mask layer has first opening and second opening of this second deep trench of this first deep trench of definition, wherein has first undercutting and second undercutting that is close to this patterned mask layer in addition respectively in this first deep trench and this second deep trench inside, this substrate;
First insulating material is partly filled up this first deep trench and this second deep trench to form this insulation system; And
Remove this patterned mask layer, make this first insulating material give prominence to this substrate surface, and this first undercutting and this second undercutting form first cavity and second cavity respectively.
2. method as claimed in claim 1, wherein this patterned mask layer comprises patterning laying and patterned buffer layer.
3. method as claimed in claim 2, wherein this patterning laying and this patterned buffer layer comprise nitride respectively.
4. method as claimed in claim 1 wherein comprises oxide in this first insulating material.
5. method as claimed in claim 1 wherein uses high density plasma CVD to deposit this first insulating material.
6. method as claimed in claim 1 wherein uses the chemical vapour deposition (CVD) of plasma assist type to deposit this first insulating material.
7. method as claimed in claim 1 also comprises after removing this patterned mask layer:
Semiconductor technology is carried out in this substrate.
8. method as claimed in claim 7, wherein this semiconductor technology is selected from ion trap technology, threshold voltage injection technology, delustering causes resist technology, cleaning, grid structure technology and metal silicide technology.
9. method as claimed in claim 7, wherein this semiconductor technology more enlarges this first cavity and this second cavity.
10. method as claimed in claim 1, wherein this insulation system is as passing by on one's way the gate insulator structure.
11. a semiconductor structure comprises:
Substrate, wherein have first deep trench, second deep trench with in abutting connection with the shallow trench isolation of this first deep trench and this second deep trench from;
First electric conducting material is partially filled in this first deep trench;
Second electric conducting material is partially filled in this second deep trench;
First insulating barrier is positioned on this first electric conducting material, fills up this first deep trench and this first electric conducting material of exposed portion;
Second insulating barrier is positioned on this second electric conducting material, fills up this second deep trench and this second electric conducting material of exposed portion, and wherein this first insulating barrier and second insulating barrier are as insulation system;
Grid, be positioned at this first insulating barrier and this second insulating barrier one of at least on;
Dielectric layer covers this substrate, this first insulating barrier, this second insulating barrier and this grid;
First contact plunger is arranged in this dielectric layer and is electrically connected this first electric conducting material; And
Second contact plunger is arranged in this dielectric layer and is electrically connected this second electric conducting material.
12. as the semiconductor structure of claim 11, wherein this insulation system is as passing by on one's way the gate insulator structure.
13. as the semiconductor structure of claim 11, wherein this first insulating barrier comprises the single insulating material layer.
14. as the semiconductor structure of claim 11, wherein this first insulating barrier comprises oxide.
15. as the semiconductor structure of claim 11, wherein this second insulating barrier comprises the single insulating material.
16. as the semiconductor structure of claim 11, this second insulating barrier comprises oxide.
17. as the semiconductor structure of claim 11, wherein this semiconductor structure has the first deep trench extension area and the second deep trench extension area in addition and is arranged in this substrate and is connected this first deep trench and this second deep trench respectively.
18. as the semiconductor structure of claim 11, wherein via this this first electric conducting material of first deep trench extension area exposed portion, via this this second electric conducting material of second deep trench extension area exposed portion.
19. the formation method of an insulation system comprises:
Substrate is provided, and have in this substrate shallow trench isolation from;
Form patterned mask layer in this substrate surface;
By this this substrate of patterned mask layer etching, to form first deep trench and second deep trench respectively from relative both sides in this shallow trench isolation;
Part is inserted electric conducting material respectively in this first deep trench and this second deep trench;
Fill up this first deep trench and this second deep trench with first insulating material; And
Remove this patterned mask layer.
20. method as claim 19, wherein forming this first deep trench and this second deep trench forms in first undercutting and second undercutting this substrate below this patterned mask layer simultaneously, make when removing this patterned mask layer that this first undercutting and this second undercutting form first cavity and second cavity respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810131012A CN101656228A (en) | 2008-08-19 | 2008-08-19 | Method for forming semiconductor structure and insulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810131012A CN101656228A (en) | 2008-08-19 | 2008-08-19 | Method for forming semiconductor structure and insulation structure |
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| Publication Number | Publication Date |
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| CN101656228A true CN101656228A (en) | 2010-02-24 |
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| CN200810131012A Pending CN101656228A (en) | 2008-08-19 | 2008-08-19 | Method for forming semiconductor structure and insulation structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987406A (en) * | 2017-05-31 | 2018-12-11 | 三星电子株式会社 | Integrated circuit device and the method for manufacturing the integrated circuit device |
| CN111834285A (en) * | 2020-07-20 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
-
2008
- 2008-08-19 CN CN200810131012A patent/CN101656228A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987406A (en) * | 2017-05-31 | 2018-12-11 | 三星电子株式会社 | Integrated circuit device and the method for manufacturing the integrated circuit device |
| CN108987406B (en) * | 2017-05-31 | 2023-09-26 | 三星电子株式会社 | Integrated circuit device and method of manufacturing the same |
| CN111834285A (en) * | 2020-07-20 | 2020-10-27 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN111834285B (en) * | 2020-07-20 | 2024-05-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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Open date: 20100224 |