KR20080000785A - Method of manufacturing a nand type flash memory device - Google Patents

Abstract

A method for manufacturing a NAND type flash memory device is provided to simplify an effective field oxide film forming process by controlling an EFH(Effective Field Oxide Height) on the NAND type flash memory device using both dry and wet etching processes. A semiconductor substrate(300) having a cell region and a peripheral circuit region is provided. A tunnel oxide film(320), a floating gate(330), and a nitride film are formed on a device region in the cell region. A planarized HDP(High Density Plasma) oxide film(350) is formed on a field region in the cell and peripheral circuit regions. The HDP oxide film is removed to a lower portion of the floating gate using a wet etching process, and the nitride film is removed. The HDP oxide film and the floating gate are removed in the cell region by a dry etching process. The EFH of the HDP oxide film and a profile of the floating gate are controlled by the dry etching process.

Description

Method of manufacturing a NAND flash memory device

1A to 1F are cross-sectional views illustrating a method for forming a dual effective field oxide thickness (EFH) of a NAND flash memory device according to the prior art.

FIG. 2 is a transmission electron microscope (TEM) photograph showing a portion of a NAND flash memory device manufactured by a conventional dual effective field oxide film thickness forming method.

3A to 3D are cross-sectional views illustrating a method of forming a dual effective field oxide thickness (EFH) of a NAND flash memory device according to the present invention.

4 is a transmission electron microscope (TEM) photograph showing a portion of a NAND flash memory device manufactured by the dual effective field oxide film thickness forming method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

300, 400: semiconductor substrate 310: trench

      320, 410: tunnel oxide film 330, 420: floating gate

      340: nitride film 350, 430: HDP oxide film

360: mask

The present invention relates to a method for manufacturing a NAND flash memory device, and more particularly, to controlling a dual effective field oxide height (EFH) in a two-step process by dry etching after wet etching and at the same time interfering between devices ( interference) and a method of manufacturing a NAND flash memory device that can improve the phenomenon.

Information stored in a cell of a nonvolatile memory device such as a flash memory device is not destroyed even when the power supply is cut off. The flash memory device includes a tunnel oxide of a thin film formed on a silicon substrate, a floating gate, a control gate, and an insulator separating the two gates, and an effective field oxide thickness (EFH). ) To control the coupling ratio between the floating gate and the control gate.

1A to 1F are cross-sectional views illustrating a method for forming a dual effective field oxide thickness (EFH) of a NAND flash memory device according to the prior art.

First, referring to FIG. 1A, a semiconductor substrate 100 having a plurality of trenches 110 formed in a cell region and a periphery circuit region is an active region a and a field. Area (b). On the semiconductor substrate 100 of the device region a, a tunnel oxide film 120 made of a silicon oxide film (SiO ₂ ), a floating gate 130 made of a polysilicon film, and a silicon nitride film (SixNy) or a silicon oxynitride film (SiON) A nitride film 140 is formed. In the field region b, an HDP oxide film 150 planarized by a chemical mechanical polishing (CMP) process is formed after a high density plasma (HDP) gap-fill process.

Referring to FIG. 1B, an HDP oxide layer 150 having a thickness of 100 to 200 μm is formed on the floating gate 130 by wet etching using BOE (Buffered Oxide Etchant), and then 120 ° C. to 150 ° C. The nitride film 140 is removed by a high temperature phosphoric acid (H ₃ PO ₄ ) solution having a.

1C and 1D, a mask 160 is formed in a peripheral circuit region in a peripheral circuit region in order to prevent damage to the device region a of the semiconductor substrate 100 in the peripheral circuit region during gate etching. The HDP oxide layer 150 in the cell region is etched by a predetermined thickness by dry etching using the mask 160.

Referring to FIG. 1E, the HDP oxide layer 150 of the cell region and the peripheral circuit region may be formed through wet etching of a dielectric layer (not shown) cleaning process using a dilute hydrofluoric acid (HF) solution after the mask 160 is removed. ) Is etched by a predetermined thickness to finally define a dual effective field oxide thickness having a low effective field oxide thickness (EFH; d1) in the cell region and a relatively high effective field oxide thickness (EFH; d2) in the peripheral circuit region.

Referring to FIG. 1F, an oxide-nitride-oxide (Oxide-Nitride-Oxide) hereinafter referred to as 'ONO' is disposed on a floating gate 130 including an HDP oxide film 150 having dual effective field oxide thicknesses EFH d1 and d2. A dielectric film 170 made of &quot; &quot; is formed.

Although not shown, a control gate, which is a word line, is formed on the dielectric layer 170 to complete the gate.

FIG. 2 is a Transmission Electron Micrograph (TEM) image of a portion of a NAND flash memory device manufactured by a conventional dual effective field oxide film thickness forming method.

As shown, a tunnel oxide film 210 made of a silicon oxide film (SiO ₂ ) and a floating gate 220 made of a polysilicon film are formed on an element region of the semiconductor substrate 200. An HDP oxide film 230 made of a high density plasma silicon oxide film (SiO ₂ ) is formed on the field region where the trench (not shown) is formed. An ONO dielectric film 240 including an oxide film 240a / nitride film 240b / oxide film 240c is formed on the floating gate 220 and the HDP oxide film 230, and a capping polysilicon for control gate is formed thereon. The film 250 is formed.

Here, the EFH of the cell region is formed to be d3, and the floating gate 220 can be seen that both sides of the upper region A are formed in a vertical profile.

As such, the conventional dual EFH is controlled through wet etching using BOE, dry etching using a mask in the peripheral circuit region, and wet etching of the cleaning process before depositing the ONO dielectric film. Therefore, since there are three processes that are variables in the formation of the EFH, there are difficulties in controlling the EFH. In particular, the EFH control using the wet etching is applied to the pattern density even in one die due to the loading effect on the dense pattern of the cell region compared to the isolation pattern of the peripheral circuit region. As a result, a difference occurs in the EFH, causing a thickness variation of the ETH region.

In addition, due to the high integration of semiconductor devices, the spacing between devices becomes narrow in the process of forming a gate. In the conventional method of forming dual EFH, the floating gate is formed to have a vertical profile as shown in FIG. Since the distance between the word line and the word line is short, there is a problem in that interference between devices occurs.

An object of the present invention is to provide a method for manufacturing a NAND flash memory device which can simplify the effective oxide film thickness (EFH) control process, reduce thickness variation of the EFH region, and improve interference between devices.

In order to achieve the above object, a method of manufacturing a NAND flash memory device according to the present invention comprises the steps of: providing a semiconductor substrate having a cell region and a peripheral circuit region; Forming a tunnel oxide film, a floating gate, and a nitride film on the device region of the cell region, and forming a planarized HDP oxide film on the field region of the cell region and the peripheral circuit region; Removing the nitride layer after removing the HDP oxide layer to the lower portion of the floating gate by wet etching; And removing a predetermined portion of the HDP oxide layer and the floating gate in the cell region by dry etching.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3A to 3D are cross-sectional views illustrating a method of controlling dual effective oxide film thickness (EFH) of a NAND flash memory device according to the present invention.

First, referring to FIG. 3A, a plurality of trenches 310 are formed in a semiconductor substrate 300 including a cell region and a peripheral circuit region to define a device region a and a field region b. Here, the semiconductor substrate 300 is preferably a silicon (Si) substrate.

The tunnel oxide layer 320, the floating gate 330, and the nitride layer 340 are formed on the semiconductor substrate 300 in the device region a, and the HDP gap-fill is formed in the field region b. After the process, the planarized HDP oxide film 350 is formed by the CMP process.

The tunnel oxide layer 320 may be formed of a silicon oxide layer (SiO ₂ ) through a wet or dry oxidation process, or silicon oxide may be formed by a chemical vapor deposition (CVD) method, for example, low pressure chemical vapor deposition (LPCVD). It is deposited by a pressure CVD method to form a silicon oxide film (SiO ₂ ).

The floating gate 330 is formed of polysilicon by depositing polysilicon by the LPCVD method, and the nitride layer 340 is formed of silicon nitride (SixNy) or silicon oxynitride (SiON) by depositing nitride or oxide by the LPCVD method. To form).

The HDP oxide film 350 is formed of HDP SiO ₂ by depositing silicon oxide by a high density plasma method.

Referring to FIG. 3B, the HDP oxide film 350 is partially etched by wet etching using BOE having a mixing ratio of NH ₄ F and HF of 100: 1 to 300: 1, thereby allowing the HDP oxide film 350 to float. 100-200 mm 3 from the top surface of 330. Thereafter, the nitride film 340 is removed using a high temperature phosphoric acid (H ₃ PO ₄ ) solution having a temperature of 120 ° C. to 150 ° C. Therefore, EFH is primarily controlled by wet etching using the BOE.

Referring to FIG. 3C, a mask 360 is formed in the peripheral circuit region. The mask 360 is formed by applying a photo resist on the semiconductor substrate 300 including the floating gate 330 by spin caoting to form a photoresist film (not shown). The photo mask is positioned on the photoresist film, and then exposed and developed to form a photoresist pattern.

Referring to FIG. 3D, the HDP oxide film 350 of the cell region is partially etched by dry etching using the mask 360, and the EFH (d4) having a low thickness in the cell region is finally formed through the secondary control of the EFH. And EFH (d5) with high thickness in the peripheral circuit area is defined.

At this time, the floating gate 330a of the peripheral circuit region of the floating gate 330 has a vertical profile, but the floating gate 330b of the cell region is formed to have a rounded profile. That is, the profiles of the EFH (d4, d5) and the floating gate 330 of the HDP oxide film 350 are controlled by the dry etching.

The dry etching for secondary control of EFH is performed using a blanket etch process. That is, the floating gate 330 is etched without the etching barrier in a blanket state so that the HDP oxide film 350 has a target thickness of 100 to 300 Å from the upper surface of the semiconductor substrate 300 in the device region a. Therefore, the EFH (d4) of the cell region is controlled to a thickness of 100 to 300 m 3.

In order to minimize the loss of the polysilicon layer of the floating gate 330, the blanket etch uses a recipe having a high polysilicon selection ratio (10: 1 or more), and uses a high pressure and a low power. ) On condition.

That is, the blanket etch is performed under a pressure of 80 to 200 mTorr, the bias power is carried out at 100 to 500W or the source power is set to 100 to 600W.

In addition, the blanket etch is performed using argon gas (Ar gas) in a range of 0 to 100 sccm, using argon gas having a lower area than the conventional one.

As a result, the height of the floating gate 330b of the cell region is minimized while being etched to some extent in both directions, thereby forming the floating gate 330b having a round profile on both sides.

Finally, the mask 360 is removed after defining the dual effective field oxide thicknesses EFH d4 and d5.

Although not shown in the drawing, a control gate, which is a word line, is formed on the floating gate through an ONO dielectric film and a conductive film through a subsequent process to complete the gate.

Before the deposition of the ONO dielectric film, a cleaning process is preceded, and the cleaning process before the ONO dielectric film deposition is performed using a diluted hydrofluoric acid (HF) solution as a target for removing only 50 nm or less of the native oxide film.

As described above, the present invention forms a dual effective field oxide thickness by a two-step process using wet etching using BOE and dry etching of a blanket etch using a mask in the peripheral circuit region, thereby reducing the process variables in forming EFH. The thickness variation of the region can be reduced, and at the same time, the process of forming the EFH can be simplified.

According to the present invention, as the wet etching process for controlling the EFH is reduced by one cycle, the variation of the EFH according to the pattern density can be improved by reducing the loading effect on the high density pattern of the cell region compared to the isolation pattern of the peripheral circuit region.

In addition, in the prior art, the process time for etching HDP oxide was more than 500 "in order to form EFH during the cleaning process before depositing the ONO dielectric film. By reducing the Turn Around Time, the investment cost for wet etching equipment can be reduced.

4 is a transmission electron microscope (TEM) photograph showing a portion of a NAND flash memory device manufactured by the dual effective field oxide film thickness forming method according to the present invention.

As shown in the drawing, a floating gate including a tunnel oxide film 410 made of a silicon oxide film (SiO ₂ ) and a polysilicon film is formed on an element region of a semiconductor substrate 400 having a cell region by a manufacturing method according to the present invention. 420 is formed, and an HDP oxide film 430 made of a high density silicon oxide film (SiO ₂ ) is formed on the field region.

In this case, the effective field oxide thickness (EFH; d6) of the cell region is formed by wet etching using a blanket etch after wet etching using the BOE according to the present invention, and the floating gate 420 is formed by rounding both sides of the upper region B region. You can see that it has a profile.

As mentioned in FIG. 4, the floating gate 420 of the cell region is formed to have a rounded profile to reduce the overall cross-sectional area of the floating gate 420, thereby increasing the spacing between the word line and the word line of the cell region. The interference between devices can be improved.

Although the present invention has been described with respect to the preferred embodiment as described above, the present invention is not limited to this, and those skilled in the art to which the present invention pertains the claims and the detailed description of the invention and attached It is possible to carry out various modifications within the scope of the drawings and this also belongs to the scope of the present invention.

The present invention is a two-step process using wet etching using BOE and dry etching of a blanket etch using a mask in the peripheral circuit region to control the effective oxide film thickness (EFH) of the NAND flash memory device, thereby reducing the process parameters when forming EFH. The thickness variation of the region can be reduced, and at the same time, there is an effect of simplifying the EFH formation process.

The present invention has the effect of improving the inter-device interference of NAND flash memory devices by reducing the overall cross-sectional area of the floating gate by forming the floating gate of the cell region to have a rounded profile by a dry etching process using a blanket etch. .

In addition, the present invention has another effect of reducing the investment cost for the wet etching equipment by shortening the process TAT by removing only 50 nm or less of the natural oxide film in the cleaning process before depositing the ONO dielectric film.

Claims (15)

Providing a semiconductor substrate having a cell region and a peripheral circuit region; Forming a tunnel oxide film, a floating gate, and a nitride film on the device region of the cell region, and forming a planarized HDP oxide film on the field region of the cell region and the peripheral circuit region; Removing the nitride layer after removing the HDP oxide layer to the lower portion of the floating gate by wet etching; And A method of manufacturing a NAND flash memory device comprising removing a predetermined portion of an HDP oxide film and a floating gate in a cell region by dry etching. The method of claim 1, The effective field oxide thickness (EFH) of the HDP oxide film and the profile of the floating gate are controlled by the dry etching. The method of claim 1, Wherein the wet etching is performed such that the HDP oxide film is removed from the upper surface of the floating gate by a thickness of 100 to 200 microseconds. The method of claim 1, The wet etching method of manufacturing a NAND flash memory device using a buffered oxide etchant (BOE) in which the mixing ratio of NH ₄ F and HF is 100: 1 to 300: 1. The method of claim 1, And dry etching is performed such that the thickness of the HDP oxide film is 100 to 300 내지 target from the surface of the semiconductor substrate in the device region. The method of claim 1, And forming a low effective field oxide film thickness in the cell region and a high effective field oxide film thickness in the peripheral circuit region through dry etching after the wet etching. The method of claim 1, The dry etching is to form a NAND flash memory device having an effective field oxide film thickness of 100 ~ 300 GPa of the cell region. The method of claim 1, The dry etching is a method of manufacturing a NAND flash memory device performed by a blanket etch (Blanket Etch). The method of claim 8, The blanket etch method of manufacturing a NAND flash memory device using a recipe having a polysilicon selectivity higher than 10: 1. The method of claim 8, And said blanket etch is performed at high pressure and low power. The method of claim 10, And said blanket etch is carried out under a pressure of 80 to 200 mTorr. The method of claim 10, The blanket etch method is performed with a bias power of 100 to 500W or a source power of 100 to 600W. The method of claim 8, The blanket etch is a method of manufacturing a NAND flash memory device performed by argon gas (Ar gas) in the range of 0 to 100sccm. The method of claim 1, A method of manufacturing a NAND flash memory device after the dry etching, performing a cleaning process before depositing a dielectric film. The method of claim 14, The method of manufacturing a NAND flash memory device, wherein the cleaning process before the deposition of the dielectric film is performed using a hydrofluoric acid (HF) solution as a target for removing a native oxide film of 50 kΩ or less.

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