KR20070118348A - Manufacturing method of nonvolatile memory device - Google Patents

Abstract

Disclosed is a method of manufacturing a nonvolatile memory device in which a floating gate in which no void is generated on a sidewall of an isolation layer is formed. Protruding from the substrate while sufficiently filling the trench formed in the substrate, and forming the preliminary device isolation films having a width of the upper surface larger than the width of the bottom. Spacers are formed on sidewalls of the preliminary isolation layers. A wet etching process may be performed on the preliminary device isolation layers on which the spacers are formed to form device isolation layers having substantially vertical sides. A floating gate conductive film is formed while the space between the device isolation films is buried. The conductive film for the floating gate is etched to form a floating gate. A dielectric film is formed on the upper surface of the floating gate to have a substantially uniform thickness. A control gate is formed on the dielectric film. Accordingly, voids are not formed in the floating gate formed by burying polysilicon in the opening by forming a spacer on the sidewalls of the device isolation layer and wet etching the same so that the opening has a wide inlet.

Description

Method of manufacturing a non-volatile memory device

1 is a scanning electron micrograph showing a void formed inside a conventional floating gate.

2 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100 substrate 102 pad oxide film

104: hard mask 106: trench

108: active region 110: spare device separator

110a: device isolation layer 112: first opening

112a: second opening 120: spacer film

122 spacer 130 conductive film for floating gate

130a: floating gate 132: photoresist pattern

134: third opening 140: dielectric film

150: control gate

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device having a floating gate made of self-aligned polysilicon.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. This can be largely classified as a non-volatile (read-only memory) product that is non-volatile to maintain its state but has a slow input / output of data.

In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable and programmable ROM (EEPROM) or flash memory capable of electrically inputting / outputting data. The flash memory device has a structure for electrically controlling input and output of data by using F-N tunneling or channel hot electron injection.

As an example of the flash memory device, according to US Pat. No. 6,465,293, a method of manufacturing a flash memory cell includes providing a semiconductor substrate on which an isolation layer is formed, and forming an oxide layer on the isolation layer and the substrate. Forming an oxide pattern by patterning the oxide layer to expose the substrate in a portion where a floating gate is to be formed; sequentially forming a tunnel oxide layer and a first polysilicon layer on an entire upper surface thereof; Planarizing the first polysilicon layer until an oxide layer is exposed to form a floating gate, etching the tunnel oxide layer and the oxide pattern of the exposed portion by a predetermined thickness, and then forming a dielectric layer on the entire upper surface thereof And a second polysilicon layer, a tungsten silicide layer, and a hard mask on the dielectric film. And forming patterned control gates sequentially, and implanting impurity ions into exposed substrates on both sides of the floating gate to form a junction region.

According to US Pat. No. 6,465,293, the floating gate can be self-aligned by the oxide pattern that partially exposes the substrate.

  Recently, as the integration degree of a semiconductor device is improved, an aspect ratio of an opening defined by the oxide film pattern for partially exposing the semiconductor substrate is increased. As the aspect ratio of the opening is increased, voids may be generated because polysilicon is not filled in a predetermined portion of the opening due to the high step coverage deposition characteristic of the polysilicon when the polysilicon is embedded in the opening. In addition, the opening is more frequently generated because the bottom portion has a wider negative slope than the inlet portion.

1 is a scanning electron micrograph showing a void formed inside a conventional floating gate.

As described above, the voids 12 generated inside the polysilicon layer 10 are not removed even after the planarization process for forming the floating gate. Therefore, unwanted oxides may be generated at the sites where the voids are generated by subsequent processes, and the oxides have a problem of deteriorating electrical characteristics of the semiconductor device. In other words, the dispersion of capacitance is increased to cause a problem of dispersion of the coupling ratio.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of preventing voids from being generated in a self-aligned floating gate formed between device isolation layers. have.

In the method for manufacturing a nonvolatile memory device according to an embodiment of the present invention for achieving the object of the present invention is a preliminary projection from the substrate while sufficiently filling the trench formed in the substrate, the width of the upper surface is larger than the width of the bottom surface Device isolation layers are formed. Spacers are formed on sidewalls of the preliminary isolation layers. A wet etching process may be performed on the preliminary device isolation layers on which the spacers are formed to form device isolation layers having substantially vertical sides. A conductive film for a floating gate is formed to cover the device isolation layers while the space between the device isolation layers is buried. The floating gate conductive layer is etched to form a floating gate. A dielectric film is formed on the upper surface of the floating gate to have a substantially uniform thickness. A control gate is formed on the dielectric layer.

Preferably, the etchant used in the wet etching process has an etching selectivity of 1:22 to 30 with respect to the preliminary device isolation layer and the spacer.

In this case, the semiconductor device may further include an opening exposing the surface of the substrate between the preliminary device isolation layers.

The spacer may be formed by forming a spacer layer having an etching selectivity different from that of the preliminary isolation layer, and performing a dry etching process until the surface of the substrate is exposed to the spacer layer. For example, the spacer layer includes one material selected from the group consisting of silicon nitride (SiN), polysilicon, silicon oxynitride (SiON), and silicon germanium (Si-Ge).

As described above, in the method of forming the nonvolatile memory device, an opening defined between the device isolation layers is formed to have a wide inlet by forming a spacer on sidewalls of the preliminary device isolation layers and performing a wet etching process. do. Therefore, when the floating gate is formed by embedding polysilicon in the openings defined between the device isolation layers, no void is formed in the floating gate.

Hereinafter, a method of forming a nonvolatile memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or film and regions are exaggerated for clarity of the invention, and each device may have various additional devices not described herein, and the film may have different films. Or when referred to as being located on a substrate, it may be formed directly on another film or substrate, or an additional film may be interposed therebetween.

2 to 8 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 2, preliminary device isolation layers 110 having a top surface higher than that of the substrate are formed on the substrate 100.

Specifically, the pad oxide film 102 and the hard mask film (not shown) are sequentially stacked on the substrate 100 such as silicon. For example, the pad oxide layer 102 may be formed through a thermal oxidation, chemical vapor deposition (CVD) process, or the like. The hard mask layer may be formed through a low pressure chemical vapor deposition (LPCVD) process using SiH ₂ Cl ₂ gas, SiH ₄ gas, NH ₃ gas, or the like. The hard mask layer preferably includes silicon nitride (SiN).

Subsequently, a photoresist pattern (not shown) is formed on the hard mask layer to expose the surface of the hard mask layer through a photolithography process. The hard mask 104 is formed by etching the hard mask layer using the photoresist pattern as an etching mask. Examples of the etching process include a dry etching process using a plasma, a reactive ion etching process, and the like.

After the hard mask 104 is formed, the photoresist pattern is removed through an ashing process, a stripping process, and a cleaning process.

The trench 106 is formed by anisotropically etching the exposed portions of the pad oxide layer 102 and the substrate 100 to a predetermined depth by using the hard mask 104 as an etching mask. The trench 106 is formed to cross the substrate 100 in a first direction.

The substrate exposed by the trench 106 to heal surface damage of the silicon substrate caused by the high energy ion bombardment during the etching process for forming the trench 106 and to prevent leakage current generation ( 100) is heat-treated in an oxidizing atmosphere. Accordingly, a trench inner wall oxide layer (not shown) is formed on the inner surface including the bottom surface and the side surface of the trench 106.

Then, preliminary isolation layers 110 may be formed on the substrate 100 on which the trench 106 is formed to completely fill the trench 106. Examples of the oxide films constituting the preliminary device isolation layers 110 may include USG, O ₃ -TEOS, USG, or high density plasma (HDP) oxide films. Preferably, the preliminary device isolation layers 110 may use an HDP oxide film formed using SiH ₄ , O _2, and Ar gas as a plasma source.

Subsequently, the preliminary device isolation layers 110 are removed through a planarization process such as an etch back process or a chemical mechanical polishing (CMP) process until the upper surface of the hard mask 104 is exposed. do. As a result, the preliminary isolation layers 110 are formed only in the trench 106 to complete the field insulating pattern 110 extending in the first direction defining the active region 108 of the substrate 100.

Referring to FIG. 3, the hard mask 104 and the pad oxide layer 102 are sequentially removed by a wet etching process to form a first opening 112 exposing the surface of the substrate 100.

The first opening 112 is defined by the preliminary device isolation layers 110, and is formed by removing the hard mask 104 through a dry etching process or a wet etching process. For example, the hard mask 104 may use an etching solution containing phosphoric acid, and the pad oxide layer 102 may be removed by a wet etching process using an etching solution containing hydrofluoric acid (HF). As a result, preliminary isolation layers 110 having a top surface higher than that of the substrate 100 are formed on the substrate 100. Meanwhile, while removing the hard mask 104 and the pad oxide layer 102, surface portions of the preliminary device isolation layers 110 may be somewhat etched.

Therefore, the width of the upper surface of the preliminary device isolation layers 110 protruding from the substrate 100 is greater than the width of the bottom surface. On the other hand, the first opening 112 formed between the preliminary device isolation layers 110 has a lower line width than the upper line width.

Referring to FIG. 4, different from the preliminary device isolation layer 110 having a substantially uniform thickness on the top and side surfaces of the preliminary device isolation layers 110 protruding from the substrate 100 and the surface of the substrate 100. The spacer layer 120 having an etching selectivity is formed.

The spacer layer 120 may be formed using an LPCVD method. In this case, the spacer layer 120 is formed to a thickness of about 150 ~ 300Å. Examples of the material for forming the spacer layer 120 include silicon nitride (SiN), polysilicon, silicon oxynitride (SiON), silicon germanium (Si-Ge), and the like. Preferably, the spacer layer 120 includes silicon nitride (SiN).

The spacer layer 120 made of silicon nitride (SiN) is used to form sidewalls of the preliminary isolation layers 110 to have a substantially vertical slope or a positive slope. When the preliminary device isolation layers 110 having the vertical sidewall profile are formed or the preliminary device isolation layers 110 having the positive sidewall profile are formed, the void V formed therein is reduced during the subsequent formation of the floating gate. You can.

Referring to FIG. 5, a dry etching process is performed until the surface of the substrate 100 is exposed to the spacer layer 120 to form spacers 122 on sidewalls of the preliminary device isolation layers 110. In this case, an upper portion of the spacer layer 120 adjacent to the inlet of the first opening 112 may be greater than a lower portion of the spacer layer 120 adjacent to the bottom of the first opening 112 by the dry etching process. The bottom surface of the spacer 122 is etched to have a wider width than the top surface.

Referring to FIG. 6, a wet etching process using an etchant is performed on the preliminary device isolation layers 110 on which the spacers 122 are formed to remove portions of the spacers 122 and the preliminary device isolation layers 110. As a result, the preliminary device isolation layers 110 are formed as device isolation layers 110a. Portions of the device isolation layers 110a exposed to the substrate 100 may have a substantially vertical side surface or a positive slope side surface.

In this case, the etchant used in the wet etching process may have an etching selectivity of 1:22 to 30 with respect to the preliminary device isolation layers 110 and the spacer 122. When the etching selectivity of the spacer 122 with respect to the preliminary device isolation layers 110 is less than 1:22, the device isolation layers 110a may not form a substantially vertical or positive sidewall profile. On the other hand, when the etch selectivity of the spacer 122 with respect to the preliminary device isolation layers 110 is greater than 1:30, only the spacer 122 is etched and the sidewalls of the lower preliminary device isolation layers 110 are sufficiently removed. As a result, the device isolation layers 110a may not form a substantially vertical or positive sidewall profile.

That is, as the spacers 122 are all removed in the wet etching process, the upper edge portions of the side surfaces of the preliminary device isolation layers 110 are removed to a greater width, so that the device isolation layers corresponding to the portions protruding to the substrate 100 are removed. The sidewalls of 110a have a substantially vertical or positive profile. Therefore, the first opening 112 defined between the device isolation layers 110a is formed as a second opening 112a having a wide inlet.

Accordingly, in the subsequent process of forming a floating gate, a polysilicon (Si) saturation nucleus density is increased and a nonvolatile memory cell in which generation of voids (V) is suppressed due to stabilization of a coupling structure can be formed. .

Referring to FIG. 7, the gap region between the device isolation layers 110a is completely filled to form a floating gate conductive layer 130 having a substantially uniform thickness on the device isolation layers 110a.

The floating gate conductive layer 130 may be formed using a polysilicon material doped with impurities. The conductive film 130 for the floating gate is formed by the LPCVD method, and then doped with ions which are a high concentration of impurities by a POCl ₃ diffusion, ion implantation, or in-situ doping method. In this case, since the floating gate conductive layer 130 is buried between the device isolation layers 110a having a positive sidewall profile of which the width of the bottom surface is larger than the width of the upper surface of the floating gate, polysilicon is formed on the bottom surfaces of the device isolation layers 110a. Void problems caused by abnormal growth of crystals are minimized.

Subsequently, a photoresist pattern 132 is formed on the floating gate conductive layer 130 to selectively expose a portion of the top surface of the device isolation layer 110a while selectively masking an active region. The photoresist pattern 132 may be formed using silicon nitride (SiN).

Referring to FIG. 8, by selectively etching the floating gate conductive layer 130 exposed to the photoresist pattern 132, the device isolation layers 110a are exposed to the floating gate conductive layer 130. The third opening 134 is formed. In this case, the floating gate conductive layer 130 is formed as a floating gate 130a covering a portion of the device isolation layer 110a on the substrate 100. Thereafter, the photoresist pattern 132 is removed by performing an ashing process, a strip process, and a cleaning process.

As described above, the spacer 122 is formed on the preliminary device isolation layers 110, and a wet etching process is performed to improve the sidewall profile, thereby forming a floating gate having a dense and uniform bonding structure in which void generation is suppressed. 130a may be formed.

Subsequently, a dielectric layer 140 having a substantially uniform thickness is formed on the third opening 134 through which the floating gate 130a and the device isolation layer 110a are exposed. The dielectric layer 140 may be formed by sequentially stacking silicon oxide, silicon nitride, and silicon oxide. Alternatively, the dielectric layer 160 may be formed by stacking a metal oxide having a high dielectric constant.

In the present embodiment, the dielectric layer 140 grows the first oxide film by a thermal oxidation process, deposits a nitride film thereon by low pressure chemical vapor deposition (LPCVD), and then deposits the second oxide film by the thermal oxidation process. Form by growing.

Subsequently, a polysilicon material is deposited on the dielectric layer 140 to form a conductive film for a control gate (not shown). The control gate conductive film may include a first conductive film made of doped polysilicon and a second conductive film made of metal silicide such as tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), and tantalum silicide (TaSix). Include.

The control gate conductive layer is patterned through a normal photolithography process to form a control gate 150 extending in a second direction substantially perpendicular to the first direction on the dielectric layer 140.

Although not shown, the dielectric layer 140 and the floating gate 130a are sequentially patterned to form a gate structure of the nonvolatile memory device. Subsequently, source / drain regions (not shown) are formed on the surface of the active region 108 of the substrate 100 facing each other in the first direction with respect to the gate structure through an impurity doping process, thereby forming the nonvolatile structure. The memory device can be completed.

As described above, in the method of forming the nonvolatile memory device according to the preferred embodiment of the present invention, an opening having a wide opening defined between the device isolation layers is formed by forming a spacer on sidewalls of the preliminary device isolation layers and performing a wet etching process. It characterized in that it is formed to have. Therefore, when the floating gate is formed by embedding polysilicon in the openings defined between the device isolation layers, no void is formed in the floating gate.

In addition, since a void-free flat floating gate is formed, a poor dispersion of capacitance and a poor dispersion of the coupling ratio can be improved, thereby improving electrical operation performance of the semiconductor device.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (5)

Forming preliminary isolation layers that protrude from the substrate while sufficiently filling trenches formed in the substrate and having a width of an upper surface greater than a width of a bottom surface; Forming a spacer on sidewalls of the preliminary isolation layers; Performing a wet etching process on the preliminary device isolation layers on which the spacers are formed to form device isolation layers having a substantially vertical side surface; Forming a conductive film for the floating gate covering the device isolation layers while the space between the device isolation layers is buried; Etching the conductive film for floating gate to form a floating gate; Forming a dielectric film on the upper surface of the floating gate to have a substantially uniform thickness; And Forming a control gate on the dielectric layer. The method of claim 1, wherein the etchant used in the wet etching process has an etching selectivity of 1:22 to 30 with respect to the preliminary device isolation layer and the spacer. The method of claim 1, further comprising an opening exposing the surface of the substrate between the preliminary device isolation layers, wherein the opening has a lower line width greater than an upper line width. The method of claim 1, wherein forming the spacer Forming a spacer layer having an etching selectivity different from that of the preliminary device isolation layer; And And performing a dry etching process until the surface of the substrate is exposed to the spacer layer. The nonvolatile memory as claimed in claim 4, wherein the spacer layer comprises one material selected from the group consisting of silicon nitride (SiN), polysilicon, silicon oxynitride (SiON), and silicon germanium (Si-Ge). Method of manufacturing the device.

Images