KR20070049267A - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device, such as a flash memory device, fills a first trench formed in a substrate, forms a device isolation pattern protruding from the substrate, and then forms a first oxide film on an active region defined on the substrate. Spacers are formed on side surfaces of the device isolation layer pattern, and the first oxide layer pattern and the second trench are formed using the spacers. Thereafter, a sacrificial oxide film is formed, and the sacrificial oxide film is partially removed to expose the spacers. After removing the spacers and the remaining sacrificial oxide film to expose the first oxide pattern, and forming a tunnel oxide film including the second oxide film and the first oxide pattern formed on the bottom and side surfaces of the second trench, the floating gate, the dielectric film and the control gate To form sequentially. As a result, leakage current at both edge portions of the tunnel oxide film can be prevented without damaging the substrate exposed by the trench.

Description

Method of manufacturing a semiconductor device

1 is a cross-sectional view showing a conventional nonvolatile memory cell.

2 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100 substrate 101 pad oxide film

102: hard mask 103: first trench

104: device isolation membrane 105: opening

106: second trench 110: first oxide film

112: first oxide film pattern 120: medium temperature oxide film

122: medium temperature oxide film pattern 130: spacer

140: sacrificial oxide film 142: sacrificial oxide film pattern

150: second oxide film 152: tunnel oxide film

160: polysilicon film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device such as a flash memory device including a tunnel oxide film having a uniform threshold voltage.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are RAM products, which are volatile memory that loses stored data when power is interrupted, and data is retained even when power is temporarily interrupted. It can be divided into ROM (read only memory) products which are non-volatile memory.

The nonvolatile memory device is capable of maintaining its state over time once inputting data. Recently, there is an increasing demand for a flash memory that can electrically input and output data.

The memory cell for storing data in the flash memory device has a stacked gate structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are sequentially stacked on the silicon substrate. In flash memory cells having such a structure, data is stored by applying an appropriate voltage to the control gate and the substrate to insert or withdraw electrons from the floating gate. In this case, the dielectric layer maintains charge characteristics charged in the floating gate and transfers the voltage of the control gate to the floating gate.

1 is a cross-sectional view showing a conventional nonvolatile memory cell.

Referring to FIG. 1, a tunnel oxide layer 12 and a floating gate 14 are stacked on a substrate 10 on which an isolation layer STI (not shown) is formed. A dielectric layer 22 having an ONO structure exists on the floating gate 14, and a control gate 24 exists on the dielectric layer 22.

In the nonvolatile memory cell having the above-described structure, the tunnel oxide film is formed by oxidizing the surface of the substrate exposed by the device isolation film. Therefore, both edge portions of the tunnel oxide film adjacent to the sidewall of the device isolation layer have a thickness relatively thinner than the center portion of the tunnel oxide film.

As described above, when the thickness uniformity of the tunnel oxide film is poor, leakage current at both edge portions of the tunnel oxide film may increase, and electron tunneling may occur at a voltage lower than the set voltage. As a result, the durability of the tunnel oxide film and the data storage capability of the floating gate electrode may be reduced, and the operation reliability of the entire flash memory device may be reduced.

An object of the present invention for solving the above problems is to provide a method of manufacturing a semiconductor device including a tunnel oxide film having a thickness of both edge portions is thicker than the thickness of the central portion.

According to the method of manufacturing a semiconductor device according to the present invention for achieving the object of the present invention, a device isolation film pattern protruding from the surface of the substrate is formed while filling the first trench formed in the substrate. A first oxide film is formed on the active region defined on the substrate. Spacers are formed on side surfaces of the device isolation layer pattern. The first oxide layer and the substrate are etched using the spacer as an etch mask to form a first oxide pattern and a second trench. A sacrificial oxide layer having a first thickness is formed on an upper surface of the device isolation layer pattern and a surface of the spacer, and a second thickness thicker than the first thickness is formed on the bottom and side surfaces of the second trench. The sacrificial oxide film having the first thickness is removed to expose the spacers. The spacers and the remaining sacrificial oxide layer are sequentially removed to expose the first oxide layer pattern, and then a second oxide layer is formed on the bottom and side surfaces of the second trench to form a first oxide pattern and a second oxide layer on the substrate. A tunnel oxide film is formed. The semiconductor device is completed by forming a polysilicon film for forming a floating gate on the device isolation pattern and the tunnel oxide film.

According to an embodiment of the present invention, the sacrificial oxide film is preferably formed by a thermal oxidation process, and the thickness of the first oxide film pattern is preferably equal to or thicker than the thickness of the second oxide film.

In the method of manufacturing a semiconductor device according to the present invention as described above, a tunnel oxide film having a thickness equal to or thicker than the thickness of the center portion may be formed at both edge portions. A tunnel oxide film having such a structure can be used to prevent leakage current at both edge portions. Therefore, the electrical characteristics and the reliability of the semiconductor device can be improved.

 Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the accompanying drawings, the dimensions of the substrates, layers (films), regions or patterns are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region or pattern is referred to as being formed "on", "top", "below" or "bottom" of the substrate, each layer (film), region or pattern. Whereby each layer (film), region or pattern is formed directly over or below the substrate, each layer (film), region or patterns, or other layers (film), other regions or patterns It may be further formed on the phase. In addition, when each layer (film), region, or pattern is referred to as "first" and / or "second", it is not intended to limit these members but merely to distinguish each layer (film), region, or pattern. It is to. Thus, "first" and / or "second" may be used selectively or interchangeably for each layer (film), region or pattern, respectively.

2 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2, a pad oxide film 101 is formed on a substrate 100 such as a silicon wafer, and a hard mask film is sequentially stacked on the pad oxide film 101. For example, the pad oxide film 101 may be formed through a thermal oxidation process, a chemical vapor deposition (CVD) process, or the like. The hard mask layer may be formed by performing a low pressure chemical vapor deposition (LPCVD) process. The hard mask layer preferably includes silicon nitride (SiN).

Subsequently, a photoresist pattern (not shown) is formed on the hard mask layer. Subsequently, the hard mask layer 102 is etched using the photoresist pattern as an etching mask to form a hard mask pattern 102. After the hard mask pattern 102 is formed, the photoresist pattern is removed through an ashing process and a cleaning process.

The first trench 103 for forming an isolation layer is formed by anisotropically etching the upper portion of the exposed semiconductor substrate 100 using the hard mask pattern 102 as an etch mask.

Subsequently, in order to cure surface damage of the silicon substrate caused by high energy ion bombardment in the etching process for forming the first trench 103, the exposed silicon substrate 100 of the trench 103 is removed. Heat treatment in oxidizing atmosphere. Accordingly, a trench inner wall oxide film (not shown) is formed on the inner surface including the bottom and side surfaces of the trench 103.

Then, trenches 103 are formed (undoped silicate glass), USG so as to completely fill the trench (103) in front of the _{results, O 3 -TEOS (tetra-ethyl} -ortho-silicate) USG, or high density plasma (High Density Plasma : HDP) An oxide film having excellent gap filling characteristics such as an oxide film is deposited to form a gap filling oxide film. Preferably, a high density plasma (HDP) oxide film formed using SiH ₄ , O _2, and Ar gas as the plasma source may be used.

Thereafter, the gap buried oxide layer is removed by an etch back or chemical mechanical polishing (CMP) process until the upper surface of the hard mask pattern 102 is exposed. As a result, an element isolation film 104 which is a field oxide film is formed in the trench 103 so that the substrate 100 is divided into a field region and an active region.

Referring to FIG. 3, a wet etching process is performed on the substrate 100 on which the device isolation layer 104 is formed to remove the hard mask pattern 102 to expose side surfaces of the pad oxide film 101 and the device isolation layer 104. The opening 105 is formed. As an example, the etchant of the wet etching process may be HF aqueous solution, H ₃ PO ₄ and SC-1 (Standard Cleaning Solution) can be used. At this time, the HF aqueous solution has a molar ratio of H ₂ O and HF of about 100: 1. As an example of the wet etching process, the substrate 100 on which the device isolation layer 104 is formed may be sequentially exposed to the etching solution of the HF aqueous solution, H ₃ PO _4, and SC-1 for 30 seconds, 30 minutes, and 3 minutes. .

Subsequently, the exposed pad oxide layer 101 is removed through a wet etching process. For example, a wet etching process of the pad oxide layer 101 may be exposed for 110 to 130 seconds using an HF aqueous solution having a molar ratio of H ₂ O to HF of about 200: 1. As a result, the pad oxide layer 101 is removed to expose the surface of the substrate 100 corresponding to the active region, and at the same time, the side surface of the device isolation layer 104 exposed by the removal of the previous hard mask 102 is etched to open the opening. The width of 105 is widened.

Subsequently, the bottom surface of the opening 105 is heat-treated in an oxygen atmosphere to form a first oxide film 110 on the surface of the exposed substrate 100 corresponding to the active region. The first oxide film 110 is preferably formed to a thickness of 80 to 120Å.

Referring to FIG. 4, a middle temperature oxide (MTO) 120 having a substantially uniform thickness is formed on an upper surface, a side surface of the device isolation layer 104, and the first oxide layer 110. As an example, the middle temperature oxide film 120 is preferably deposited at a temperature of 750 to 800 ℃, more preferably at 780 ℃. The middle temperature oxide film 120 is preferably formed to a thickness of 90 kPa to 140 kPa.

The mid temperature oxide layer 120 serves to protect the surface of the substrate 100 on which the device isolation layer 104 is formed during subsequent spacer formation and etching of the first oxide layer 110 exposed by the spacer.

Referring to FIG. 5, a spacer film (not shown) is continuously formed on the entire surface of the resultant product in which the intermediate temperature oxide film 120 is formed. That is, the spacer film should not completely fill the inside of the opening 105.

In this case, the spacer layer is formed of a material having an etching selectivity with respect to the middle temperature oxide layer 120 in any etching process. As an example, the spacer layer may be formed by depositing silicon nitride (SiN). The spacer film is preferably formed to have a uniform thickness of about 130 to 170Å.

Next, the spacer layer is anisotropically etched to expose the upper surface of the mesophilic oxide film 120 to form a spacer 130 on the side of the device isolation film 104 on which the mesophilic oxide film 120 is formed. As an example, the anisotropic etching process is preferably an etch back process. The spacer 130 is formed to a thickness of about 30 to 60Å on the sidewall of the mesophilic oxide film 120. The spacer 130 formed by the above process is then provided as an etching mask pattern for etching the center portion of the first oxide film 110 under the middle temperature oxide film 120 and the active region of the substrate 100.

Referring to FIG. 6, an ashing process and a strip process are performed on the substrate 100 on which the spacers 130 are formed. The etching by-products including the polymer generated in the etching process are removed when the spacer 130 is formed through the ashing process.

An intermediate temperature oxide layer pattern 122 that exposes the active region on the substrate 100 by sequentially etching the intermediate temperature oxide layer 120 and the first oxide layer 110 through an etching process using the spacer 130 as an etching mask. ) And the first oxide film pattern 112 are formed. For example, the etching process may be performed through a wet etching process using hydrofluoric acid (HF).

Subsequently, the second trench 106 is formed by anisotropically etching the upper portion of the exposed active region by using the spacer 130 as an etching mask.

Subsequently, the exposed substrate 100 of the second trench 106 to cure surface damage of the silicon substrate caused by the high energy ion bombardment in the etching process for forming the second trench 106. ) Is heat-treated in an oxidizing atmosphere. Accordingly, a trench inner wall oxide layer (not shown) is formed on the inner surface including the bottom and side surfaces of the second trench 106.

Referring to FIG. 7, a sacrificial oxide layer 140 is formed inside the middle isolation pattern 122 formed on the upper surface of the isolation layer 108, the surface of the spacer 130, and the side and bottom surfaces of the second trench 106. ). For example, the sacrificial oxide layer 140 may be formed by performing a thermal oxidation process.

When the thermal oxidation process is performed, an oxidation reaction occurs actively in the silicon substrate 100 exposed by the second trench 106, while the device including the spacer 130 and the oxide including the silicon nitride is included in the device. An oxidation reaction hardly occurs on the middle temperature oxide pattern 122 formed on the upper surface of the separator pattern 104. Accordingly, a first sacrificial oxide film 140a having a first thickness is formed on the spacer 130 including silicon nitride and the intermediate temperature oxide pattern 122 including an oxide, and formed inside the second trench 106. A second sacrificial oxide film 140b having a second thickness thicker than the first thickness is formed.

Referring to FIG. 8, the sacrificial oxide layer pattern exposing the intermediate temperature oxide layer pattern 122 on the spacer 130 and the device isolation layer 104 by removing the first sacrificial oxide layer 140a through a wet etching process. 142). The wet etching is performed only until both the spacer 130 having a relatively thin thickness and the first sacrificial oxide layer 140a on the middle temperature oxide pattern 122 are removed.

Subsequently, the exposed spacers 130 are selectively removed. The process of removing the spacer 130 may be performed through a wet etching process using phosphoric acid. The substrate 100 is protected by the sacrificial oxide layer pattern 142 during the spacer 130 removal process. Therefore, damage to the substrate 100 may be prevented during the spacer 130 removal process.

Referring to FIG. 9, the sacrificial oxide pattern 142 and the middle temperature oxide pattern 122 are removed. The process of removing the sacrificial oxide pattern 142 and the middle temperature oxide pattern 122 may be a wet cleaning process. Specifically the cleaning process is carried out using a mixture of SC-1 and HF. For reference, the SC-1 etchant is a mixture of NH ₄ OH, H ₂ O ₂ and H ₂ O. The wet cleaning process using the etchant is preferably exposed to the etchant for 160 seconds. As a result, the first oxide layer pattern 112 having a third thickness and adjacent to the side surface of the isolation layer 104 is exposed by removing the middle temperature oxide layer pattern 122 on the substrate 100. In this case, the surface of the substrate 100 on which the first oxide film pattern 112 is not formed, that is, the inside of the second trench 106 is exposed.

As such, when the spacer 130, the sacrificial oxide pattern 142, and the middle temperature oxide pattern 122 are removed, the subsequent tunnel oxide layer 152 (FIG. 10) and the floating gate 160, FIG. 11 are interposed between the device isolation layers 104. The gap site for forming) is completed.

Referring to FIG. 10, a thermal oxidation process is performed on the substrate 100 on which the second trench 106 is formed. According to the above process, a second oxide film 150 having a fourth thickness is formed along side surfaces and bottom surfaces of the second trench 106. The third thickness is preferably the same as the fourth thickness or thicker than the fourth thickness.

As a result, the tunnel oxide film 152 including the first oxide film pattern 112 and the second oxide film 150 is formed on the substrate 100.

The first oxide layer pattern 112 of the tunnel oxide layer 152 is formed to have a third thickness adjacent to the side surface of the device isolation layer 104. In addition, the second oxide film 150 of the tunnel oxide film 152 is formed to have the fourth thickness on the side and bottom of the second trench 106. That is, the tunnel oxide film 152 is formed such that the thickness of both edge portions is equal to or thicker than that of the central portion.

In the related art, partial thinning of the tunnel oxide film 152 has occurred on both edge portions of the substrate 100 exposed between the device isolation films 104. In this case, leakage current through the thin both edges of the tunnel oxide film 152 increased.

On the contrary, in the present invention, the first oxide pattern 112 is formed on both edge portions of the substrate 100 exposed between the device isolation layers 104, and the second oxide layer (which is the same as or thinner than the both edge portions in the center) is formed. 150 to form a tunnel oxide film 152 whose thickness is equal to or greater than the thickness of the central portion. In this case, the depth and width of the second trench 106 in which the second oxide film 150 of the tunnel oxide film 152 is formed may be controlled constantly according to the width of the spacer 130. In the nonvolatile memory cell including the tunnel oxide layer 152 having the above structure, most of the current flows through the center portion of the tunnel oxide layer 152, and leakage of current through both edge portions can be prevented. Therefore, a cell having uniform electrical characteristics can be formed, so that the reliability of the operation of the semiconductor device can be improved.

Referring to FIG. 9, as described above, the first oxide film pattern 112 having the third thickness and the second thickness having a fourth thickness that is equal to or smaller than the third thickness on the substrate 100. After the tunnel oxide film 152 including the oxide film 150 is formed, a polysilicon film 160 for forming a floating gate is deposited on the device isolation film 104 and the tunnel oxide film 152.

Subsequently, the polysilicon film 160 is doped to a high concentration of N-type by a conventional doping method such as POCl ₃ diffusion, ion implantation, or in-situ doping, and then, although not shown, The silicon layer 160 is removed to insulate the floating gates of neighboring memory cells from each other.

Although not shown, an ONO dielectric film including a lower oxide film, a nitride film, and an upper oxide film is formed on the floating gate, and then a control gate film in which polysilicon and tungsten (W) or tungsten silicide (WSix) are sequentially stacked on the dielectric film is formed. do. Subsequently, the control gate film, the dielectric film and the floating gate film are patterned by a photolithography process. As a result, a nonvolatile memory cell in which a floating gate and a control gate are vertically stacked is completed.

In the method of manufacturing a semiconductor device as described above, a tunnel oxide film having a thickness of both edge portions equal to or thicker than that of the central portion can be formed. A nonvolatile memory cell including a tunnel oxide film having such a structure can prevent leakage currents at both edge portions. In addition, damage to the substrate may be prevented by protecting the substrate exposed by the second trench during spacer etching using the sacrificial oxide layer.

As a result, the electrical characteristics and the reliability of the operation of the semiconductor device can be improved.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (3)

Forming an isolation layer pattern protruding from the surface of the substrate while filling the first trench formed in the substrate: Forming a first oxide film on an active region defined on the substrate; Forming a spacer on a side of the device isolation layer pattern; Etching the first oxide layer and the substrate using the spacers as an etching mask to form a first oxide pattern and a second trench; Forming a sacrificial oxide film having a first thickness on an upper surface of the device isolation layer pattern and a surface of the spacer and having a second thickness thicker than the first thickness on the bottom and side surfaces of the second trench; Removing the sacrificial oxide film having the first thickness to expose the spacers; Sequentially removing the spacers and the remaining sacrificial oxide film to expose the first oxide film pattern; Forming a second oxide layer on the bottom and side surfaces of the second trench to form a tunnel oxide layer including a first oxide pattern and a second oxide layer on the substrate; And A polysilicon film for forming a floating gate on the device isolation pattern and the tunnel oxide film is formed. The method of claim 1, wherein the sacrificial oxide film is formed by a thermal oxidation process. The method of claim 1, wherein a thickness of the first oxide film pattern is equal to or thicker than a thickness of the second oxide film.

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