KR20060125979A - Method of manufacturing a floating gate in non-volatile memory device - Google Patents

Abstract

A method for forming a floating gate of a non-volatile memory is provided to form a U-typed floating gate by polishing a sacrificial layer formed on a conductive layer for the floating gate until the surface of a part of the conductive layer is exposed and by removing the exposed part of the conductive layer by an etch process. A field oxide layer pattern(110) protrudes from the surface of a substrate(100) so that an opening for exposing a part of the surface of the substrate is formed. A conductive layer for a floating gate(118) is continuously deposited on the field oxide layer pattern and the exposed substrate. A sacrificial layer is formed on the conductive layer for the floating gate to fill the opening. The sacrificial layer is polished to expose the surface of a part of the conductive layer for the floating gate. The exposed conductive layer for the floating gate is selectively etched to form a node-separated floating gate. The sacrificial layer and the field oxide layer pattern remaining between the floating gates are partially removed.

Description

Method of manufacturing a floating gate in non-volatile memory device

1 to 10 are schematic cross-sectional views illustrating a method of forming a floating gate of a nonvolatile memory according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 102 pad oxide film pattern

104: nitride film pattern 106: trench

108: gap filling oxide film 110: field oxide film pattern

112: first conductive film 114: sacrificial film

116: sacrificial film pattern 118: floating gate

120: dielectric film

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a floating gate of a nonvolatile memory device.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), are volatile and fast data input / output that loses data over time, and data is input once. It can be maintained in this state, but it can be classified into ROM (Read Only Memory) products that have slow input / output data. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory.

The flash memory unit cell includes a vertical stacked gate structure having a floating gate. In detail, the gate of the flash memory cell has a structure in which a floating gate, a dielectric layer, and a control gate are stacked on the tunnel oxide layer.

In order to form the floating gate as described above, an opening is formed in a portion where the floating gate is to be formed, a process of polishing the polysilicon after depositing the floating silicon polysilicon filling the inside of the opening. However, not only the polishing rate of polysilicon is different at the center and the edge of the substrate, but also the polishing rate of polysilicon is different in a cell region having a high pattern density and a ferry region having a low pattern density within one chip. Because of this, it is very difficult to polish the polysilicon uniformly over the entire substrate area. Therefore, problems such as the height of the finally formed floating gate is changed for each region or the floating gate is not normally separated at the portion where the polysilicon is not polished.

On the other hand, in the gate of the flash memory cell, the floating gate electrode is typically provided on the line type active region. The floating gate electrode must be formed in a predetermined size or more on the active region to maintain a cell current and a coupling ratio. That is, in order to increase the operating speed of the flash memory device by increasing the cell current, it is desirable to decrease the channel length and increase the width of the active.

However, as the design-rules of memory cells become smaller and smaller, the width of the active region continues to decrease. This prevents sufficient F-N tunneling effect from occurring and reduces cell current during operation resulting in reduced operating speed.

In order to solve the above problems, a method of forming a floating gate of a flash memory according to Korean Patent Publication No. 2001-0035297 will be described.

A first floating gate is formed to fill an opening formed between the field regions of the semiconductor substrate, and a U-shaped second floating gate is formed on the first floating gate.

In the method of forming the second floating gate, first, a mold layer having a step with the first floating gate is formed on a portion where the first floating gate is not formed, that is, a field region. Subsequently, the polysilicon for the second floating gate is continuously deposited on the mold layer and the first floating gate, a portion of the polysilicon is removed so that the mold layer is exposed, and the exposed mold layer is removed. Form a floating gate. A bottom surface of the second floating gate is in contact with the first floating gate, and all surfaces except the bottom surface are exposed to the outside, thereby increasing the area of contact with the dielectric layer to be formed later. This means that the coupling coefficient can be improved by increasing the capacitance between the floating gate and the control gate.

However, since the floating gate is formed using the mold layer, the deposition process, the photolithography process, and the etching process may be performed during the formation of the mold layer, which may cause the process to be somewhat complicated, resulting in loss of process time and cost. .

An object of the present invention to solve the above problems is to provide a method of forming a floating gate of a nonvolatile memory that can reduce the problem that the effective area of the floating gate is increased, and the neighboring floating gates short (short). .

According to an aspect of the present invention for achieving the above object, to form a field oxide pattern protruding from the substrate surface to form an opening for exposing a portion of the substrate surface, and floating on the field oxide pattern and the exposed substrate The gate conductive film is deposited continuously. Subsequently, after the sacrificial film is formed on the floating gate conductive film to fill the opening, the sacrificial film is polished to expose a surface of a portion of the floating gate conductive film. The floating gate of the nonvolatile memory is formed by selectively etching the exposed floating gate conductive film to form a node-separated floating gate.

The etching process may be a front side anisotropic etching process.

According to the present invention as described above, by using the field oxide film pattern defining the opening as a mold layer used in the prior art, in forming the step of the floating gate, no mold layer is formed, thereby simplifying the process.

In addition, in performing an etching process to form a floating gate, a chemical mechanical polishing process is first performed to expose a portion of the conductive film for the floating gate, and then a portion of the exposed conductive film is removed by an entire anisotropic etching process. Thereby, while forming the U-shaped floating gate, it is possible to separate neighboring floating gates, thereby reducing the shortening of the floating gate.

Hereinafter, a method of forming a floating gate of a nonvolatile memory according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 10 are schematic cross-sectional views illustrating a method of forming a floating gate of a nonvolatile memory according to an embodiment of the present invention.

Referring to FIG. 1, a pad oxide film (not shown) and a silicon nitride film for a hard mask (not shown) are formed on the semiconductor substrate 100. The pad oxide film may be formed by a thermal oxidation process, and the pad oxide film later functions as a tunnel oxide film. In addition, the pad oxide layer is formed to reduce stress generated when the silicon nitride layer formed thereafter is in direct contact with the semiconductor substrate 100.

The silicon nitride film may be formed by a low pressure chemical vapor deposition (LPCVD) process.

In this case, an organic anti-reflection layer (ARL, not shown) may be further formed on the silicon nitride layer. The holding antireflection film is a film provided to prevent the photoresist sidewall profile from being deteriorated by diffuse reflection in a subsequent photographic process.

Next, a photoresist pattern (not shown) is formed on the silicon nitride layer, and the silicon nitride layer and the pad oxide layer are etched using the photoresist pattern as an etching mask to form the pad oxide layer pattern 102 and the silicon nitride layer pattern 104. This laminated hard mask pattern 105 is formed. The hard mask pattern 105 is formed to selectively expose a portion corresponding to a field region of the semiconductor substrate 100.

After the hard mask pattern 105 is formed, the photoresist pattern is removed through an ashing process or a strip process.

Referring to FIG. 2, the trench 106 may be formed by selectively etching the exposed region of the semiconductor substrate 100 using the hard mask pattern 105 as an etching mask. In this case, the organic anti-reflection film is removed during the etching of the semiconductor substrate 100.

In this case, after the trench 106 is formed, a thermal oxide film (not shown) and an insulating film liner (not shown) may be selectively formed. More specifically, a thermal oxide film is thermally oxidized on the surface of the trench 106 to cure surface damage generated during the previous dry etching process, and is formed inside the trench 106 in a very thin thickness. do. Subsequently, an insulating film liner is formed on the inner side and bottom of the trench 106 where the thermal oxide film is formed, and the surface of the hard mask pattern 105 with a thickness of several hundreds of microseconds.

The insulating film liner is formed to reduce stress in the silicon isolation film (not shown) embedded in the trench 106 by a subsequent process and to prevent impurity ions from penetrating into the field region. The insulating film liner should be formed of a material having a high etching selectivity with respect to a silicon oxide film, which will be described later, under specific etching conditions. For example, the insulating film liner may be formed of silicon nitride (SiN).

Referring to FIG. 3, an undoped silicate glass (USG), O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or a High Density Plasma (HDP) oxide film may be used to fill the trench 106. An oxide film having excellent gap filling properties is deposited by a chemical vapor deposition (CVD) method to form a gap filling oxide film 108. Preferably, a high density plasma oxide film is formed by generating a high density plasma using SiH ₄ , O ₂ and Ar gases as the plasma source. At this time, the trench 106 is embedded by improving the gap filling capability of the high density plasma oxide film so that cracks or voids are not formed in the trench 106.

Further, if necessary, annealing may be performed under a high temperature and inert gas atmosphere of about 800 to 1050 ° C. to densify the gap buried oxide film 108 to lower the wet etch rate for subsequent cleaning processes. have.

Referring to FIG. 4, the gap filling oxide layer 108 is polished to expose the surface of the hard mask pattern 105 by an etch back or chemical mechanical polishing (CMP) method to expose the trench 106. ) To form a field oxide film pattern 110. Subsequently, the nitride layer pattern 104 is removed by a phosphate strip process to form an opening 111 exposing the pad oxide layer pattern 102. In this case, the exposed pad oxide layer pattern 102 functions as a tunnel oxide layer.

In this case, a pad oxide layer pattern 102 is formed in the active region on the semiconductor substrate 100, and a field oxide layer pattern 110 is formed higher than the pad oxide layer pattern 102. The step difference between the pad oxide layer pattern 102 and the field oxide layer pattern 110 corresponds to the height of the removed nitride layer pattern 104.

Referring to FIG. 5, a first conductive layer 112 for forming a floating gate is formed along surfaces of the pad oxide layer pattern 102 and the field oxide layer pattern 110. As the first conductive film 112, polysilicon or amorphous silicon is deposited by a low pressure chemical vapor deposition method and doped with impurities by a doping method. For example, the first conductive layer 112 is doped with a high concentration of N-type impurities, for example, by POCl ₃ diffusion, ion implantation, or in-situ doping.

As illustrated, the formed first conductive layer 112 is formed with irregularities due to the step difference between the pad oxide layer pattern 102 and the field oxide layer pattern 110.

The uneven shape is used to form a U-shaped floating gate (not shown) that will later be formed. Unlike the conventional method, since the floating gate can be formed without a predetermined mold layer, the process can be simplified, thereby reducing the time and cost of the process.

Referring to FIG. 6, the sacrificial layer 114 is formed by depositing an oxide layer having excellent gap filling characteristics such as a USG layer on the first conductive layer 112 by a chemical vapor deposition method so that the opening 111 is filled. do.

Referring to FIG. 7, the sacrificial layer 114 is partially removed to expose the surface of the first conductive layer 112 by performing a chemical mechanical polishing process to form the sacrificial layer pattern 116. In this case, a surface of a portion of the first conductive layer 112 is a portion of the first conductive layer 112 formed on the field oxide layer pattern 110.

Referring to FIG. 8, a portion of the exposed first conductive layer 112 is removed by performing an anisotropic etching process to separate neighboring floating gates 118 from each other, and to simultaneously remove the portion of the field oxide layer pattern 110. Expose the surface. In this case, the etching process is a dry etching process using a mixed gas containing CFx and O ₂ .

As described above, a conventional chemical mechanical polishing process and a dry etching process may be performed in order to separate neighboring floating gates 118.

More specifically, in the related art, a chemical mechanical polishing process is performed on a conductive film for floating gates to separate neighboring floating gates, and polishing is performed on the entire area of the semiconductor substrate because the speed at which the center and edge portions of the semiconductor substrate are polished is different. It is not uniform. In particular, the polysilicon in the ferry region is also less polished so that neighboring floating gates are not separated, causing shorts between the neighboring floating gates.

Meanwhile, in the present exemplary embodiment, after the sacrificial layer 114 is subjected to a chemical mechanical process to expose a portion of the first conductive layer 112 for the floating gate, the exposed first conductive layer 112 is anisotropically etched. It can be completely removed by the process. Therefore, the shorting phenomenon of the floating gate 118 may be reduced by accurately separating the neighboring floating gates 118 as compared with the related art.

Referring to FIG. 9, a portion of the exposed field oxide layer pattern 110 and the sacrificial layer pattern 116 are removed through a wet etch process. When the field oxide pattern 110 and the sacrificial layer pattern 116 are removed, all surfaces except for the bottom surface of the U-shaped floating gate 118 are exposed. This increases the effective area of the dielectric film (not shown) to be formed later.

A portion of the field oxide layer pattern 110 and a portion of the sacrificial layer pattern 116 are etched using a hydrofluoric acid (HF) diluent. In this case, all of the sacrificial layer pattern 116 is to be removed, and a portion of the field oxide layer pattern 110 having the same etching rate is removed while the sacrificial layer pattern 116 is removed.

As shown in FIG. 9, the field oxide layer pattern 110 contacting the outer surface of the floating gate 118 is removed to a height lower than the surface of the semiconductor substrate 100 so that all of the outer surface of the floating gate 118 is exposed. It is desirable to be. This is to further increase the effective area of the dielectric film to be described later.

Referring to FIG. 10, a dielectric film 120 is formed along the floating gate 118. The dielectric film 120 is a composite dielectric film made of an oxide film / nitride film / oxide film (ONO), a high dielectric material film made of a high dielectric constant material, etc. to insulate the floating gate 118 from a control gate (not shown) to be formed later. May be employed.

The composite dielectric film may be formed by an LPCVD process, and the high dielectric constant material film may be formed of Y ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , and the like, and may be atomic layer deposited. It can be formed by a layer deposition (ALD) process or a CVD process

Although not shown in detail, a control gate including a second conductive layer and a third conductive layer is formed on the dielectric layer.

A second conductive film made of polysilicon doped with impurities on the dielectric layer and a third conductive film made of metal silicide such as tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), and tantalum silicide (TaSix). To form a control gate.

The control gate layer is patterned to form a control gate. In addition, the dielectric layer, the floating gate, and the tunnel oxide layer are sequentially patterned to complete the gate structure of the flash memory device.

As described above, according to a preferred embodiment of the present invention, after polishing the sacrificial film formed on the conductive film for the floating gate to expose the surface of a portion of the conductive film, a portion of the exposed conductive film is removed by an etching process U A magnetic floating gate is formed. At the same time, the neighboring floating gates are separated to reduce the shorting of the floating gate.

In addition, the U-shaped floating gate can be formed without any mold layer conventionally used to simplify the process, thereby reducing process time and cost.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (4)

Forming a field oxide pattern protruding from the surface of the substrate such that an opening is formed to expose a portion of the surface of the substrate; Continuously depositing a conductive film for a floating gate on the field oxide pattern and the exposed substrate; Forming a sacrificial layer on the floating gate conductive layer to fill the opening; Polishing the sacrificial film to expose a surface of a portion of the conductive film for the floating gate; And And selectively etching the exposed floating gate conductive film to form node-separated floating gates. The method of claim 1, wherein the etching process is a front side anisotropic etching process. The method of claim 1, further comprising removing a portion of the sacrificial layer and the field oxide layer pattern remaining between the floating gates. The method of claim 1, wherein the field oxide film pattern, Forming a hard mask pattern in which a pad oxide film and a nitride film pattern are stacked on a substrate; Etching the substrate using the hard mask pattern as an etch mask to form a trench; Forming an isolation layer on the substrate to fill the trench; Forming a field oxide layer pattern by polishing the oxide layer for isolation of the device to expose an upper portion of the hard mask pattern; And And removing the nitride film pattern.

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