CN110120363B - Method for forming isolation structure and method for forming semiconductor device - Google Patents
Method for forming isolation structure and method for forming semiconductor device Download PDFInfo
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- CN110120363B CN110120363B CN201810119512.8A CN201810119512A CN110120363B CN 110120363 B CN110120363 B CN 110120363B CN 201810119512 A CN201810119512 A CN 201810119512A CN 110120363 B CN110120363 B CN 110120363B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Abstract
The invention discloses a forming method of an isolation structure and a forming method of a semiconductor device, wherein the forming method of the isolation structure comprises the following steps: providing an active region; forming a front-end material layer on the active region; patterning the front-end material layer to form an opening, wherein residues are formed in the opening; etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue; reducing the width of the protrusion and removing the residue; etching the active region for the second time by taking the initial groove as a reference to form an isolation groove; and forming an isolation structure in the isolation groove. Therefore, the isolation groove is formed by two times of etching, and residues generated in the process of etching the front-end material layer and the active region protrusion defect caused by the residues can be eliminated, so that the isolation structure is normally formed, and the quality of the isolation structure is ensured.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming an isolation structure and a method for forming a semiconductor device.
Background
As the devices of integrated circuits are scaled down, the width and pitch (pitch) of the active area is also reduced. Therefore, the conventional local oxidation of silicon (LOCOS) is gradually replaced by a Shallow Trench Isolation (STI). Shallow trench isolation is more feasible than silicon partial oxide isolation because it does not produce bird's beak(s) features in comparison.
However, in actual production, the quality of the shallow trench isolation structure is still affected for various reasons, and the yield of the device is not ideal.
Disclosure of Invention
The invention aims to provide a method for forming an isolation structure and a method for forming a semiconductor device, which can improve the quality of the isolation structure.
To solve the above technical problem, the present invention provides a method for forming an isolation structure, including:
providing an active region;
forming a front-end material layer on the active region;
patterning the front-end material layer to form an opening, wherein residues are formed in the opening;
etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue;
reducing the width of the protrusion and removing the residue;
etching the active region for the second time by taking the initial groove as a reference to form an isolation groove; and
and forming an isolation structure in the isolation groove.
Optionally, for the method for forming the isolation structure, the step of reducing the width of the protrusion and removing the residue includes:
processing the initial groove in an oxygen atmosphere to form an oxide layer on the bottom wall and the side wall of the initial groove and the outer wall of the protrusion; and
and (5) carrying out wet cleaning.
Optionally, in the method for forming the isolation structure, when the initial groove is processed in an oxygen atmosphere, the temperature is 700-1000 ℃, and the processing time is 2-5 hours.
Optionally, in the method for forming the isolation structure, a mixed solution of hydrofluoric acid and ammonium fluoride is used for cleaning to remove the oxide layer and the residue.
Optionally, for the method for forming the isolation structure, before the processing the initial recess in the oxygen atmosphere, the method further includes:
and bombarding the bumps by adopting plasma.
Optionally, for the forming method of the isolation structure, the plasma includes argon ions, and the bombardment time is 1s to 20 s.
Optionally, for the forming method of the isolation structure, the depth of the first etching is greater than 0 and less than or equal to
Optionally, for the forming method of the isolation structure, the depth of the second etching is greater than 0 and less than or equal to
Optionally, with respect to the method for forming the isolation structure, an upper surface of the isolation structure is flush with an upper surface of the active region.
The invention also provides a method for forming a semiconductor device, which comprises the following steps:
providing an active region;
forming a front-end material layer on the active region;
patterning the front-end material layer to form an opening, wherein residues are formed in the opening;
etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue;
reducing the width of the protrusion and removing the residue;
etching the active region for the second time by taking the initial groove as a reference to form an isolation groove;
forming an isolation structure in the isolation groove; and
forming a functional layer on the isolation structure
Optionally, for the method for forming the semiconductor device, the material of the functional layer includes polysilicon.
In the method for forming an isolation structure and the method for forming a semiconductor device provided by the invention, the method for forming the isolation structure comprises the following steps: providing an active region; forming a front-end material layer on the active region; patterning the front-end material layer to form an opening, wherein residues are formed in the opening; etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue; reducing the width of the protrusion and removing the residue; etching the active region for the second time by taking the initial groove as a reference to form an isolation groove; and forming an isolation structure in the isolation groove. Therefore, the isolation groove is formed by two times of etching, residues generated when the front-end material layer is etched and the active region protrusion defect caused by the residues can be effectively eliminated, so that the isolation structure is normally formed, and the quality of the isolation structure is ensured to be good. In addition, the semiconductor device formed on the basis avoids the conduction of the active region and the functional layer, and finally improves the reliability of the semiconductor device.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device;
FIG. 2 is a flow chart of a method of forming a semiconductor device in one embodiment of the invention;
FIG. 3 is a schematic diagram of providing an active region and forming a front end material layer on the active region in one embodiment of the present invention;
FIG. 4 is a schematic view of forming an opening in one embodiment of the present invention;
FIG. 5 is a schematic illustration of the formation of an initial groove in one embodiment of the present invention;
FIG. 6 is a schematic view of plasma processing performed in one embodiment of the present invention;
FIG. 7 is a schematic illustration of a sacrificial oxidation performed in accordance with an embodiment of the present invention;
FIG. 8 is a schematic illustration of an embodiment of the present invention after a wet clean;
FIG. 9 is a schematic view of the formation of isolation grooves in one embodiment of the present invention;
FIG. 10 is a schematic illustration of the formation of an isolation structure in one embodiment of the present invention;
FIG. 11 is a schematic illustration of the formation of a functional layer in one embodiment of the present invention;
FIG. 12 is a diagram of experimental verification of the present invention.
Detailed Description
The method of forming the isolation structure and the method of forming the semiconductor device of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that those skilled in the art can modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, pad, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
The inventors have found in production that devices with high voltage circuitry have undesirable practical properties. After analysis, a part of the structure of the high-voltage circuit with the abnormality is shown in fig. 1, and the part of the semiconductor device comprises an active region 1, an isolation structure 2 and a functional layer 3, but the active region 1 is provided with a protrusion 4 which is positioned in the isolation structure 2. The active region 1 and the functional layer 3 are bridged on by the application of a voltage, in particular a higher voltage, which affects the quality of the device.
Further research and development finds that when active area etching is carried out, for example, photoresist, a mask layer and the like cannot be well removed to form residues 5, and the residues 5 obstruct normal etching of the active area 1 below the residues, so that the bumps 4 are formed.
In contrast, the inventors tried to optimize the etching process of the active region, strictly control the quality of the developing solution, and perform brushing after the formation of the dielectric anti-reflection film layer (DARC) on the active region, with little effect.
Based on this, the inventor adjusts the etching process of the active region, and solves the above problems. As shown in fig. 2, the method for forming a semiconductor device of the present invention includes:
step S11, providing an active region;
step S12, forming a front end material layer on the active region;
step S13, patterning the front end material layer to form an opening, wherein a residue is formed in the opening;
step S14, etching the active area for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue;
step S15, reducing the width of the protrusion, and removing the residue;
step S16, etching the active area for the second time by taking the initial groove as a reference to form an isolation groove;
step S17, forming an isolation structure in the isolation groove; and
step S18, forming a functional layer on the isolation structure.
The following describes a method for forming an isolation structure and a method for forming a semiconductor device in detail, with reference to the accompanying drawings.
As shown in fig. 3, for step S11, an active region 10 is provided. In one embodiment, the active region 10 is a portion of a semiconductor substrate, and it is understood that the active region 10 is formed after doping the semiconductor substrate. Specifically, the semiconductor substrate may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, Silicon On Insulator (SOI), or the like. By way of example, in the present embodiment, the semiconductor substrate is made of a single crystalline silicon material. A buried layer (not shown in the figure) or the like may also be formed in the semiconductor substrate. In addition, for PMOS, an N-well (not shown in the figure) may be formed in the semiconductor substrate, and one or more small-dose boron implants may be performed on the entire N-well for adjusting the threshold voltage Vth of PMOS.
With continued reference to fig. 3, for step S12, step S12, a front end material layer 20 is formed on the active region 10. Specifically, the front end material layer 20 includes a Pad Oxide layer (Pad Oxide)21, such as a silicon Oxide material, which may have a thickness of
The hard mask layer 22 is, for example, a silicon nitride material, and may have a thickness of
Dielectric anti-reflective coating (DARC) layer 23, such as silicon oxynitride, having a thickness of
And a photoresist layer 24, which may be of a thickness of
The formation of the front-end material layer 20 described above can be done according to the prior art and will not be described in detail here.
Next, referring to fig. 4, for step S13, the front-end material layer 20 is patterned to form an opening 30, and the opening 30 has a residue 40 formed therein. The opening 30 may be formed by photolithography and etching processes according to the specific material of the front-end material layer 20. The residue 40 may be formed due to residues of photoresist layer, deposition non-uniformity of DARC, and the like. The residue 40 adheres to the active region 10 and is not easily removed, so the presence of the residue 40 will affect the etching of the active region 10 therebelow. It is understood that the residue 40 may be more and less distributed, and is only illustrated in fig. 4.
Next, referring to fig. 5, in step S14, the active region 10 is first etched with the opening as a reference to form an initial groove 31, a protrusion 50 is formed in the initial groove 31, and the protrusion 50 is located below the residue 40. As mentioned above, the presence of residue 40 affects the etching of the active region 10 thereunder, thus resulting in the formation of said protrusion 50. In one embodiment, the protrusions 50 are tapered, having a greater width (specifically, e.g., diameter) farther away from the residue 40. It will be appreciated that in the presence of such a protrusion 50, direct filling of the isolation layer without removal may easily result in breakdown failure of the isolation layer.
In one embodiment, the depth of the first etching is greater than 0 and less than or equal to
Then, referring to fig. 6-8, for step S15, the width of the protrusion 50 is reduced, and the residue is removed.
The method specifically comprises the following steps:
as shown in fig. 6, the protrusions 50 are bombarded with a plasma 60.
In one embodiment, the plasma may be comprised of argon (Ar) ions and the bombardment time may be 1s to 20s, such as 5s, 8s, 10s, 15s, and the like.
The plasma 60 bombardment process is shown as plasma etching, thus allowing the width of the protrusions 50 to be reduced for subsequent removal.
It will be appreciated that the bombardment of the plasma 60 may also have an effect on the residue 40, such as breaking its viscosity, causing loosening, displacement, etc., between the residue 40 and the protrusions 50, facilitating subsequent removal.
Referring to fig. 7, the initial trench is wet-oxidized, specifically, the initial trench is treated in an oxygen atmosphere to form an oxide layer 51 on the bottom wall and the sidewall of the initial trench and the outer wall of the protrusion 50.
In one embodiment, the temperature is 700-1000 ℃ and the treatment time is 2-5 hours, such as 2.5 hours, 3 hours, 3.5 hours, 4 hours, 4.5 hours, etc.
In one embodiment, a small amount of hydrogen may be further incorporated into the oxygen gas, for example, the volume ratio of oxygen gas to hydrogen gas may be 400:1 to 800:1, or even lower.
Referring to fig. 8, a wet cleaning process is performed.
In one embodiment, hydrofluoric acid (HF) and ammonium fluoride (NH) are used4F) The mixed solution of (a) is washed to remove the oxide layer and the residue.
Since the plasma bombardment reduces the viscosity of the residue and may displace it, the residue can be easily washed away when wet cleaning is performed, and the sacrificial oxidation is performed so that the outer wall of the protrusion 50 becomes silicon oxide, and the connection with the residue 40 is broken after the reaction with the acid.
By sacrificial oxidation and cleaning removal, the possible lattice defects can be improved, and subsequent etching and formation of an isolation structure are facilitated.
With continued reference to fig. 8, after the step S15, the protrusions 50 become smaller and the residue is removed. It will be appreciated that since the residue may actually be in a larger and smaller distribution, removal is understood to reduce the amount of residue, and may, of course, be complete, but in the case of filling, when the amount of residue is reduced to a certain extent, for example, to the acceptable range of defect detection equipment, it is considered to be removed. Since the protrusions 50 become small, they are easily removed at the time of subsequent etching, thereby helping the final isolation grooves to be formed with good quality.
Then, referring to fig. 9, for step S16, the active region 10 is etched for the second time by using the initial recess as a reference to form an isolation recess 32.
In one embodiment, the thickness of the second etching is greater than 0 and less than or equal to
The above-mentionedThe second etching may employ substantially the same or similar conditions as the first etching, and will not be described in detail herein.
In one embodiment, the total thickness of the first and second etches reaches the depth of the isolation recess 32.
After the second etching, the isolation groove 32 is formed to avoid the existence of the protrusion, thereby facilitating the formation of the isolation structure.
The isolation trenches 32 are of better quality and thus contribute to better critical dimensions.
After the isolation groove 32 is formed, further, the front end material layer 20 may be removed.
Thereafter, referring to fig. 10, for step S17, an isolation structure 60 is formed in the isolation groove. In one embodiment, the isolation structure 60 may comprise at least one of silicon nitride, silicon oxide, silicon oxynitride, and the like. The upper surface of the isolation structure 60 may, for example, be flush with the upper surface of the active region 10, which may be formed by a planarization process, such as a chemical mechanical polishing process, after forming a layer of isolation material in the isolation trench, to obtain the desired isolation structure.
Thus, the method for forming the isolation structure of the present invention is described.
The method for forming the semiconductor device of the present invention is completed on the basis of the method for forming the isolation structure. Therefore, the same steps can be seen in the above-mentioned step S11 to step S17.
Thereafter, referring to fig. 11, for step S18, a functional layer 70 is formed on the isolation structure 60.
In one embodiment, the material of the functional layer 70 includes polysilicon, and specifically, High Resistance Polysilicon (HRP).
As can be seen from fig. 11, the functional layer 70 is not in contact with the active region 10. Isolation is achieved by isolation structure 60.
Referring to fig. 12, a semiconductor device formed by the method of the present invention and the semiconductor device shown in fig. 1 are compared in terms of yield. In fig. 12, the YIELD (YIELD) is plotted on the ordinate, which can be counted in percent (%), for example, 92 on the ordinate refers to 92%.
In this comparison, a denotes the semiconductor device shown in fig. 1, B denotes the semiconductor device obtained by the method of the present invention, N is the number of samples, Avg is the mean value, Std is the standard deviation, and Min is the minimum value.
It can be seen that the average yield of the semiconductor device obtained by the method of the present invention is about 96.9%, which is about 3% higher than the yield of the semiconductor device shown in fig. 1. And the convergence is better, which shows that the product quality reliability is good.
Furthermore, the semiconductor device obtained by the method of the invention can show great advantages especially when being applied to a high-voltage circuit (for example, 10-20V voltage is applied to HRP), and the normal-voltage circuit (compared with a circuit with lower voltage than the high-voltage circuit) is not easy to be abnormal due to the lower voltage, so that the improvement is not very obvious, but the potential risk is reduced, and the semiconductor device still has good practicability.
In summary, in the method for forming an isolation structure and the method for forming a semiconductor device provided by the present invention, the method for forming an isolation structure includes: providing an active region; forming a front-end material layer on the active region; etching the front-end material layer to form an opening, wherein residues are formed in the opening; etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue; reducing the width of the protrusion and removing the residue; etching the active region for the second time by taking the initial groove as a reference to form an isolation groove; and forming an isolation structure in the isolation groove. Therefore, the isolation groove is formed by two times of etching, residues generated when the front-end material layer is etched and the active region protrusion defect caused by the residues can be effectively eliminated, so that the isolation structure is normally formed, and the quality of the isolation structure is ensured to be good. In addition, the semiconductor device formed on the basis avoids the conduction of the active region and the functional layer, and finally improves the reliability of the semiconductor device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. A method for forming an isolation structure, comprising:
providing an active region;
forming a front-end material layer on the active region;
patterning the front-end material layer to form an opening, wherein residues are formed in the opening;
etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue;
reducing the width of the protrusion and removing the residue;
etching the active region for the second time by taking the initial groove as a reference to form an isolation groove; and
and forming an isolation structure in the isolation groove.
2. The method of forming an isolation structure according to claim 1, wherein the step of reducing the width of the protrusion and removing the residue comprises:
processing the initial groove in an oxygen atmosphere to form an oxide layer on the bottom wall and the side wall of the initial groove and the outer wall of the protrusion; and
and (5) carrying out wet cleaning.
3. The method of claim 2, wherein the initial recess is processed in an oxygen atmosphere at a temperature of 700-1000 ℃ for 2-5 hours.
4. The method of claim 2, wherein a mixed solution of hydrofluoric acid and ammonium fluoride is used for cleaning to remove the oxide layer and the residue.
5. The method of forming an isolation structure of claim 2, wherein prior to processing said initial recess in an oxygen atmosphere, further comprising:
and bombarding the bumps by adopting plasma.
6. The method of claim 5, wherein the plasma comprises argon ions and the bombardment time is 1s to 20 s.
7. The method for forming an isolation structure according to claim 1, wherein the depth of the first etching is greater than 0 and less than or equal to
8. The method for forming the isolation structure according to claim 1 or 7, wherein the depth of the second etching is greater than 0 and less than or equal to
9. The method of claim 1, wherein an upper surface of the isolation structure is flush with an upper surface of the active region.
10. A method of forming a semiconductor device, comprising:
providing an active region;
forming a front-end material layer on the active region;
patterning the front-end material layer to form an opening, wherein residues are formed in the opening;
etching the active region for the first time by taking the opening as a reference to form an initial groove, wherein a bulge is formed in the initial groove and is positioned below the residue;
reducing the width of the protrusion and removing the residue;
etching the active region for the second time by taking the initial groove as a reference to form an isolation groove;
forming an isolation structure in the isolation groove; and
and forming a functional layer on the isolation structure.
11. The method for forming a semiconductor device according to claim 10, wherein a material of the functional layer includes polysilicon.
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| US6395620B1 (en) * | 1996-10-08 | 2002-05-28 | Micron Technology, Inc. | Method for forming a planar surface over low density field areas on a semiconductor wafer |
| KR20060125979A (en) * | 2005-06-03 | 2006-12-07 | 삼성전자주식회사 | Method of manufacturing a floating gate in non-volatile memory device |
| CN102157429A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure |
| CN103227111A (en) * | 2013-04-09 | 2013-07-31 | 上海华力微电子有限公司 | Manufacturing method of semiconductor device |
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2018
- 2018-02-06 CN CN201810119512.8A patent/CN110120363B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395620B1 (en) * | 1996-10-08 | 2002-05-28 | Micron Technology, Inc. | Method for forming a planar surface over low density field areas on a semiconductor wafer |
| KR20060125979A (en) * | 2005-06-03 | 2006-12-07 | 삼성전자주식회사 | Method of manufacturing a floating gate in non-volatile memory device |
| CN102157429A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of shallow trench isolation structure |
| CN103227111A (en) * | 2013-04-09 | 2013-07-31 | 上海华力微电子有限公司 | Manufacturing method of semiconductor device |
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