KR20030056388A - Method for forming trench isolation in semiconductor device - Google Patents

Method for forming trench isolation in semiconductor device Download PDF

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Publication number
KR20030056388A
KR20030056388A KR1020010086592A KR20010086592A KR20030056388A KR 20030056388 A KR20030056388 A KR 20030056388A KR 1020010086592 A KR1020010086592 A KR 1020010086592A KR 20010086592 A KR20010086592 A KR 20010086592A KR 20030056388 A KR20030056388 A KR 20030056388A
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South Korea
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forming
semiconductor device
trench
layer
film
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KR1020010086592A
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Korean (ko)
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정이선
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주식회사 하이닉스반도체
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Publication of KR20030056388A publication Critical patent/KR20030056388A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to be capable of reducing corrosion of a buried oxide layer, improving hump and obtaining etch margins by using etching selectivity between oxynitride and oxide. CONSTITUTION: A trench is formed in a semiconductor substrate(11) by using a pad oxide pattern and a nitride pattern as a mask. A buried oxide layer is filled into the trench. The buried oxide layer is annealed by using N2O gas, thereby forming an oxinitride layer on the surface of the buried oxide layer. After removing the nitride pattern, the pad oxide pattern is removed by cleaning process, thereby forming an isolation layer(19a).

Description

반도체 소자의 소자분리막 형성방법{METHOD FOR FORMING TRENCH ISOLATION IN SEMICONDUCTOR DEVICE}METHODS FOR FORMING TRENCH ISOLATION IN SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는 N2O가스를 이용한 열처리로써 소자분리막의 침식 현상을 방지할 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly to a method of forming a device isolation film of a semiconductor device that can prevent the erosion of the device isolation film by heat treatment using N 2 O gas.

일반적으로, 반도체 소자는 개개의 회로 패턴을 전기적으로 분리하기 위한 소자분리 영역을 포함한다. 특히, 반도체 소자가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자분리 영역의 축소에 대한 연구가 활발히 진행되고 있다. 그 이유는 소자분리 영역의 형성은 모든 반도체 소자의 제조 단계의 초기 단계로서 활성영역의 크기 및 후공정 단계의 공정 마진을 좌우되기 때문이다.Generally, semiconductor devices include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices become highly integrated and miniaturized, research on not only reducing the size of each individual device but also reducing the device isolation region is being actively conducted. The reason for this is that the formation of the device isolation region depends on the size of the active region and the process margin of the post-process step as the initial stages of all semiconductor device manufacturing steps.

최근까지 반도체 소자의 제조에 널리 이용되는 로코스(LOCOS) 소자분리 방법은 반도체 소자가 고집적화 되어감에 따라 그 한계점이 이르렀다. 이에 따라 고집적화된 반도체 소자의 소자분리에 적합한 기술로는 트랜치를 이용한 섈로우 트렌치 분리(STI:SHALLOW TRENCH ISOLATION) 방법이 제안되었다.Until recently, the LOCOS device isolation method, which is widely used in the manufacture of semiconductor devices, has reached its limit as semiconductor devices have been highly integrated. Accordingly, as a technique suitable for device isolation of highly integrated semiconductor devices, a shallow trench isolation (STI) method using trenches has been proposed.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도이다.1A to 1C are cross-sectional views illustrating processes of forming a device isolation layer of a semiconductor device according to the prior art.

종래 기술에 따른 반도체 소자의 소자분리막 형성방법은, 도 1a에 도시된 바와 같이, 먼저 반도체 기판(1) 표면을 산화시켜 패드 산화막(3)을 성장시키고, 상기 패드 산화막(3)상에 질화물을 증착시켜 패드 질화막(5)을 형성한다.In the method of forming a device isolation film of a semiconductor device according to the prior art, as shown in FIG. 1A, first, the surface of the semiconductor substrate 1 is oxidized to grow a pad oxide film 3, and nitride is deposited on the pad oxide film 3. The vapor deposition is performed to form the pad nitride film 5.

이어서, 도 1b에 도시된 바와 같이, 상기 패드 질화막(5)을 선택적으로 패터닝한 다음, 상기 패터닝된 패드 질화막(5a)을 마스크로 상기 패드 산화막(3)과 기판(1)을 선택적으로 제거하여 트렌치(7)를 형성한다.Subsequently, as illustrated in FIG. 1B, the pad nitride layer 5 is selectively patterned, and then the pad oxide layer 3 and the substrate 1 are selectively removed using the patterned pad nitride layer 5a as a mask. The trench 7 is formed.

그다음, 상기 트렌치(7)를 매립하도록 산화막 등을 상기 기판(1) 전면상에 증착한 다음, 상기 패드 질화막(5a)을 연마정지층으로 하는 연마공정을 진행하여 평탄화시킨다.Then, an oxide film or the like is deposited on the entire surface of the substrate 1 so as to fill the trench 7, and then the polishing process is performed to make the pad nitride film 5a an abrasive stop layer and planarized.

이어서, 상기 잔류하는 패드 질화막(5a)를 제거한후, 상기 패드 산화막(3a)마저 세정공정으로 제거하여 소자분리막(9a)을 완성한다.Subsequently, the remaining pad nitride film 5a is removed, and then the pad oxide film 3a is also removed by a cleaning process to complete the device isolation film 9a.

그러나, 종래 기술에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the method of forming a device isolation film of a semiconductor device according to the prior art has the following problems.

종래 기술에 있어서는, 도 1c에 도시된 바와 같이, 소자분리막 형성공정이 완료된 후에는 상기 소자분리막(9a)의 모서리부(A)가 리세스(recess) 된다. 이와 같이, 소자분리막이 리세스(recess)되면 소자 동작시 전기적 필드가 이에 집중되어 소자의 이상동작을 유발하고, 또한 접합(junction) 측면에서는 이 지역을 통하여 임플랜트 도우즈(implant dose)가 더 깊이 침투하여 누설전류가 과도하게 흐르는 경향이 발생한다는 문제점이 있다.In the prior art, as shown in FIG. 1C, the corner portion A of the device isolation film 9a is recessed after the device isolation film forming process is completed. As such, when the device isolation layer is recessed, an electrical field is concentrated in the device operation, causing an abnormal operation of the device. Also, on the junction side, the implant dose is deeper through this area. There is a problem that the leakage current tends to penetrate excessively.

이러한 현상을 제거하기 위해 종래에는 폴리실리콘 또는 질화막 등으로 스페이서를 형성하는 방안이 있었으나, 이러한 방안은 증착공정이 추가되어 후속공정에서 많은 문제점이 발생하게 된다는 문제점이 있다.In order to eliminate this phenomenon, there have been conventional methods of forming a spacer using polysilicon or a nitride film, but such a method has a problem that many problems occur in subsequent processes due to the addition of a deposition process.

이에, 본 발명은 상기 종래 기술의 제반 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 옥시나이트라이드(oxynitride)가 옥사이드(oxide) 보다식각 속도가 느리다는 원리를 이용하여 트렌치를 매립하는 필드 옥사이드(field oxide)의 침식을 감소시키는 반도체 소자의 소자분리막 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the problems of the prior art, an object of the present invention is to fill the trench using the principle that oxynitride is slower than the oxide (etch) etching rate Disclosed is a method of forming a device isolation film of a semiconductor device to reduce the erosion of oxide (field oxide).

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도.1A to 1C are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도.2A through 2E are cross-sectional views of processes illustrating a method of forming an isolation layer of a semiconductor device in accordance with the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

11; 반도체 기판13; 패드 산화막11; Semiconductor substrate 13; Pad oxide

15; 패드 질화막17; 트렌치15; Pad nitride film 17; Trench

18; 라이너(liner)19; 매립 산화막18; Liner 19; Buried oxide film

19a; 소자분리막21; 게이트 산화막19a; An isolation layer 21; Gate oxide

23; 폴리실리콘층23; Polysilicon layer

상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 반도체 기판상에 트렌치를 형성하는 단계; 상기 트렌치 내면에 라이너를 형성하는 단계; 상기 트렌치를 매립하는 산화막을 형성하는 단계; 상기 산화막을 N2O를 이용하여 어닐링하는 단계; 및 상기 산화막이 형성된 기판을 세정하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming an isolation layer for a semiconductor device, the method including forming a trench on a semiconductor substrate; Forming a liner on the inner surface of the trench; Forming an oxide film filling the trench; Annealing the oxide film using N 2 O; And cleaning the substrate on which the oxide film is formed.

이하, 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 도시한 공정별 단면도이다.2A through 2E are cross-sectional views illustrating processes of forming an isolation layer of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 소자분리막 형성방법은, 도 2a에 도시된 바와 같이, 실리콘과 같은 반도체 원소로 구성된 기판(11) 표면을 산화시켜 패드 산화막(13)을 형성하고, 상기 패드 산화막(13)상에 질화물을 증착하여 패드 질화막(15)을 형성한다.In the method of forming a device isolation film of a semiconductor device according to the present invention, as illustrated in FIG. 2A, a pad oxide film 13 is formed by oxidizing a surface of a substrate 11 made of a semiconductor element such as silicon, and the pad oxide film 13. Nitride is deposited on the pad) to form the pad nitride film 15.

그다음, 상기 패드 질화막(15)을 패터닝하고, 상기 패터닝된 패드 질화막(15)을 마스크로 상기 패드 산화막(13)과 기판(11)을 선택적으로 제거하여 상기 기판(11)에 트렌치(17)를 형성한다.Next, the pad nitride layer 15 is patterned, and the pad oxide layer 13 and the substrate 11 are selectively removed using the patterned pad nitride layer 15 as a mask to form the trench 17 in the substrate 11. Form.

이어서, 도 2b에 도시된 바와 같이, 상기 트렌치(17) 내표면을 산화시켜 라이너(18;liner)를 형성한다.Then, as shown in FIG. 2B, the inner surface of the trench 17 is oxidized to form a liner 18.

이후에, 도 2c에 도시된 바와 같이, 상기 트렌치(17)를 매립할 수 있도록, 예를 들면, 고밀도 플라즈마(HDP;high density plasma) 산화막과 같은 갭필(gap fill) 물질(19;이하 매립 산화막이라 한다)을 상기 기판(11) 전면상에 증착한 다음, 화학적기계적 연막공정으로 평탄화를 실시하여 상기 트렌치(17)를 매립하도록 한다.Subsequently, as shown in FIG. 2C, a gap fill material 19 such as a high density plasma (HDP) oxide film 19 (hereinafter, a buried oxide film) may be used to fill the trench 17. And the planarization process are deposited on the entire surface of the substrate 11, and then planarized by a chemical mechanical deposition process to fill the trench 17.

그다음, 도 2d에 도시된 바와 같이, 상기 기판(11) 전체 구조를 일정한 노(furnace)에서 약 1분 내지 240분 정도의 시간으로 N2O분위기에서 어닐링(annealing)을 진행한다. 이때, 상기 어닐링 온도는 약 600 내지 1,200℃ 범위로 하고, 상기 N2O가스는 약 10sccm 내지 10slm 정도의 유동속도로 공급한다.Next, as shown in FIG. 2D, the entire structure of the substrate 11 is annealed in an N 2 O atmosphere for about 1 to 240 minutes in a constant furnace. At this time, the annealing temperature is in the range of about 600 to 1,200 ℃, the N 2 O gas is supplied at a flow rate of about 10sccm to 10slm.

상기와 같은 조건으로 어닐링을 진행하면 다음과 같은 반응을 거쳐 NO와 N 및 O 등이 상기 매립 산화막(19) 내부로 침투하여 들어가게 된다.When the annealing is performed under the above conditions, NO, N, O, and the like penetrate into the buried oxide film 19 through the following reaction.

N2O -> N2+ ON 2 O-> N 2 + O

2N2O + O -> 2NO2N 2 O + O-> 2NO

2N2O -> N2+ O2 2N 2 O-> N 2 + O 2

상기와 같은 반응을 거쳐 상기 매립 산화막(19)내로 침투된 NO 와 N 등에서 얻을 수 있는 N 농도는, 도 2d의 (B)에 도시된 바와 같이, N2O 어닐링 특성상 상기매립 산화막(19) 표면에서 높게 나오고 표면으로부터 깊어질수록 점점 감소하는 경향을 보인다.As shown in (B) of FIG. 2D, the concentration of N obtained from NO, N, and the like penetrated into the buried oxide film 19 through the reaction as described above, is a surface of the buried oxide film 19 due to N 2 O annealing characteristics. It tends to decrease as it emerges higher at and deeper from the surface.

그 결과, 상기 매립 산화막(19)은 그 표면이 옥시나이트라이드(oxynitride)화 되는데, 상기 옥시나이트라이드는 일반적인 산화막(oxide) 보다는 식각속도가 느리다. 한편, 부가적으로 상기와 같이 NO 어닐링을 진행하면 상기 트렌치(17)의 상단 모서리부의 곡선화도 이룰 수가 있게 된다.As a result, the buried oxide film 19 has an oxynitride surface, and the oxynitride has a lower etch rate than a normal oxide film. On the other hand, if the NO annealing proceeds as described above, the upper edge portion of the trench 17 can also be curved.

이어서, 도 2e에 도시된 바와 같이, 상기 패드 질화막(15)을 제거한 다음 불산(HF)을 이용한 세정공정으로 상기 패드 산화막(13)도 제거한다. 이때, 상기 세정 공정시 상기 매립 산화막, 즉 소자분리막(19a) 표면에 형성된 옥시나이트라이드는 상기한 바와 같이 식각속도가 낮으므로 산화막의 침식이 없게 된다.Subsequently, as shown in FIG. 2E, the pad nitride layer 15 is removed and then the pad oxide layer 13 is also removed by a cleaning process using hydrofluoric acid (HF). At this time, the oxynitride formed on the buried oxide film, that is, the surface of the device isolation film 19a during the cleaning process has a low etching rate as described above, so that the oxide film is not eroded.

그후, 상기 소자분리막(19a)을 포함한 상기 기판(11) 전면상에 게이트 산화막(21)과 게이트 전극용으로 사용될 도전층, 예를 들면 폴리실리콘층(23)을 증착하고 예정된 후속공정을 진행한다.Thereafter, a conductive layer, for example, a polysilicon layer 23, to be used for the gate oxide film 21 and the gate electrode is deposited on the entire surface of the substrate 11 including the device isolation film 19a, and a predetermined subsequent process is performed. .

본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 소자분리막 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of forming an isolation layer of a semiconductor device according to the present invention has the following effects.

본 발명에 있어서는, 옥시나이트라이드가 옥사이드 보다 식각속도가 느리다는 원리를 이용하여 소자분리막 형성공정시 트렌치를 매립하는 산화막 침식을 감소시켜 험프를 개선할 수 있으며, 잔류물에 따른 문제를 줄여 식각마진을 확보할 수 있는 효과가 있다.In the present invention, by using the principle that oxynitride has a lower etching rate than oxide, it is possible to improve the hump by reducing the oxide erosion to fill the trench during the device isolation film forming process, and to reduce the etch margin by reducing the problem caused by residue There is an effect that can be secured.

Claims (4)

반도체 기판상에 트렌치를 형성하는 단계;Forming a trench on the semiconductor substrate; 상기 트렌치 내면에 라이너를 형성하는 단계;Forming a liner on the inner surface of the trench; 상기 트렌치를 매립하는 산화막을 형성하는 단계;Forming an oxide film filling the trench; 상기 산화막을 N2O를 이용하여 어닐링하는 단계; 및Annealing the oxide film using N 2 O; And 상기 산화막이 형성된 기판을 세정하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.And cleaning the substrate having the oxide film formed thereon. 제1항에 있어서,The method of claim 1, 상기 N2O를 이용한 어닐링은 600℃ 내지 1,200℃ 온도에서 진행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Annealing using the N 2 O is a device isolation film forming method of a semiconductor device, characterized in that proceeding at 600 ℃ to 1,200 ℃ temperature. 제1항에 있어서,The method of claim 1, 상기 N2O를 이용한 어닐링은 1분 내지 240분 동안 진행하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.Annealing using the N 2 O device separation film forming method of the semiconductor device, characterized in that for 1 to 240 minutes. 제1항에 있어서,The method of claim 1, 상기 N2O를 이용한 어닐링은 N2O 가스의 유동을 10sccm 내지 10slm으로 하는것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The annealing using the N 2 O is a method of forming a device isolation film of a semiconductor device, characterized in that the flow of N 2 O gas to 10sccm to 10slm.
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KR20000077020A (en) * 1999-05-12 2000-12-26 윤종용 Trench isolation method, Method of manufacturing semiconductor device having trench and Semiconductor device formed thereby
KR20010058946A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a field oxide of semiconductor device

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JP2000306990A (en) * 1999-04-20 2000-11-02 Sony Corp Manufacture of semiconductor device
KR20000077020A (en) * 1999-05-12 2000-12-26 윤종용 Trench isolation method, Method of manufacturing semiconductor device having trench and Semiconductor device formed thereby
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