KR100452274B1 - method of forming gate electrode in Non-Volatile Memory cell - Google Patents

Abstract

A method of forming a gate electrode of a nonvolatile memory cell is disclosed. The method forms first oxide film patterns having a positive slope by forming a first trench that exposes an etch stop film surface of a substrate on which a gate oxide film, an etch stop film, and a first oxide film are sequentially stacked. After the nitride is buried in the first trench to form a first nitride film pattern, a second trench is formed to separate the substrate by using an etching mask. After the oxide material is buried in the second trench to form the device isolation pattern, the first isolation layer pattern and the etch stop layer pattern exposed by the device isolation layer pattern are removed using the device isolation pattern. By depositing a polysilicon layer between the device isolation layer patterns, a gate electrode without voids is formed.

Description

Method of forming gate electrode in non-volatile memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode of a nonvolatile memory cell including a method of forming a device isolation film pattern to which a damaging process is applied.

In general, semiconductor memory devices are classified into volatile memory (Volatile Memory, VM) and non-volatile memory (NVM). Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be input and stored when power is applied, but data cannot be saved because of volatilization when power is removed. Has On the other hand, nonvolatile memory, which is mostly occupied by ROM (Read Only Memory), is characterized in that data is preserved even when power is not applied.

The nonvolatile memory may be classified into an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, and the like. Here, the flash memory cell generally has a structure including a floating gate, at least one tunnel oxide layer or a dielectric layer formed on the silicon substrate, and a control gate. Data storage of flash memory cells having such a structure is achieved by applying an appropriate voltage to the control gate and the substrate to insert or draw electrons into the floating gate.

1A to 1D are cross-sectional views illustrating a method of forming a nonvolatile memory cell to which a conventional method of forming a device isolation layer pattern is applied.

1A and 1D, the gate oxide film 12, the first polysilicon film 14, and the nitride film 16 are sequentially formed on the silicon substrate 10. Subsequently, the first trenches 20 may be dry-etched by sequentially etching the substrate 10 on which the nitride film 16, the first polysilicon film 14, and the gate oxide film 12 are sequentially stacked, using a photoresist pattern as an etching mask. ).

Subsequently, an insulating oxide material is buried in the first trench 20 to form device isolation layer patterns 22 that may be divided into an active region and a field region of the substrate 10, as illustrated in FIG. 1C.

After removing the nitride film pattern 14a positioned between the device isolation layer patterns 22, a second polysilicon layer 24 is deposited to bury a polysilicon material between the device isolation layer patterns 22. A floating gate 26 of a nonvolatile memory cell as shown in 1d is formed.

However, when the second polysilicon film 24 is formed between the device isolation layer patterns 22, the sidewalls of the device isolation layer pattern 22 have a vertical or negative slope structure as shown in FIG. 2. As a result, it can be seen that voids are formed in the second polysilicon film 24.

In addition, a predetermined step is generated in the active region and the field region due to the variation in the thickness of the film polished during the chemical mechanical polishing process for forming the device isolation layer pattern 22, and the first polysilicon for the gate electrode stacked in a subsequent process. Stringer defects occur when etching the membrane. In this case, the stringer electrically shorts adjacent gate electrodes, thereby causing a problem of deteriorating an electrical characteristic of the device of the memory cell.

Accordingly, an object of the present invention is to provide a method of forming a nonvolatile memory cell in which voids and stringers do not occur in a gate electrode by forming a device isolation film pattern having a good positive profile by a damaging process.

1A to 1D are flowcharts illustrating a method of forming a gate electrode of a nonvolatile memory cell to which a conventional method of forming a device isolation layer pattern is applied.

2 is a SEM photograph showing a problem occurring when a gate electrode is formed on a substrate having a conventional device isolation layer pattern formed thereon.

3A to 3J are process flowcharts illustrating a method of forming a gate electrode of a nonvolatile memory cell according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 104 gate oxide film

108: etch stop film 112: first oxide film

116: first photoresist pattern 120: first trench

122: first silicon nitride film pattern 126: first structure

132: second trench 136: device isolation film

140: floating gate 144: interlayer dielectric film

148: control gate

In order to achieve the above object, the present invention provides a substrate in which a gate oxide film, an etch stop film, and a first oxide film are sequentially stacked. The first oxide layer patterns having a positive slope are formed by forming a first trench in the first oxide layer exposing the surface of the etch stop layer. Nitride is buried in the first trenches between the first oxide layer patterns to form a first nitride layer pattern. Using the first nitride layer pattern as an etch mask, a second trench is formed to separate the substrates sequentially stacked on the first oxide layer pattern, the etch stop layer, and the gate oxide layer. An oxide material is buried in the second trench to form an isolation pattern. And removing a portion of the first nitride layer pattern and the etch stop layer pattern exposed by the device isolation layer pattern by using the device isolation layer pattern as an etch mask. It is.

Therefore, the device isolation film pattern, which is a field oxide film formed by the above method, has a positive profile because portions exposed on the substrate have a positive profile, and voids are generated in the polysilicon film pattern formed when the polysilicon film is buried between the device isolation film patterns. In addition, since the edge portion of the polysilicon layer pattern is not buried inside the device isolation layer pattern, the electrical characteristics of the nonvolatile memory cell may be improved.

Hereinafter, the present invention will be described in detail.

In the method of forming a device isolation layer pattern of a nonvolatile memory cell of the present invention, first a gate oxide layer, an etch stop layer, and a first oxide layer are sequentially stacked on a substrate, and then a first photoresist pattern defining an active region in the first oxide layer. To form.

Subsequently, the first oxide layer is dry-etched using the first photoresist pattern as an etch mask to form a first trench that exposes the surface of the etch stop layer. Here, the first oxide film has first oxide film patterns having a positive slough by the first trench.

In addition, after the first nitride film is formed on the first trenches and the first oxide film patterns between the first oxide film patterns, the first nitride film on the first oxide film patterns is removed by a CMP process. A first nitride film pattern existing only inside the first trench is formed.

Subsequently, using the first nitride layer pattern as an etching mask, a second trench for dividing the substrate sequentially stacked on the first oxide layer pattern, the etch stop layer, and the gate oxide layer into a field region and an active region is formed. In detail, the method of forming the second trench may be performed by first etching the first oxide layer pattern, the etch stop layer, and the gate oxide layer sequentially exposed by the first nitride layer pattern to form the first nitride layer pattern, the second oxide layer pattern, and the first First structures including an etch stop layer pattern and a gate oxide layer pattern are formed. A second trench having a predetermined depth is formed by trench etching the substrate using the first structures as an etching mask.

Thereafter, an isolation material for device isolation is applied on the second trench and the first structure to remove the insulation material existing only on the first structure through a CMP process, thereby forming an isolation layer existing only inside the second trench. do.

Subsequently, an LAL etching process is performed to form the device isolation film to a predetermined thickness to form a device isolation film pattern having a predetermined thickness. A portion of the first nitride layer pattern and the etch stop layer pattern exposed by the device isolation layer pattern is removed using the device isolation layer pattern as an etching mask.

Therefore, since the device isolation layer pattern exposed on the substrate includes another portion of the etch stop layer pattern, the void and stringer problems occurring when the poly film pattern of the gate electrode is subsequently formed do not occur. You can get it.

Hereinafter, a method of forming a gate electrode of a nonvolatile memory cell to which the method of forming an isolation layer pattern according to the present invention is applied will be described with reference to one embodiment.

3A to 3J are flowcharts illustrating a method of forming a gate electrode structure of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3A, first, a gate oxide film 104, an etch stop film 108, and a first oxide film 112 are sequentially formed on a semiconductor substrate 100.

The gate oxide film 104 formed on the substrate 100 has a silicon oxide film having a thickness of 40 to 100 Å, and the etch stop film 104 formed on the gate oxide film 102 has a low pressure chemical vapor deposition of silicon nitride. (LPCVD) is formed to a thickness of about 100 ~ 500Å, the first oxide film is a thermal oxidation or plasma-enhanced chemical vapor deposition (PE-CVD) method of oxidizing the oxide on the etch stop layer To about 1500 to 4000 mm in thickness.

Subsequently, a photoresist film (not shown) is formed by applying a photoresist on the surface of the first oxide film 112 with a uniform thickness, and then a photolithography process is performed on the photoresist film to thereby form an active region of the substrate. A first positive pattern 116 is defined. Here, the first photoresist pattern is a first etching mask pattern.

Referring to FIG. 3B, the etch stop layer 108 is formed by first dry etching the first oxide layer 112 exposed by the first photoresist pattern using the first photoresist pattern 116 as an etching mask. A first trench 120 is formed to expose the surface of the first trench 120. Here, the first oxide layer 112 is formed of first oxide layer patterns 112a having a positive slope due to the first trenches 120 formed in the first oxide layer 112.

Subsequently, the first photoresist pattern 116 positioned on the first oxide layer patterns 112a is removed by performing a plasma ashing or sulfuric acid strip process.

Referring to FIG. 3C, a first silicon nitride layer may be formed on the first oxide layer patterns 112a such that silicon nitride may be buried in the first trenches 120 formed between the first oxide layer patterns 112a. Not shown).

3A to 3I present only in the first trench 120 by removing the first silicon nitride layer existing on the first oxide layer patterns 112a through a chemical mechanical polishing process (CMP) process. A process flow chart illustrating a method of forming a gate electrode structure of a nonvolatile memory device according to an embodiment of the present invention.

3D and 3E, the first oxide layer pattern 112a, the etch stop layer 108, the gate oxide layer 104, and the substrate are sequentially formed using the first silicon nitride layer pattern 124 as an etching mask. By dry etching, a second trench 132 is formed to separate the substrate 100.

In detail, a method of forming the second trench 130 may be described. First, the first oxide pattern 112a, the etch stop layer 108, and the gate oxide layer 104 are exposed by the first silicon nitride layer pattern 124a. By sequentially dry etching, the first structures 126 including the first silicon nitride layer pattern 124a, the second oxide layer pattern 112b, the first etch stop layer pattern 108a, and the gate oxide layer pattern 104a may be formed. Is formed.

In addition, a recess 130 having a predetermined depth is formed by etching the substrate 100 exposed by the first structures 126 using the first structures 126 as an etching mask. As a result, the second trench 132 includes an opening 128 disposed between the first structures 126 and a recess 130 formed in the substrate 100.

Referring to FIGS. 3F and 3G, an insulating film (not shown) is applied to the resultant material so that the insulating material for isolation may be buried in the second trench 132 disposed between the first structures 126. . The insulating film for device isolation may include spin on glass (SOG), undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphosilicate glass (PSG), plasma enhanced tatra ethyl thosilicate (PE-TEOS), and a flowable oxide film. Any one of the group consisting of an oxide film made of (Flowable Oxide) and the like can be used.

Subsequently, a CMP process is performed on an isolation layer (not shown) existing only on the first structure 126 to form an isolation layer 136 existing only inside the second trench 132.

In addition, an LAL etching process is performed to adjust the thickness of the device isolation layer 136, thereby forming a device isolation layer pattern 136a having a predetermined thickness. At this time, a part of the second oxide pattern 112b included in the first structure is etched by the LAL etching process to form a second oxide pattern piece 112c.

Referring to FIG. 3H, the first silicon nitride layer pattern 124 exposed by the device isolation layer pattern 136a is etched using the device isolation layer pattern 136a and the second oxide layer pattern piece 112c as an etching mask. A portion of the blocking film pattern 108a is removed. As a result, one side of the device isolation layer pattern 136a exposed on the substrate may include a portion of the second oxide layer pattern 112c and a portion of the first etch stop layer pattern 108a. ), The profile of the device isolation layer pattern exposed on the substrate has a positive slough.

Referring to FIG. 3I, the polysilicon may be buried in a space (not shown) in which the first nitride layer pattern 124 included in the first structure disposed between the device isolation layer patterns 136a is removed. A first polysilicon film (not shown) is formed in the film. Thereafter, a floating gate 140 in which no void is generated is formed by partially removing the first polysilicon layer on the device isolation layer pattern 136 by performing a conventional photolithography process. The floating gates 140 thus formed are separated from each other with floating gates of neighboring cells.

Referring to FIG. 3J, a stacked gate electrode structure of a nonvolatile memory cell is formed by sequentially forming the interlayer dielectric film pattern 144 and the control gate 148 made of ONO on the floating gate 140.

Referring to the method of forming the gate electrode structure in detail, first, an interlayer dielectric film is formed on the entire surface of the resultant including the floating gate. The interlayer dielectric film is formed by depositing a first silicon oxide film having a thickness of about 20 to about 80 kPa by performing a low pressure chemical vapor deposition (LPCVD) process. Subsequently, a nitride film having a thickness of about 20 to 100 GPa is deposited on the first silicon oxide film, and a second silicon oxide film having a thickness of about 20 to 70 GPa is deposited on the nitride film to form an interlayer dielectric film made of ONO.

Subsequently, a second polysilicon film for a control gate is formed on the interlayer dielectric film. The second polysilicon layer is composed of a polysilicon layer 114 doped with N ⁺ type and a metal silicide layer such as tungsten silicide (WSix), titanium silicide (TiSix), and tantalum silicide (TaSix).

In order to form a gate electrode structure on the second conductive layer, the interlayer dielectric layer and the second polysilicon layer are sequentially etched using a hard mask pattern as an etching mask to form the floating gate 140 and the interlayer dielectric layer pattern 144. And a gate electrode structure of the nonvolatile memory cell in which the control gates 148 are sequentially stacked.

As described above, according to the present invention, the device isolation film pattern, which is a field oxide film formed by the above method, has a positive profile on the exposed part on the substrate, so that the polysilicon film is formed when the polysilicon film is buried between the device isolation film patterns. Not only voids are generated in the silicon layer pattern, but a situation in which the edge portion of the polysilicon layer pattern is embedded in the device isolation layer pattern does not occur, thereby improving electrical characteristics of the nonvolatile memory cell.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

(a) preparing a substrate in which a gate oxide film, an etch stop film, and a first oxide film are sequentially stacked; (b) forming first oxide layer patterns having a positive slope by forming a first trench in the first oxide layer to expose a surface of the etch stop layer; (c) embedding nitride in the first trenches present between the first oxide film patterns to form a first nitride film pattern; (d) forming a second trench for isolating devices sequentially stacked on the first oxide layer pattern, the etch stop layer, and the gate oxide layer using the first nitride layer pattern as an etching mask; (e) embedding an oxide material in the second trench to form an isolation pattern; removing the first nitride layer pattern and the etch stop layer pattern exposed by the device isolation layer pattern by using the device isolation layer pattern as an etching mask; And (g) depositing a polysilicon layer to bury the polysilicon between the device isolation layer patterns. The nonvolatile memory cell of claim 1, wherein the etch stop layer is formed by applying a silicon nitride layer to a thickness of 100 to 500 GPa, and the first oxide layer is formed by applying a silicon oxide layer to a thickness of 1500 to 4000 GPa. Method of forming a gate electrode. The method of claim 1, wherein the method of forming the first oxide film pattern includes: Forming a first photoresist pattern defining an active region on the substrate on which the gate oxide film, the etch stop film, and the first oxide film are sequentially stacked; Dry etching the first oxide layer corresponding to the active region of the substrate by using the first photoresist pattern as an etching mask to expose an upper surface of the etch stop layer; And Removing the first photoresist pattern; and forming a gate electrode of the nonvolatile memory cell. The method of claim 1, wherein the second trench is formed. By using the first nitride layer pattern as an etching mask, the first oxide layer pattern, the etch stop layer, and the gate oxide layer exposed by the nitride layer pattern are sequentially etched to expose the surface of the substrate and to expose the first nitride layer pattern and the second oxide layer. Forming first structures including a pattern, a first etch stop layer pattern, and a gate oxide layer pattern; And And etching the gate electrode of the nonvolatile memory cell by using the first structures as an etching mask to form a recess having a predetermined depth in the substrate exposed by the first structures. Forming method. The method of claim 4, wherein the device isolation layer pattern is formed thereon. Forming an isolation layer on the first structure while burying an oxide material in a second trench positioned between the first structures; And And forming a device isolation layer pattern between the first structures by performing a chemical mechanical polishing process on the device isolation layer existing on the first structure. The method of claim 1, wherein the first nitride layer pattern and the etch stop layer pattern are removed by a phosphate strip process.