KR100840791B1 - Method of Forming Gate electrode in non-volatile memory device - Google Patents

Abstract

A method of forming a gate electrode of a nonvolatile memory device is disclosed. A tunnel oxide film, a first conductive layer, an interlayer dielectric film, and a second conductive layer are sequentially formed on a semiconductor substrate. A mask pattern defining a gate region is formed on the second conductive layer. By first etching both sides of the upper surface of the second conductive layer that is in contact with the mask pattern, both sides of the lower surface of the mask pattern are exposed to form recesses in the second conductive layer. By using the hard mask pattern as an etch mask, the second conductive layer having the recess is etched to form a control gate pattern smaller than the line width of the mask pattern. Using the resultant as an etching mask to form a floating gate by third etching the interlayer dielectric layer and the first conductive layer. The gate electrode formed by the method may prevent damage due to the plasma ions during the etching process using plasma.

Description

Method of forming a gate electrode of a nonvolatile memory device {Method of Forming Gate electrode in non-volatile memory device}

1A and 1C are cross-sectional views illustrating a method of forming a gate electrode of a nonvolatile memory device according to a conventional method.

2A to 2E are cross-sectional views illustrating a method of forming a gate electrode of a nonvolatile memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel oxide film

104: first conductive layer 106: first oxide film

108: nitride film 110: second oxide film

112: interlayer dielectric layer 114: polysilicon layer

116 metal silicide layer 118 hard mask layer

The present invention relates to a method of forming a nonvolatile memory device, and more particularly, to a method of forming a gate electrode of a nonvolatile memory device which prevents damage of the gate electrode in an etching process of forming a gate electrode of the nonvolatile memory device. It is about.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output.

The nonvolatile memory device has an almost indefinite storage capacity, and there is an increasing demand for a flash memory capable of electrically inputting and outputting data such as electrically erasable and programmable ROM (EEPROM). Memory cells in these devices generally have a vertically stacked gate structure with floating gates formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric films and a control gate formed on or around the floating gate. In flash memory cells having this structure, data is stored by applying an appropriate voltage to the control gate and the substrate to insert or draw electrons into the floating gate. At this time, the dielectric film functions to maintain a potential on the floating gate.

1A to 1C are cross-sectional views illustrating a method of forming a nonvolatile memory gate electrode by a conventional method.

Referring to FIG. 1A, a tunnel oxide layer 12 is formed on a semiconductor substrate 10 divided into an active region and a field region. After depositing the first conductive layer 14 for the floating gate on the tunnel oxide layer 12, the first conductive layer 14 is doped with N-type impurities using a conventional doping method.

The first oxide layer 16, the nitride layer 18, and the second oxide layer 20 are sequentially deposited as the interlayer dielectric layer 22 for insulating the floating gate and the control gate on the resultant. The second conductive layer 24 and the metal silicide layer 26 for the control gate are sequentially deposited on the interlayer dielectric film 22.

Referring to FIG. 1B, after forming a hard mask layer for patterning a gate electrode on the silicide layer 26, the hard mask layer is patterned by a photolithography process to form a hard mask pattern 28.

Referring to FIG. 1C, the silicide layer 26, the second conductive layer 24, the interlayer dielectric layer 22, and the first conductive layer 14 are anisotropically etched using the hard mask pattern 28 as an etching mask. do. Then, a stacked gate structure of a nonvolatile memory cell having a floating gate formed of the first conductive layer pattern 14a and a control gate 40 formed of the second conductive layer pattern 24a and the silicide layer pattern 26a. Is formed.

Reference numerals 16a, 18a, and 20a denote first oxide film patterns, nitride film patterns, and second oxide film patterns constituting the interlayer dielectric film 22, respectively.

When the dry etching process is performed to form the gate structure, the etching ions are tilted at a predetermined angle rather than in a vertical direction to etch the etching target, thereby physically or chemically damaging sidewalls of the metal silicide layer pattern. Such damage causes a change in the structure of the metal silicide layer, which in turn causes unwanted film characteristics in the semiconductor device manufacturing process, thereby lowering the reliability and electrical characteristics of the semiconductor device.

Accordingly, an object of the present invention is to provide a method of forming a gate electrode of a nonvolatile memory device capable of preventing physical and chemical damage of a metal silicide pattern generated during a gate electrode forming process to prevent deterioration of electrical characteristics of the device.

The gate electrode forming method of the nonvolatile memory device of the present invention for achieving the above object,

(a) forming a tunnel oxide film on the semiconductor substrate;

(b) forming a first conductive layer for floating gate on the tunnel oxide film;

(c) forming an interlayer dielectric film on the first conductive layer;

(d) forming a second conductive layer for a control gate on the interlayer dielectric film;

(e) forming a mask pattern defining a gate region on the second conductive layer;

(f) exposing both sides of the upper surface of the second conductive layer to be interviewed with the mask pattern by first etching, thereby exposing both sides of the lower surface of the mask pattern to form a recess in the upper surface of the second conductive layer;

(g) forming a control gate pattern smaller than the line width of the mask pattern by second etching the second conductive layer on which the recess is formed using the hard mask pattern as an etching mask; And

(h) forming a floating gate pattern by third etching the interlayer dielectric layer and the first conductive layer using the resultant as an etching mask.

According to the present invention, when the dry etching process is performed to form the gate structure, the metal silicide layer pattern having the excellent profile is formed by preventing the damage caused by the etching ions tilted at the predetermined angle to etch the etching target. The semiconductor device reliability and electrical characteristics can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 2A, the semiconductor substrate 100 is divided into an active region and a field region through a device isolation process such as shallow trench isolation (STI). Specifically, after forming the trench by etching the semiconductor substrate 100 to a predetermined depth, an oxide film is deposited by chemical vapor deposition (CVD) to fill the trench. Next, the CVD-oxide film is etched by an etch back or chemical mechanical polishing (CMP) method to form a field oxide film only inside the trench.

In addition, the field region may be formed by a conventional local oxidation of silicon (LOCOS) process, and a self-aligned shallow trench trench that simultaneously forms a floating gate and an active region. isolation (SA-STI) process.

Subsequently, a tunnel oxide film 102 having a thickness of about 70 to about 100 GPa is formed on the semiconductor substrate 100 by a thermal oxidation process.

Next, the first conductive layer 104 for the floating gate is formed on the semiconductor substrate 100 on which the tunnel oxide film 102 is formed. The first conductive layer 104 is made of polysilicon or amorphous silicon, and is deposited to a thickness of about 900 to 1500Å. Then, the first conductive layer 104 is doped with a high concentration of N-type impurities using POCl ₃ diffusion, ion implantation, or in-situ doping method, which is a conventional doping method, and then a photolithography process is performed on the field region. The present first conductive layer 104 is selectively removed.

An interlayer dielectric film 112 formed of ONO on the first conductive layer to insulate the first conductive layer 104 for the floating gate formed on the semiconductor substrate 100 and the second conductive layer for the control gate to be formed later. To form. The interlayer dielectric film 112 may be formed by a conventional thermal oxidation process, but is preferably formed by a chemical vapor deposition process.

A specific method of forming the interlayer dielectric film 112 may be performed by performing a low pressure chemical vapor deposition (LPCVD) process on the first conductive layer 104 at a temperature of about 700 to 750 ° C. A first oxide film 106 having a thickness is deposited. Subsequently, a first annealing process is performed under NO or N ₂ O atmosphere to densify the first oxide film 106. Subsequently, after performing an LPCVD process on the first oxide film 106 to deposit a nitride film 108 having a thickness of about 20 to about 100 kHz, the LPCVD method is performed on the nitride film 108 at a temperature of about 700 to 750 ° C. A second oxide film 110 of about 20 to 70 microns thick is deposited. Subsequently, a second annealing process is performed under NO or N ₂ O atmosphere to densify the second oxide film 110. By going through the above process, an interlayer dielectric film 112 made of LPCVD-ONO is formed.

The second conductive layer 118 for the control gate is formed on the interlayer dielectric film 112. The second conductive layer 118 is composed of a polysilicon layer 114 doped with N ⁺ type and a metal silicide layer 116 such as tungsten silicide (WSix), titanium silicide (TiSix), and tantalum silicide (TaSix). have.

Referring to FIG. 2A, a hard mask layer for patterning a gate structure is then formed on the second conductive layer. The hard mask layer is formed of a single film of an oxide film or a nitride film or a composite film of an oxide film and a nitride film. The hard mask layer is etched by a photolithography process to form a hard mask pattern 118 defining a gate structure formation region.

Referring to FIG. 2C, by etching both sides of an upper surface of the metal silicide layer 116 that is in contact with the hard mask pattern 118 using the hard mask pattern 118 as an etching mask, the metal silicide layer ( Lower surfaces of both sides of the hard mask pattern 118 are exposed to form recesses in 116.                     

The recess may be formed by immersing a semiconductor substrate on which the hard mask pattern 118 is formed in an etching bath containing a chemical liquid to perform a wet etching process, thereby forming a bottom surface of the hard mask pattern 118 on the metal silicide layer 116. Form an undercut structure that exposes it.

The recesses are formed at both sides of the upper surface of the metal silicide layer 116 to be in contact with the hard mask pattern 118. The recesses may be formed to have widths wider than those of the hard mask pattern 118 in the subsequent etching process. In order to form a small metal silicide pattern more easily.

In addition, the recess may be formed to have a depth that does not cause damage to the metal silicide layer pattern in proportion to the inclination to the plasma etching ions in the subsequent etching process.

Referring to FIG. 2D, a second etching process of anisotropically etching the recessed metal silicide layer 116a and the polysilicon layer 114 using the hard mask pattern 118 as an etching mask is performed. As a result, a control gate structure including a polysilicon layer pattern 114b and a silicide layer pattern 116a having a line width smaller than that of the hard mask pattern 118 is formed.

The metal silicide layer pattern 116b formed as described above may have a hard mask pattern having a larger line width than the metal silicide layer pattern 116b during a plasma etching process of patterning the interlayer dielectric layer 112 and the first conductive layer 104. By 118, damage due to the plasma ions can be prevented.                     

If the metal silicide layer pattern 116b has the same line width as that of the hard mask pattern 118, the etching ions generated in the plasma etching process have a predetermined angle, not a vertical direction, and the interlayer dielectric layer and the Since the conductive layer is etched, damage to the metal silicide layer pattern 116b occurs.

Therefore, the metal silicide layer pattern 116b should be formed to have a line width smaller than that of the hard mask pattern 118.

In addition, a passivation process may be performed on the resultant to further form a third oxide film (not shown) on both sidewalls of the control gate structure, thereby preventing damage from the plasma ions during the subsequent plasma etching process.

After the control gate structure is formed, the curing process is further performed to heal the damaged structure in the etching process.

Referring to FIG. 2E, using the resultant as an etching mask, the interlayer dielectric layer 112 and the first conductive layer 104 are subjected to a plasma etching process to form the interlayer dielectric layer pattern 112a and the first conductive layer pattern 104a. To form a floating gate structure comprising.

The plasma etching process should be performed independently while modifying etching conditions when etching the interlayer dielectric layer or the first conductive layer.

Referring to FIG. 2F, after patterning the gate electrode structure as described above, the resultant is subjected to a dry oxidation process at a temperature of about 950 ° C. or less, for example. Then, both sides of the floating gate structure and both sides of the control gate structure are oxidized to form an oxide film 124 having a predetermined thickness.

As described above, according to the present invention, before the second conductive layer is etched using the hard mask layer pattern, a recess is formed in the first conductive layer, thereby reducing the line width smaller than that of the hard mask layer pattern. A two conductive layer pattern could be formed. Therefore, when the interlayer dielectric layer and the first conductive layer are subsequently etched, since the second conductive layer has a line width smaller than that of the mask pattern, the second conductive layer pattern due to the etching ions incident at a predetermined angle with the upper surface of the etch target. By preventing the damage of the metal silicide layer pattern having the excellent profile can be formed to improve the semiconductor device reliability and electrical properties.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (8)

(a) forming a tunnel oxide film on the semiconductor substrate; (b) forming a first conductive layer for floating gate on the tunnel oxide film; (c) forming an interlayer dielectric film on the first conductive layer; (d) forming a second conductive layer for a control gate on the interlayer dielectric film; (e) forming a mask pattern defining a gate region on the second conductive layer; (f) exposing both sides of the upper surface of the second conductive layer to be interviewed with the mask pattern by first etching, thereby exposing both sides of the lower surface of the mask pattern to form a recess in the upper surface of the second conductive layer; (g) forming a control gate pattern smaller than the line width of the mask pattern by second etching the recessed second conductive layer using the mask pattern as an etching mask; And and (h) forming a floating gate pattern by third etching the interlayer dielectric film and the first conductive layer using the resultant as an etching mask. The method of claim 1, wherein the first conductive layer is made of polysilicon or amorphous silicon. The method of claim 1, wherein the interlayer dielectric film has a structure in which a first oxide film, a nitride film, and a second oxide film are stacked. The method of claim 1, wherein the second conductive layer has a structure in which a polysilicon layer and a metal silicide layer are stacked. The method of claim 1, wherein the second etching is a plasma etching process. The method of claim 1, wherein after the step (g), a passivation process is further performed to form a third oxide film on both sidewalls of the control gate. The method of claim 1, further comprising performing a curing process after step (g) to cure damages generated during the etching process of the second conductive layer. The gate electrode of claim 1, wherein the recess of the second conductive layer is formed to have a depth at which the control gate is not damaged by plasma ions during the third etching process. Forming method.

Images