KR20030050194A - Method of forming a gate in a flash memory - Google Patents
Method of forming a gate in a flash memory Download PDFInfo
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- KR20030050194A KR20030050194A KR1020010080594A KR20010080594A KR20030050194A KR 20030050194 A KR20030050194 A KR 20030050194A KR 1020010080594 A KR1020010080594 A KR 1020010080594A KR 20010080594 A KR20010080594 A KR 20010080594A KR 20030050194 A KR20030050194 A KR 20030050194A
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- polysilicon layer
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 229920005591 polysilicon Polymers 0.000 claims abstract description 42
- 229920000642 polymer Polymers 0.000 claims abstract description 28
- 239000007769 metal material Substances 0.000 claims abstract description 25
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 239000006227 byproduct Substances 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 93
- 238000005530 etching Methods 0.000 claims description 34
- 229910019001 CoSi Inorganic materials 0.000 claims description 3
- 229910008484 TiSi Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 플래쉬 메모리의 게이트 형성 방법에 관한 것으로, 특히 자기정렬 식각으로 플로팅 게이트를 형성할 때, 폴리실리콘층과 금속계 물질층이 적층된 컨트롤 게이트에 노치(notch)가 발생되는 것을 방지하여 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있는 플래쉬 메모리의 게이트 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate of a flash memory. In particular, when a floating gate is formed by self-aligned etching, a notch is prevented from occurring in a control gate in which a polysilicon layer and a metal material layer are stacked. The present invention relates to a method of forming a gate of a flash memory capable of improving reliability and electrical characteristics.
일반적으로, 플래쉬 메모리는 정보를 저장하는 플로팅 게이트와 워드라인 역할을 하는 컨트롤 게이트로 구성된다. 최근 반도체 소자의 고집적화로 컨트롤 게이트의 선폭이 줄어듦에 따라 워드라인의 저항이 증가되고 있다. 워드라인의 저항을 감소시키기 위하여, 컨트롤 게이트를 폴리실리콘만으로 형성하지 않고 전도성이 우수한 금속계 물질을 폴리실리콘과 함께 사용하고 있다. 즉, 컨트롤 게이트를 폴리실리콘층과 금속계 물질층이 적층된 구조로 만들고 있다.In general, a flash memory includes a floating gate for storing information and a control gate serving as a word line. Recently, as the line width of the control gate is reduced due to the high integration of semiconductor devices, the resistance of the word line is increasing. In order to reduce the resistance of the word line, a metal-based material having excellent conductivity is used together with polysilicon instead of forming the control gate using only polysilicon. That is, the control gate is made of a structure in which a polysilicon layer and a metal material layer are stacked.
도 1a 내지 도 1d는 종래 플래쉬 메모리의 게이트 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for explaining a gate forming method of a conventional flash memory.
도 1a를 참조하면, 반도체 기판(11) 상에 터널 산화막(12) 및 제 1 폴리실리콘층(13)을 순차적으로 형성한다. 플로팅 게이트 마스크를 사용한 식각 공정으로 제 1 폴리실리콘층(13)을 패터닝하여 플로팅 게이트의 일부를 정의(define)한다. 패터닝된 제 1 폴리실리콘층(13) 상에 유전체막(14)을 형성한다. 유전체막(14) 상에 제 2 폴리실리콘층(15) 및 금속계 물질층(16)을 순차적으로 형성한다. 금속계 물질층(16) 상에 하드 마스크층(hard mask layer; 17)을 형성한다.Referring to FIG. 1A, the tunnel oxide film 12 and the first polysilicon layer 13 are sequentially formed on the semiconductor substrate 11. The first polysilicon layer 13 is patterned by an etching process using a floating gate mask to define a portion of the floating gate. The dielectric film 14 is formed on the patterned first polysilicon layer 13. The second polysilicon layer 15 and the metal material layer 16 are sequentially formed on the dielectric film 14. A hard mask layer 17 is formed on the metal material layer 16.
상기에서, 유전체막(14)은 ONO(oxide-nitride-oxide) 구조나 기타 유전체 물질로 형성한다. 금속계 물질층(16)은 WSix, W, CoSiX, TiSiX등으로 형성한다.In the above, the dielectric film 14 is formed of an oxide-nitride-oxide (ONO) structure or other dielectric material. The metal-based material layer 16 is formed of WSi x , W, CoSi X , TiSi X, or the like.
도 1b를 참조하면, 컨트롤 게이트 마스크 작업을 통해 워드라인 영역이 클로즈(close)된 포토레지스트 패턴(18)을 하드 마스크층(17) 상에 형성한다. 포토레지스트 패턴(18)을 식각 마스크로 사용한 건식 식각 공정으로 하드 마스크층(17), 금속계 물질층(16) 및 제 2 폴리실리콘층(15)을 순차적으로 식각 하여, 제 2 폴리실리콘층(15) 및 금속계 물질층(16)이 적층된 컨트롤 게이트(156)가 형성된다.Referring to FIG. 1B, the photoresist pattern 18 having the word line region closed is formed on the hard mask layer 17 through a control gate mask operation. In the dry etching process using the photoresist pattern 18 as an etching mask, the hard mask layer 17, the metal material layer 16, and the second polysilicon layer 15 are sequentially etched to form a second polysilicon layer 15. ) And a control gate 156 in which the metal material layer 16 is stacked.
상기에서, 건식 식각 공정 동안 폴리머가 발생되며, 발생된 폴리머는 컨트롤 게이트(156)의 측벽에 달라붙어 폴리머층(19)을 형성하게 된다.In the above, a polymer is generated during the dry etching process, and the polymer is attached to the sidewall of the control gate 156 to form the polymer layer 19.
도 1c를 참조하면, 폴리머층(19)은 후속의 증착 공정에서 결함(defect)을 유발시키거나 전기적으로 연결이 되어야 할 부분을 절연시키기 때문에, 포토레지스트 패턴(18)을 제거한 후 세정 공정을 통해 제거한다.Referring to FIG. 1C, since the polymer layer 19 insulates a portion to be defective or electrically connected in a subsequent deposition process, the photoresist pattern 18 is removed and then cleaned. Remove
상기에서, 폴리머층(19)을 제거하기 위한 세정 공정은 HF 계열의 습식 세정제(wet cleaning chemical)를 사용한다.In the above, the cleaning process for removing the polymer layer 19 uses an HF-based wet cleaning chemical.
도 1d를 참조하면, 셀 지역이 오픈(open)된 포토레지스트 패턴(도시 안됨)을 형성한 후, 셀 지역의 하드 마스크층(17)을 식각 장벽층(etch barrier)으로 한 자기정렬 식각 공정으로 유전체막(14)의 노출된 부분 및 패터닝된 제 1 폴리실리콘층(13)의 노출된 부분을 식각 하여 플로팅 게이트(130)를 형성한다.Referring to FIG. 1D, after forming a photoresist pattern (not shown) in which a cell region is opened, a self-aligned etching process using the hard mask layer 17 of the cell region as an etch barrier is performed. The exposed portion of the dielectric film 14 and the exposed portion of the patterned first polysilicon layer 13 are etched to form the floating gate 130.
상기에서, 자기정렬 식각 공정으로 플로팅 게이트(130)를 형성할 때, 제 2폴리실리콘층(15)과 금속계 물질층(16)이 적층된 컨트롤 게이트(156)는 자기정렬 식각 공정에 측면이 노출된 상태이고, 이로 인하여 식각 침범(etch attack)을 당하게 된다. 식각 침범은 제 2 폴리실리콘층(15)과 금속계 물질층(16)의 계면에 많이 발생되어, 도 1d에 도시된 바와 같이, 노치(notch; N)가 생기게 된다.In the above, when the floating gate 130 is formed by the self-aligned etching process, the control gate 156 in which the second polysilicon layer 15 and the metal-based material layer 16 are stacked is exposed to the self-aligned etching process. It is in an etched state, which causes an etch attack. Etch violations are frequently generated at the interface between the second polysilicon layer 15 and the metal-based material layer 16, resulting in notches N, as shown in FIG. 1D.
따라서, 본 발명은 자기정렬 식각으로 플로팅 게이트를 형성할 때, 폴리실리콘층과 금속계 물질층이 적층된 컨트롤 게이트에 노치가 발생되는 것을 방지하여 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있는 플래쉬 메모리의 게이트 형성 방법을 제공함에 그 목적이 있다.Therefore, when the floating gate is formed by self-aligned etching, the present invention provides a flash memory that can improve the reliability and electrical characteristics of the device by preventing notches from occurring in the control gate in which the polysilicon layer and the metal material layer are stacked. Its purpose is to provide a gate forming method.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 플래쉬 메모리의 게이트 형성 방법은 반도체 기판 상에 터널 산화막 및 제 1 폴리실리콘층을 순차적으로 형성한 후, 상기 제 1 폴리실리콘층의 일부를 패터닝하는 단계; 상기 패터닝된 제 1 폴리실리콘층 상에 유전체막, 제 2 폴리실리콘층, 금속계 물질층 및 하드 마스크층을 순차적으로 형성하는 단계; 포토레지스트 패턴을 식각 마스크로 사용한 식각 공정으로 상기 하드 마스크층, 상기 금속계 물질층 및 상기 제 2 폴리실리콘층을 순차적으로 식각 하여 컨트롤 게이트를 형성하고, 상기 컨트롤 게이트의 측벽에 폴리머층이 형성되는 단계; 상기 포토레지스트 패턴을 제거한 후, 상기 폴리머층을 제외한 식각 부산물을 제 1 세정 공정으로 제거하는 단계; 상기 하드 마스크층을 식각 장벽층으로 한 자기정렬 식각 공정으로 상기 패터닝된 제 1 폴리실리콘층의 노출된 부분을 식각 하여 플로팅 게이트를 형성하고, 상기 폴리머층은 상기 컨트롤 게이트의 식각 보호층으로 작용하는 단계; 및 상기 자기정렬 식각 공정 동안에 발생되는 식각 부산물 및 상기 폴리머층을 제 2 세정 공정으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of forming a gate of a flash memory according to an embodiment of the present invention for achieving the above object, by sequentially forming a tunnel oxide film and a first polysilicon layer on a semiconductor substrate, patterning a portion of the first polysilicon layer step; Sequentially forming a dielectric film, a second polysilicon layer, a metal material layer, and a hard mask layer on the patterned first polysilicon layer; Forming a control gate by sequentially etching the hard mask layer, the metal material layer, and the second polysilicon layer in an etching process using a photoresist pattern as an etching mask, and forming a polymer layer on sidewalls of the control gate ; Removing the photoresist pattern, and then removing the etching by-products except the polymer layer by a first cleaning process; Forming a floating gate by etching the exposed portion of the patterned first polysilicon layer by a self-aligned etching process using the hard mask layer as an etching barrier layer, wherein the polymer layer serves as an etch protective layer of the control gate. step; And removing the etching by-products generated during the self-aligned etching process and the polymer layer by a second cleaning process.
도 1a 내지 도 1d는 종래 플래쉬 메모리의 게이트 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of devices for explaining a gate forming method of a conventional flash memory.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 플래쉬 메모리의 게이트 형성 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of devices for explaining a gate forming method of a flash memory according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 반도체 기판12, 22: 터널 산화막11, 21: semiconductor substrate 12, 22: tunnel oxide film
13, 23: 제 1 폴리실리콘층14, 24: 유전체막13, 23: first polysilicon layer 14, 24: dielectric film
15, 25: 제 2 폴리실리콘층16, 26: 금속계 물질층15, 25: second polysilicon layer 16, 26: metal-based material layer
17, 27: 하드 마스크층18, 28: 포토레지스트 패턴17, 27: hard mask layer 18, 28: photoresist pattern
19, 29: 폴리머층130, 230: 플로팅 게이트19, 29: polymer layer 130, 230: floating gate
156, 256: 컨트롤 게이트156, 256: control gate
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 플래쉬 메모리의 게이트 형성 방법을 설명하기 위한 소자의 단면도이다.2A through 2E are cross-sectional views of devices for explaining a gate forming method of a flash memory according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(21) 상에 터널 산화막(22) 및 제 1 폴리실리콘층(23)을 순차적으로 형성한다. 플로팅 게이트 마스크를 사용한 식각 공정으로 제 1 폴리실리콘층(23)을 패터닝하여 플로팅 게이트의 일부를 정의(define)한다. 패터닝된 제 1 폴리실리콘층(23) 상에 유전체막(24)을 형성한다. 유전체막(24) 상에 제 2 폴리실리콘층(25) 및 금속계 물질층(26)을 순차적으로 형성한다. 금속계 물질층(26) 상에 하드 마스크층(hard mask layer; 27)을 형성한다.Referring to FIG. 2A, the tunnel oxide film 22 and the first polysilicon layer 23 are sequentially formed on the semiconductor substrate 21. The first polysilicon layer 23 is patterned by an etching process using a floating gate mask to define a portion of the floating gate. The dielectric film 24 is formed on the patterned first polysilicon layer 23. The second polysilicon layer 25 and the metal material layer 26 are sequentially formed on the dielectric film 24. A hard mask layer 27 is formed on the metal material layer 26.
상기에서, 유전체막(24)은 ONO(oxide-nitride-oxide) 구조나 기타 유전체 물질로 형성한다. 금속계 물질층(26)은 WSix, W, CoSiX, TiSiX등으로 형성한다.In the above, the dielectric film 24 is formed of an oxide-nitride-oxide (ONO) structure or other dielectric material. The metallic material layer 26 is formed of WSi x , W, CoSi X , TiSi X, or the like.
도 2b를 참조하면, 컨트롤 게이트 마스크 작업을 통해 워드라인 영역이 클로즈(close)된 포토레지스트 패턴(28)을 하드 마스크층(27) 상에 형성한다. 포토레지스트 패턴(28)을 식각 마스크로 사용한 건식 식각 공정으로 하드 마스크층(27), 금속계 물질층(26) 및 제 2 폴리실리콘층(25)을 순차적으로 식각 하여, 제 2 폴리실리콘층(25) 및 금속계 물질층(26)이 적층된 컨트롤 게이트(256)가 형성된다.Referring to FIG. 2B, a photoresist pattern 28 having the word line region closed is formed on the hard mask layer 27 through a control gate mask operation. In the dry etching process using the photoresist pattern 28 as an etching mask, the hard mask layer 27, the metal material layer 26, and the second polysilicon layer 25 are sequentially etched to form a second polysilicon layer 25. ) And a control gate 256 in which the metal material layer 26 is stacked.
상기에서, 건식 식각 공정 동안 폴리머가 발생되며, 발생된 폴리머는 컨트롤 게이트(256)의 측벽에 달라붙어 폴리머층(29)을 형성하게 된다.In the above, a polymer is generated during the dry etching process, and the polymer is attached to the sidewall of the control gate 256 to form the polymer layer 29.
도 2c를 참조하면, 컨트롤 게이트(256)를 형성하기 위한 건식 식각 공정시에 발생되는 식각 부산물(etch by-product)을 제거하기 위하여, 포토레지스트 패턴(28)을 제거한 후, 제 1 세정 공정을 실시하는데, 컨트롤 게이트(256)의 측벽에 형성된 폴리머층(29)만을 남겨놓기 위하여 H2SO4습식 세정제(wet cleaning chemical)를 사용한다. 본 발명에서는 H2SO4습식 세정제만을 언급하였지만, 폴리머층(29)을 남기면서 다른 부산물을 세정할 수 있는 모든 세정제를 사용할 수 있다.Referring to FIG. 2C, in order to remove etch by-products generated during the dry etching process for forming the control gate 256, after removing the photoresist pattern 28, the first cleaning process may be performed. In practice, H 2 SO 4 wet cleaning chemical is used to leave only the polymer layer 29 formed on the sidewall of the control gate 256. Although only the H 2 SO 4 wet cleaner is mentioned in the present invention, any cleaner capable of cleaning other byproducts while leaving the polymer layer 29 may be used.
도 2d를 참조하면, 셀 지역이 오픈(open)된 포토레지스트 패턴(도시 안됨)을 형성한 후, 셀 지역의 하드 마스크층(27)을 식각 장벽층(etch barrier)으로 한 자기정렬 식각 공정으로 유전체막(24)의 노출된 부분 및 패터닝된 제 1 폴리실리콘층(23)의 노출된 부분을 식각 하여 플로팅 게이트(230)를 형성한다.Referring to FIG. 2D, after forming a photoresist pattern (not shown) in which a cell region is opened, a self-aligned etching process using the hard mask layer 27 of the cell region as an etch barrier is performed. The exposed portion of the dielectric film 24 and the exposed portion of the patterned first polysilicon layer 23 are etched to form the floating gate 230.
상기에서, 자기정렬 식각 공정으로 플로팅 게이트(230)를 형성할 때, 컨트롤 게이트(256)는 폴리머층(29)이 자기정렬 식각 공정 동안 식각 보호층(etch passivation layer)으로 작용하기 때문에 식각 침범(etch attack)을 당하지 않게되어 컨트롤 게이트(256)에 노치(notch)가 생기지 않게 된다.In the above, when the floating gate 230 is formed by the self-aligned etching process, the control gate 256 is etched because the polymer layer 29 acts as an etch passivation layer during the self-aligned etching process. It is not subjected to an etch attack so that notches are not generated in the control gate 256.
도 2e를 참조하면, 폴리머층(29)은 후속의 증착 공정에서 결함(defect)을 유발시키거나 전기적으로 연결이 되어야 할 부분을 절연시키기 때문에 반듯이 제거되어야 한다. 플로팅 게이트(230)를 형성하기 위한 자기정렬 식각 공정 동안에 발생되는 식각 부산물(etch by-product)을 제거하기 위하여 제 2 세정 공정을 실시하는데, 컨트롤 게이트(256)의 측벽에 형성된 폴리머층(29)도 함께 제거하기 위하여 HF 계열의 습식 세정제(wet cleaning chemical)를 사용한다.Referring to FIG. 2E, the polymer layer 29 must be removed because it will cause defects or insulate the portions to be electrically connected in subsequent deposition processes. A second cleaning process is performed to remove etch by-products generated during the self-aligned etching process for forming the floating gate 230, wherein the polymer layer 29 formed on the sidewall of the control gate 256 is formed. In addition, a wet cleaning chemical of HF series is used to remove the same.
상술한 바와 같이, 본 발명은 플로팅 게이트를 형성하기 위한 자기정렬 식각 공정에서 발생할 수 있는 컨트롤 게이트의 식각 침범을 컨트롤 게이트를 형성하기 위한 건식 식각 공정시에 형성되는 폴리머층을 식각 보호층으로 이용하여 방지하므로써, 컨트롤 게이트에 노치가 발생되지 않아 소자의 신뢰성 및 전기적 특성을 향상시킬 수 있고, 단순히 기존에 사용하는 습식 세정제만 변경하기 때문에 공정 변경이 간소하며, 플로팅 게이트의 표면적이 폴리머층이 차지하는 면적만큼 더 늘어나기 때문에 셀의 유효 채널 길이 마진(effective channel length margin)을 더욱 더 확보할 수 있다.As described above, the present invention uses the polymer layer formed during the dry etching process for forming the control gate as an etching protection layer by using the etching of the control gate that may occur in the self-aligned etching process for forming the floating gate. This prevents notches in the control gate, improving the reliability and electrical properties of the device, and by simply changing the conventional wet cleaner, the process change is simple, and the surface area of the floating gate occupies the area of the polymer layer. As a result, the effective channel length margin of the cell can be further increased.
Claims (4)
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| KR1020010080594A KR20030050194A (en) | 2001-12-18 | 2001-12-18 | Method of forming a gate in a flash memory |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100840791B1 (en) * | 2002-07-31 | 2008-06-23 | 삼성전자주식회사 | Method of Forming Gate electrode in non-volatile memory device |
| KR100932341B1 (en) * | 2006-12-27 | 2009-12-16 | 주식회사 하이닉스반도체 | How to Form a Flash Memory Device |
| KR100953021B1 (en) * | 2008-04-07 | 2010-04-14 | 주식회사 하이닉스반도체 | Manufacturing method of gate pattern for semiconductor device |
| KR100975975B1 (en) * | 2003-08-18 | 2010-08-13 | 매그나칩 반도체 유한회사 | Method for manufacturing EEPROM cell |
-
2001
- 2001-12-18 KR KR1020010080594A patent/KR20030050194A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100840791B1 (en) * | 2002-07-31 | 2008-06-23 | 삼성전자주식회사 | Method of Forming Gate electrode in non-volatile memory device |
| KR100975975B1 (en) * | 2003-08-18 | 2010-08-13 | 매그나칩 반도체 유한회사 | Method for manufacturing EEPROM cell |
| KR100932341B1 (en) * | 2006-12-27 | 2009-12-16 | 주식회사 하이닉스반도체 | How to Form a Flash Memory Device |
| KR100953021B1 (en) * | 2008-04-07 | 2010-04-14 | 주식회사 하이닉스반도체 | Manufacturing method of gate pattern for semiconductor device |
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