KR100292052B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100292052B1 KR100292052B1 KR1019980008018A KR19980008018A KR100292052B1 KR 100292052 B1 KR100292052 B1 KR 100292052B1 KR 1019980008018 A KR1019980008018 A KR 1019980008018A KR 19980008018 A KR19980008018 A KR 19980008018A KR 100292052 B1 KR100292052 B1 KR 100292052B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 230000010354 integration Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 16
- 238000005530 etching Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 반도체소자의 게이트산화막의 두께가 감소되는 추세에 따라 게이트 형성을 위한 과도식각(overetch)시 실리콘기판 표면의 피해를 최소화하도록 한 반도체장치의 모스전계효과트랜지스터(MOSFET)의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a morse of a semiconductor device, which minimizes damage to a surface of a silicon substrate during an overetch for forming a gate according to a trend of decreasing thickness of a gate oxide film of a semiconductor device. A method of manufacturing a field effect transistor (MOSFET).
반도체장치는 양호한 회로 동작 성능과 집적도를 얻기위하여 집적 회로를 구성하는 MOSFET의 크기를 감소시키기 위한 노력의 결과로 반도체장치의 제조기술이 서브미크론(submicron) 단위로 축소(scale down)되었다. 따라서, 집적 회로 의 구성 요소인 단일 MOSFET에 있어서 게이트(gate line)의 폭이 좁아지게 되었으며, 그에 따라 게이트의 선저항이 크게 증가될 뿐만 아니라 게이트산화막의 두께 또한 더욱 얇아지게 되었다.Semiconductor devices have been scaled down in submicron units as a result of efforts to reduce the size of MOSFETs constituting integrated circuits in order to obtain good circuit operation performance and integration. Therefore, the gate line width becomes narrow in a single MOSFET which is a component of an integrated circuit. As a result, the gate resistance of the gate is increased not only, but also the thickness of the gate oxide film becomes thinner.
따라서 게이트를 패터닝하기 위하여 게이트 형성용 폴리실리콘층을 식각시 식각부위의 잔류하는 폴리실리콘을 제거하기 위하여 과도식각(overetch)을 실시하게 되므로 얇아진 게이트산화막의 두께는 소자의 신뢰도에 악영향을 끼치게 된다.As a result, an overetch is performed to remove the remaining polysilicon in the etched portion of the gate forming polysilicon layer in order to pattern the gate, so that the thickness of the thin gate oxide film adversely affects the reliability of the device.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(1)인 실리콘기판(1) 표면의 소정 부분에 LOCOS (Local Oxidation of Silicon) 등의 선택산화방법에 의해 필드산화막(2)을 형성하여 소자의 활성영역과 필드영역을 한정한다. 상기에서, 소자의 활성영역과 필드영역을 한정하는 필드산화막(2)을 반도체기판(1)에 트렌치를 형성하고 산화실리콘을 채워 형성할 수도 있다.Referring to FIG. 1A, a field oxide film 2 is formed on a predetermined portion of a surface of a silicon substrate 1, which is a semiconductor substrate 1, by a selective oxidation method such as LOCOS (Local Oxidation of Silicon) to form an active region and a field of a device. Define the area. In the above, a field oxide film 2 defining an active region and a field region of the device may be formed in the semiconductor substrate 1 by filling trenches and filling silicon oxide.
그리고 반도체기판(1)의 표면을 열산화하여 게이트산화막(3)을 형성한다.The surface of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 3.
도 1b를 참조하면, 필드산화막(2) 및 게이트산화막(3)의 상에 불순물이 고농도로 도핑된 다결정실리콘층(4)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한다.Referring to FIG. 1B, a polycrystalline silicon layer 4 doped with impurities at high concentration on the field oxide film 2 and the gate oxide film 3 is deposited by chemical vapor deposition (hereinafter, referred to as CVD). do.
그 다음 다결정실리콘층(4) 표면에 포토레지스트를 도포한 후 사진공정을 실시하여 게이트가 형성될 부위만을 보호하는 포토레지스트패턴(10)을 정의한다.Next, after the photoresist is applied to the surface of the polysilicon layer 4, a photoresist is performed to define a photoresist pattern 10 that protects only a portion where the gate is to be formed.
도 1c를 참조하면, 포토레지스트패턴(10)을 식각마스크로 이용하는 식각공정을 실시하여 포토레지스트패턴으로 보호되지 아니하는 부위의 폴리실리콘층(4)을 제거하여 게이트(4)를 패터닝한다.한다. 이때의 식각은 게이트산화막(3)의 표면이 노출될 때까지 실시한다. 그러나 게이트(4) 패터닝시 게이트(4)를 제외한 부위의 폴리실리콘층이 잔류하는 것을 방지하기 위하여 과도식각을 하게된다.Referring to FIG. 1C, the gate 4 is patterned by performing an etching process using the photoresist pattern 10 as an etching mask to remove the polysilicon layer 4 in a portion not protected by the photoresist pattern. . At this time, etching is performed until the surface of the gate oxide film 3 is exposed. However, when the gate 4 is patterned, the over-etching is performed to prevent the polysilicon layer except for the gate 4 from remaining.
도 1d를 참조하면, 전술한 바와 같이 잔류한 폴리실리콘을 완전히 제거하기 위하여 과도식각을 행하므로 게이트산화막도 함께 식각되어 기판(1)의 표면에 게이트산화막(30)이 불균일하게 잔류하게 된다.Referring to FIG. 1D, the gate oxide film is also etched together so that the gate oxide film 30 is non-uniformly remaining on the surface of the substrate 1 because the transient etching is performed to completely remove the remaining polysilicon as described above.
이후 도시되지는 아니하였으나 게이트(4)를 이용한 이온주입 등의 공정을 거쳐 게이트의 측면 하단 기판내에 소스/드레인을 형성하여 모스형 전게효과트랜지스터를 형성한다.Although not shown thereafter, a source / drain is formed in the lower substrate on the side surface of the gate through ion implantation using a gate 4 to form a MOS type transistor.
그러나, 상술한 종래 기술에 따른 반도체장치의 제조방법은 폴리실리콘층을 식각하여 게이트를 형성하는 경우 게이트를 제외한 부위에 폴리실리콘의 잔류가능성을 완전히 배제하기 위한 과도식각시 트랜지스터의 활성영역이 형성될 부위의 게이트산화막이 식각되어 실리콘 기판의 실리콘 표면을 손상시키게 되는 문제점이 있다.However, in the method of manufacturing the semiconductor device according to the related art described above, when the gate is formed by etching the polysilicon layer, an active region of the transistor may be formed at the time of the transient etching to completely exclude the possibility of remaining of the polysilicon at a portion except the gate. There is a problem that the gate oxide film of the portion is etched to damage the silicon surface of the silicon substrate.
따라서, 본 발명의 목적은 반도체장치 제조공정중 트랜지스터를 제조하기 위한 게이트패터닝시 반도체의 고집적화에 따른 게이트산화막 두께의 감소에 기인한 실리콘기판 표면의 손상을 방지하는 게이트 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a gate forming method for preventing damage to the surface of a silicon substrate due to a decrease in the thickness of the gate oxide film due to the high integration of the semiconductor during gate patterning for manufacturing a transistor during a semiconductor device manufacturing process.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 제 1 도전형의 반도체기판 상에 게이트절연막을 형성하는 공정과, 게이트절연막 상에 도전층을 형성하는 공정과, 도전층의 소정부위를 제거하여 잔류한 도전층으로 이루어진 게이트를 형성하는 공정과, 기판의 전면에 산화공정을 실시하는 단계와, 게이트 측면 하단부의 상기 기판에 활성영역을 형성하는 단계로 이루어진다.A semiconductor device manufacturing method according to the present invention for achieving the above object is a step of forming a gate insulating film on a first conductive semiconductor substrate, a step of forming a conductive layer on the gate insulating film, and a predetermined portion of the conductive layer Forming a gate formed of the remaining conductive layer, performing an oxidation process on the entire surface of the substrate, and forming an active region on the substrate at the lower end of the gate side surface.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 제조공정도1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 제조공정도2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체장치의 제조공정도이다.2A through 2D are diagrams illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체기판(21)인 실리콘기판(21) 표면의 소정 부분에 LOCOS (Local Oxidation of Silicon) 등의 선택산화방법에 의해 필드산화막(22)을 형성하여 소자의 활성영역과 필드영역을 한정한다. 상기에서, 소자의 활성영역과 필드영역을 한정하는 필드산화막(22)을 반도체기판(21)에 트렌치를 형성하고 산화실리콘을 채워 형성할 수도 있다.Referring to FIG. 2A, a field oxide film 22 is formed on a predetermined portion of a surface of a silicon substrate 21, which is a semiconductor substrate 21, by a selective oxidation method such as LOCOS (Local Oxidation of Silicon) to form an active region and a field of a device. Define the area. In the above description, the field oxide film 22 defining the active region and the field region of the device may be formed in the semiconductor substrate 21 by filling trenches and filling silicon oxide.
그리고 반도체기판(21)의 표면을 열산화하여 게이트산화막(23)을 형성한다.The surface of the semiconductor substrate 21 is thermally oxidized to form a gate oxide film 23.
도 2b를 참조하면, 필드산화막(22) 및 게이트산화막(23)의 상에 불순물이 고농도로 도핑된 다결정실리콘층(24)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착한다.Referring to FIG. 2B, a polycrystalline silicon layer 24 doped with a high concentration of impurities on the field oxide film 22 and the gate oxide film 23 is deposited by chemical vapor deposition (hereinafter, referred to as CVD). do.
그 다음 다결정실리콘층(24) 표면에 포토레지스트를 도포한 후 사진공정을 실시하여 게이트가 형성될 부위만을 보호하는 포토레지스트패턴(20)을 정의한다.Next, a photoresist is applied to the surface of the polysilicon layer 24 and then a photolithography process is performed to define the photoresist pattern 20 that protects only the portion where the gate is to be formed.
도 2c를 참조하면, 포토레지스트패턴(20)을 식각마스크로 이용하는 식각공정을 실시하여 포토레지스트패턴으로 보호되지 아니하는 부위의 폴리실리콘층(24)을 제거하여 게이트(24)를 패터닝한다.한다. 이때의 식각은 게이트산화막(23)의 표면이 노출될 때까지 실시한다. 그러나 게이트(24) 패터닝시 게이트(24)를 제외한 부위의 폴리실리콘층이 잔류하여 잔류폴리실리콘층(240)이 게이트산화막(23)위에 일부 남는다.Referring to FIG. 2C, the gate 24 is patterned by performing an etching process using the photoresist pattern 20 as an etching mask to remove the polysilicon layer 24 in a portion not protected by the photoresist pattern. . At this time, etching is performed until the surface of the gate oxide layer 23 is exposed. However, when the gate 24 is patterned, the polysilicon layer except for the gate 24 remains, so that the remaining polysilicon layer 240 remains on the gate oxide layer 23.
따라서 본 발명에서는 이를 제거하기 위한 과도식각을 실시하지 아니하므로 실리콘기판(21) 표면은 게이트산화막(23)에 의하여 손상되지 아니한다.Therefore, the present invention does not perform the excessive etching to remove this, so the surface of the silicon substrate 21 is not damaged by the gate oxide film (23).
도 2d를 참조하면, 잔류폴리실리콘층(도 2c 에서 240)을 완전히 제거하기 위하여 종래의 과도식각방법 대신 잔류폴리실리콘층(240)에 열산화공정을 실시하여 잔류폴리실리콘층(240)이 모두 산화되게 하므로서 본래의 게이트산화막과 산화된 잔류폴리실리콘층으로 이루어진 새로운 산화막(234)을 기판의 활성영역 표면에 형성한다.Referring to FIG. 2D, in order to completely remove the residual polysilicon layer (240 in FIG. 2C), a thermal oxidation process is performed on the residual polysilicon layer 240 instead of the conventional transient etching method, so that the remaining polysilicon layer 240 is completely removed. By oxidizing, a new oxide film 234 composed of the original gate oxide film and the oxidized residual polysilicon layer is formed on the surface of the active region of the substrate.
이후 도시되지는 아니하였으나 포토레지스트패턴(20)을 제거한 다음 게이트(24)를 이용한 이온주입 등의 공정을 거쳐 게이트의 측면 하단 기판내에 소스/드레인을 형성하여 모스형 전게효과트랜지스터를 형성한다.Thereafter, although not shown, the photoresist pattern 20 is removed, followed by ion implantation using a gate 24 to form a source / drain in the lower side substrate of the gate to form a MOS type transistor.
따라서, 본 발명은 반도체장치의 트랜지스터를 제조하기 위한 게이트패터닝시 반도체의 고집적화에 따른 게이트산화막 두께의 감소에 기인한 실리콘기판 표면의 손상을 방지하는 장점을 제공한다.Accordingly, the present invention provides an advantage of preventing damage to the surface of the silicon substrate due to the reduction of the gate oxide film thickness due to the high integration of the semiconductor during gate patterning for manufacturing transistors of the semiconductor device.
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KR950025920A (en) * | 1994-02-01 | 1995-09-18 | 문정환 | Semiconductor device manufacturing method |
KR960012381B1 (en) * | 1994-11-30 | 1996-09-20 | 대우자동차 주식회사 | Canister |
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KR950025920A (en) * | 1994-02-01 | 1995-09-18 | 문정환 | Semiconductor device manufacturing method |
KR960012381B1 (en) * | 1994-11-30 | 1996-09-20 | 대우자동차 주식회사 | Canister |
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