KR20020000821A - Method of forming a gate in a semiconductor device - Google Patents
Method of forming a gate in a semiconductor device Download PDFInfo
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- KR20020000821A KR20020000821A KR1020000036057A KR20000036057A KR20020000821A KR 20020000821 A KR20020000821 A KR 20020000821A KR 1020000036057 A KR1020000036057 A KR 1020000036057A KR 20000036057 A KR20000036057 A KR 20000036057A KR 20020000821 A KR20020000821 A KR 20020000821A
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- film
- gate
- forming
- trench
- tungsten
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 19
- 239000010937 tungsten Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 14
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 abstract description 3
- 239000013043 chemical agent Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003667 anti-reflective effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Abstract
Description
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 특히 폴리실리콘막에 트렌치를 형성하고, 트렌치내에 텅스텐막 또는 텅스텐 실리사이드막을 형성한 후 게이트 패턴을 형성함으로써 텅스텐막 또는 텅스텐 실리사이드막이 산화되지 않으면서 수직한 프로파일로 게이트를 형성할 수 있는 반도체 소자의 게이트 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and in particular, a trench is formed in a polysilicon film, a tungsten film or a tungsten silicide film is formed in the trench, and a gate pattern is formed to form a gate pattern so that the tungsten film or tungsten silicide film is not oxidized. A gate forming method of a semiconductor device capable of forming a gate in one profile.
종래의 반도체 소자의 게이트 형성 방법을 도 1을 이용하여 설명하면 다음과 같다.Referring to FIG. 1, a gate forming method of a conventional semiconductor device is as follows.
반도체 기판(11) 상부에 게이트 산화막(12), 폴리실리콘막(13), 텅스텐막 또는 텅스텐 실리사이드막(14), 마스크 산화막 또는 마스크 질화막(15) 및 반사 방지막(16)을 순차적으로 형성한다. 반사 방지막(16) 상부에 감광막(도시안됨)을 형성한 후 노광 및 현상 공정을 실시하여 감광막을 패터닝한다. 패터닝된 감광막을 마스크로 반사 방지막(16)부터 게이트 산화막(12)까지 식각하여 게이트를 형성한 후 감광막 패턴을 제거한다.A gate oxide film 12, a polysilicon film 13, a tungsten film or a tungsten silicide film 14, a mask oxide film or a mask nitride film 15, and an antireflection film 16 are sequentially formed on the semiconductor substrate 11. After the photoresist film (not shown) is formed on the antireflection film 16, the photoresist film is patterned by performing exposure and development processes. The patterned photoresist is etched from the anti-reflection film 16 to the gate oxide film 12 using a mask to form a gate, and then the photoresist pattern is removed.
상기와 같은 텅스텐막 또는 텅스텐 실리사이드막을 포함하는 금속 게이트 전극은 게이트 패턴을 형성한 후 후속 열공정 과정에서 텅스텐이 쉽게 산화되어 소자에 치명적인 문제로 작용하고 있다. 특히, 텅스텐막 또는 텅스텐 실리사이드막은폴리실리콘막과의 식각 선택비가 크지 않아 텅스텐막 또는 텅스텐 실리사이드막을 식각한 후 폴리실리콘막 식각 과정에서 텅스텐막 또는 텅스텐 실리사이드막이 손상되어 수직한 게이트 프로파일을 얻기 힘들다. 이 때문에 게이트의 전기적 특성이 저하되어 소자의 동작에 치명적인 악영향을 미치게 된다.In the metal gate electrode including the tungsten film or the tungsten silicide film as described above, tungsten is easily oxidized in a subsequent thermal process after forming a gate pattern, thereby causing a fatal problem for the device. In particular, the tungsten film or the tungsten silicide film does not have a large etching selectivity with the polysilicon film, so that the tungsten film or the tungsten silicide film is damaged during the polysilicon film etching process after etching the tungsten film or the tungsten silicide film, thereby obtaining a vertical gate profile. As a result, the electrical characteristics of the gate are degraded, which has a fatal adverse effect on the operation of the device.
본 발명의 목적은 수직한 게이트 프로파일을 얻을 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.An object of the present invention is to provide a gate forming method of a semiconductor device that can obtain a vertical gate profile.
본 발명의 다른 목적은 텅스텐막 또는 텅스텐 실리사이드막의 산화를 방지할 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a gate of a semiconductor device capable of preventing oxidation of a tungsten film or a tungsten silicide film.
본 발명의 또다른 목적은 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.Another object of the present invention is to provide a method for forming a gate of a semiconductor device that can improve the electrical characteristics of the device.
도 1은 종래의 반도체 소자의 게이트 형성 방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a gate forming method of a conventional semiconductor device.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming a gate of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 및 21 : 반도체 기판 12 및 22 : 게이트 산화막11 and 21: semiconductor substrate 12 and 22: gate oxide film
13 및 23 : 폴리실리콘막 24 : 트렌치13 and 23: polysilicon film 24: trench
14 및 25 : 텅스텐막(또는 텅스텐 실리사이드막)14 and 25: tungsten film (or tungsten silicide film)
15 및 26 : 마스크 산화막(또는 마스크 질화막)15 and 26: mask oxide film (or mask nitride film)
16 및 27 : 반사 방지막 28 : 산화막16 and 27: antireflection film 28: oxide film
본 발명은 반도체 기판 상부에 게이트 산화막 및 폴리실리콘막을 형성하는 단계와, 상기 폴리실리콘막의 소정 부분을 소정 깊이로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치가 매립되도록 전체 구조 상부에 텅스텐막을 형성한 후 연마하는 단계와, 전체 구조 상부에 마스크 산화막 및 반사 방지막을 형성하는 단계와, 상기 반사 방지막, 마스크 산화막, 폴리실리콘막 및 게이트 산화막을 식각하여 게이트 패턴을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention comprises forming a gate oxide film and a polysilicon film on a semiconductor substrate, forming a trench by etching a predetermined portion of the polysilicon film to a predetermined depth, and forming a tungsten film over the entire structure to fill the trench. And then polishing, forming a mask oxide film and an anti-reflection film on the entire structure, and etching the anti-reflection film, mask oxide film, polysilicon film, and gate oxide film to form a gate pattern. do.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a gate forming method of a semiconductor device according to the present invention.
도 2(a)를 참조하면, 반도체 기판(21) 상부에 게이트 산화막(22) 및 폴리실리콘막(23)을 형성한다. 폴리실리콘막(23)의 소정 부분을 소정 깊이로 식각하여 트렌치(24)를 형성한다.Referring to FIG. 2A, a gate oxide film 22 and a polysilicon film 23 are formed on the semiconductor substrate 21. The trench 24 is formed by etching a predetermined portion of the polysilicon film 23 to a predetermined depth.
도 2(b)를 참조하면, 트렌치(24)가 매립되도록 전체 구조 상부에 텅스텐막 또는 텅스텐 실리사이드막(25)을 타겟 두께보다 두껍게 형성한다. CMP 공정으로 텅스텐막 또는 텅스텐 실리사이드막(25)을 연마하여 폴리실리콘막(23)을 노출시킨다. 이에 의해 트렌치(24)에만 텅스텐막 또는 텅스텐 실리사이드막(25)이 매립된다. 전체 구조 상부에 마스크 산화막 또는 마스크 질화막(26)을 형성한 후 반사 방지막(27)을 형성한다.Referring to FIG. 2B, a tungsten film or a tungsten silicide film 25 is formed thicker than the target thickness on the entire structure so that the trench 24 is buried. The tungsten film or tungsten silicide film 25 is polished by the CMP process to expose the polysilicon film 23. As a result, the tungsten film or the tungsten silicide film 25 is embedded only in the trench 24. After the mask oxide film or the mask nitride film 26 is formed over the entire structure, the antireflection film 27 is formed.
도 2(c)를 참조하면, 반사 방지막(27) 상부에 감광막(도시안됨)을 형성한다. 게이트 마스크를 이용한 노광 및 현상 공정으로 감광막을 패터닝한다. 패터닝된 감광막을 마스크로 반사 방지막(27), 마스크 산화막 또는 마스크 질화막(26), 폴리실리콘막(23) 및 게이트 산화막(22)을 식각하여 게이트를 형성한다. 감광막 패턴을 제거한 후 게이트를 형성하기 위한 식각 공정에 의해 손상된 반도체 기판(21) 또는 게이트 산화막(22)을 보상하기 위해 산화 공정을 실시한다. 산화 공정에 의해 폴리실리콘막(23) 측벽에 산화막(28)이 성장된다. 그러나, 텅스텐막 또는 텅스텐 실리사이드막(25)이 폴리실리콘막(23)에 형성된 트렌치(24)에 매립되어 형성되기 때문에 이들막은 산화되지 않는다.Referring to FIG. 2C, a photosensitive film (not shown) is formed on the anti-reflection film 27. The photosensitive film is patterned by an exposure and development process using a gate mask. The gate is formed by etching the anti-reflection film 27, the mask oxide film or the mask nitride film 26, the polysilicon film 23, and the gate oxide film 22 using the patterned photoresist as a mask. After removing the photoresist pattern, an oxidation process is performed to compensate for the semiconductor substrate 21 or the gate oxide film 22 damaged by the etching process for forming the gate. The oxide film 28 is grown on the sidewall of the polysilicon film 23 by the oxidation process. However, since the tungsten film or the tungsten silicide film 25 is formed by being embedded in the trench 24 formed in the polysilicon film 23, these films are not oxidized.
한편, 폴리실리콘막(23)에 트렌치(24)를 형성하기 위한 마스크는 게이트를 패터닝하기 위한 마스크에 포함되며, 그 크기보다 작아야 된다. 또한, 트렌치(24)는 패터닝된 폴리실리콘막(23)의 측벽으로부터 50∼300Å 정도 이격시켜 형성한다. 이는 후속 산화 공정에서 성장되는 산화막(28)의 두께를 고려한 것이다.On the other hand, the mask for forming the trench 24 in the polysilicon film 23 is included in the mask for patterning the gate, it should be smaller than the size. In addition, the trench 24 is formed to be spaced apart from the sidewall of the patterned polysilicon film 23 by about 50 to 300 Å. This takes into account the thickness of the oxide film 28 grown in the subsequent oxidation process.
상술한 바와 같이 본 발명에 의하면 화학제나 후속 열처리 공정의 산화 분위기에 약한 금속 물질의 노출을 방지하면서 폴리실리콘막만을 식각하여 게이트를 형성함으로써 수직 프로파일의 게이트를 형성할 수 있다. 또한, 게이트를 패터닝하기 위한 식각 공정에서 발생된 손상을 금속 게이트 물질에 영향을 주지 않으면서 보상할 수 있으므로 소자의 집적도 및 동작 특성을 향상시킬 수 있다.As described above, according to the present invention, a gate having a vertical profile may be formed by etching only a polysilicon layer to prevent the exposure of a weak metal material to an oxidizing atmosphere of a chemical agent or a subsequent heat treatment process. In addition, damage generated in the etching process for patterning the gate can be compensated without affecting the metal gate material, thereby improving the integration and operating characteristics of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000036057A KR20020000821A (en) | 2000-06-28 | 2000-06-28 | Method of forming a gate in a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000036057A KR20020000821A (en) | 2000-06-28 | 2000-06-28 | Method of forming a gate in a semiconductor device |
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| KR20020000821A true KR20020000821A (en) | 2002-01-05 |
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| KR1020000036057A KR20020000821A (en) | 2000-06-28 | 2000-06-28 | Method of forming a gate in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100680002B1 (en) * | 2005-06-25 | 2007-02-08 | 김의겸 | A dinner table |
| KR102478700B1 (en) | 2021-12-30 | 2022-12-19 | 강원대학교산학협력단 | Manufacturing Method of In-situ MgB2 Superconducting Wire Improved Critical Current Density |
-
2000
- 2000-06-28 KR KR1020000036057A patent/KR20020000821A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100680002B1 (en) * | 2005-06-25 | 2007-02-08 | 김의겸 | A dinner table |
| KR102478700B1 (en) | 2021-12-30 | 2022-12-19 | 강원대학교산학협력단 | Manufacturing Method of In-situ MgB2 Superconducting Wire Improved Critical Current Density |
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