JP2011029562A - Processing method of semiconductor-wafer end face, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remove a hump formed by rinsing treatment of an antireflection film at a wafer end face, or an etching step and a residual film caused by the hump, and to prevent minute foreign materials from scattering from the wafer end face. <P>SOLUTION: The outer peripheries of the antireflection films 121, 141 formed on a semiconductor wafer 111 are removed by rinsing treatment at the end face of the semiconductor wafer 111. Thereafter, the antireflection films 121, 141 and their underlayer structures are etched by using resist patterns 123, 143 formed on the antireflection films 121, 141. The rinsing treatment may produce the humps 122, 142 at the outermost peripheries of the antireflection films 121, 141. Before or after the etching, positions where the humps 122, 142 are formed are etched, at the wafer end face without providing masks to regions except the wafer end face. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for treating an end face of a semiconductor wafer after formation of an antireflection film, and a method for manufacturing a semiconductor device using the same.

  In the manufacturing process of a semiconductor device, a plurality of photolithography processes are generally used for forming various device patterns. In the photolithography process, a photoresist film coated on a substrate such as a semiconductor wafer is exposed through a mask (reticle) on which a desired pattern is formed, and then a development process is performed to form a resist pattern.

  In order to form the resist pattern in a desired pattern, an anti-reflection film (BARC) is formed prior to the application of the photoresist film in at least a part of the photolithography process. BARC prevents the exposure light incident on the photoresist film from being reflected by the semiconductor wafer or the film formed thereon, and thus prevents the exposure pattern from fluctuating due to interference between the incident light and the reflected light. With the recent miniaturization of semiconductor devices, short-wavelength light that is easily reflected, such as KrF or ArF excimer laser light, has been used as exposure light, and BARC has been used in an increasing number of photolithography processes. .

  In addition, with the miniaturization of semiconductor devices, even minute adhered foreign substances cannot be ignored. For this reason, it is important to suppress not only the generation of foreign matter within the effective chip area within the wafer surface but also the generation of foreign matter at the wafer end face (bevel). This is because the foreign matter generated on the wafer end surface is scattered in a later process and adheres to the effective chip area or contaminates the environment in the manufacturing apparatus, thereby reducing the yield of the semiconductor device.

  As an example, consider a process of forming a metal-oxide-semiconductor field effect transistor (MOSFET) on a silicon (Si) wafer that is element-isolated by shallow trench isolation (STI). FIG. 1 shows a typical example of this process in a cross-sectional view near the wafer end face.

  First, as shown in FIG. 1A, a resist pattern 23 that defines an STI formation portion is formed on a Si wafer 11 by photolithography. A SiN stopper film 12 and a BARC 21 are formed on the Si wafer 11. The BARC 21 is, for example, an organic film, and is removed from the wafer end surface by a rinsing process such as edge rinsing (ER) or edge back rinsing (EBR). However, it is known that such a rinsing process causes a portion 22 where the BARC is locally thickened, called a hump, at the outermost peripheral portion of the BARC 21. The thickness of the BARC 21 can be about 75 nm, for example, and the height of the hump 22 can be about twice the thickness of the BARC 21 or more.

  Next, as shown in FIG. 1B, the BARC 21, the SiN film 12 and the Si wafer 11 are etched using the resist pattern 23 as a mask to form an STI trench 24 in the Si wafer 11. At this time, the portions 21 ′ and 12 ′ of the BARC 21 and the SiN film 12 remain at the locations where the humps 22 were formed. Further, a step 24 ′ is generated on the surface of the Si wafer 11 by the film residues 21 ′ and 12 ′ acting as a mask. Next, as shown in FIG. 1C, the resist pattern 23 and the BARC 21 are removed from the entire surface of the Si wafer 11 by ashing or the like.

  Next, as shown in FIG. 1D, after the STI 25 is completed, an oxide film 31, a poly-Si film 32, and a BARC 41 are formed, and a resist pattern 43 for forming a gate electrode is formed by photolithography. The BARC 41 is subjected to a rinsing process such as EBR in the same manner as the BARC 21 and may have a hump 42 having a height of about twice or more the thickness of the BARC 41 (for example, about 75 nm) on the outermost peripheral portion. Next, as shown in FIG. 1E, using the resist pattern 43 as a mask, the BARC 41, the poly-Si film 32, and the oxide film 31 are etched by anisotropic etching to form the gate electrode 32 and the gate oxide film 31. To do. Poly Si residues 32 ′ and oxide film residues 31 ′ are generated at the locations where the humps 42 existed and at the step portions 24 ′ of the Si wafer 11.

  Next, as shown in FIG. 1F, the resist pattern 43 and the BARC 41 are removed from the entire surface of the Si wafer 11 by ashing or the like. Then, as shown in FIG. 1G, ion implantation of the source / drain 51 of the MOSFET is performed. Although this step involves application and peeling of the photoresist, the poly Si residue 32 ′ and the oxide film residue 31 ′ may be peeled off and scattered by a resist peeling process such as ashing. If these residues scatter and adhere to the MOSFET in the effective chip area as foreign matter, the operation and / or reliability of the MOSFET is impaired.

  If the over etching amount of the gate etching shown in FIG. 1E is added, the etching rate is low at the wafer end surface, so that the poly Si residue 32 'on the wafer end surface is completely removed, the gate is connected to the MOSFET in the effective chip area. Causes thinning problems. Even if these residues are completely removed by batch-type wet cleaning or the like on the entire surface of the wafer, the gate of the MOSFET is still damaged. Therefore, in order to use these methods, an additional mask process for protecting the effective chip area is required.

  With regard to removing the hump due to the BARC rinsing process, which is also the cause of this problem, a method focusing on the rinsing process is known. For example, after the first rinsing step of dropping the solvent on the wafer end surface, the hump formed by the step is flattened by increasing the wafer rotation speed, and then the solvent is dropped on the wafer end surface. A method for performing the above has been proposed.

JP 2006-5344 A Japanese Patent Application Laid-Open No. 2005-311339 Japanese Patent No. 3348842

  However, the above-described method of dropping the solvent on the wafer end face after flattening the hump is not practical for large-diameter wafers. For example, in a 300 mm wafer, a resist film thickness abnormality may occur in an area of several tens of millimeters from the outer periphery of the wafer, and there may be a phenomenon that the resist edge undulates. Furthermore, the larger the aperture, the greater the restriction in terms of increasing the number of wafer rotations.

  A method of removing a hump formed by the process or an etching step or a film residue caused by the hump without requiring an additional mask process after the rinsing process of the BARC on the wafer end surface, and using the same A method for manufacturing a semiconductor device is provided.

  According to one aspect, there is provided a wafer end surface processing method including a step of removing the outer peripheral portion of the BARC formed on the semiconductor wafer on the end surface of the semiconductor wafer by rinsing. By this rinsing step, a hump can be formed on the outermost peripheral portion of the BARC. The method further includes a step of etching the BARC and its underlying structure using a resist pattern provided on the BARC, and a mask is not provided in a region other than the wafer end surface before or after the step. And etching the position where the hump is formed.

  According to another aspect, there is provided a method for manufacturing a semiconductor device in a semiconductor device formation region of a semiconductor wafer having a semiconductor device formation region and an end face by using a photolithography process. At least one photolithography step includes a step of forming a BARC film on the semiconductor wafer and a step of removing an outer peripheral portion of the BARC by rinsing processing on the end face of the semiconductor wafer. By this rinsing step, a hump can be formed on the outermost peripheral portion of the BARC. The manufacturing method further includes an etching process for etching the BARC and its underlying structure using a resist pattern provided on the BARC, and a mask is provided in the semiconductor device formation region at the wafer end face before or after the process. And a step of etching the position where the hump is formed.

  The humps formed by the BARC rinsing process, or the etching steps and film residues resulting from the humps are removed without a mask, and the scattering of minute foreign matters from the wafer end surface is suppressed.

FIG. 10 is a cross-sectional view in the vicinity of a wafer end surface illustrating a method for manufacturing a semiconductor device according to the related art. 6 is a cross-sectional view of the vicinity of the wafer end surface illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 11 is a cross-sectional view in the vicinity of a wafer end surface illustrating a method for manufacturing a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view in the vicinity of a wafer end surface illustrating a method for manufacturing a semiconductor device according to a third embodiment; FIG. It is sectional drawing which illustrates the etching apparatus (bevel etcher) which can be used for the dry etching of a wafer end surface. It is a figure which illustrates the wet etching method of a wafer end surface. It is a figure which shows an example of the etching characteristic of the etching apparatus of FIG. It is a figure which shows another example of the etching characteristic of the etching apparatus of FIG.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, various components are not necessarily drawn to the same scale. Throughout the drawings, the same or corresponding components are denoted by the same or similar reference numerals.

(First embodiment)
First, with reference to FIG. 2, a wafer end surface processing method and a semiconductor device manufacturing method according to the first embodiment will be described. FIG. 2 shows a typical example of a process for forming MOSFETs separated by STI in an effective chip area (semiconductor device formation region) of a Si wafer, in a cross-sectional view near the wafer end face (bevel) in the main process group. ing.

  First, as shown in FIG. 2A, a resist pattern 123 that defines an STI formation portion is formed on the Si wafer 111 by photolithography. A nitride film (hereinafter, SiN film) 112 and a BARC 121 are formed on the Si wafer 111. The SiN film 112 has a thickness of about 100 nm, for example, and can function as a polishing stopper at the time of planarization after embedding the STI insulating film. However, the SiN film 112 can be omitted depending on the STI process used. The photoresist film used as the resist pattern 123 can be applied to a thickness of 250 nm, for example.

  The BARC 121 is, for example, an organic film, and is removed on the wafer end surface by a rinse process such as edge rinse (ER) or edge back rinse (EBR) with a chemical solution. This is to prevent the particles from scattering and becoming a foreign substance during wafer conveyance or when the photoresist is peeled off. The thickness of the BARC 121 is determined according to the exposure wavelength or the like, and may be about 75 nm, for example. The rinsing process such as EBR is performed in an area from the outer periphery of the Si wafer 111 to about 1.0 mm, for example. By this rinsing process, a hump 122 having a height of about twice or more than the thickness of the BARC 121 can be formed on the outermost peripheral portion of the BARC 121.

  Next, as shown in FIG. 2B, the hump 122 is removed. This step is performed by bevel etching that etches only the outer peripheral portion of the Si wafer without using an additional mask.

This etching can be performed, for example, by dry etching using a plasma etching apparatus (bevel etcher) 500 as shown in FIG. The apparatus 500 includes a ceramic plate 507 including electrodes 501 and 502, a wafer stage 503, plasma blocking plates 504 and 505, and a gas inlet 506. The electrodes 501 and 502 and the wafer stage 503 are made of a metal such as Al, and the plasma shielding plates 504 and 505 are made of a ceramic such as yttria (Y ₂ O ₃ ). High frequency power is applied between the electrodes 501 and 502 and the wafer stage 503.

  The distance d1 between the upper surface of the wafer stage 503 and the lower surface of the ceramic plate 507, that is, the height of the space into which the wafer 511 to be etched is inserted can be, for example, 1 mm-2 mm. By adjusting the distance d1 and / or the distance d2 between the outer periphery of the plasma blocking plate 504 and the outer periphery of the wafer 511, the plasma 508 is prevented from wrapping around the effective chip area of the wafer 511, and the wafer end face is desired. Only the outer peripheral region can be etched.

The processing conditions for etching the BARC 121 (hence, hump 122) in the apparatus 500 are, for example, d1: 1.15 mm, O ₂ : 200 sccm, N ₂ : 150 sccm, Ar: 50 sccm, pressure: 1.9 Torr, power: It can be 500W. The hump 122 can be removed by etching the outermost peripheral portion of the BARC 121 by, for example, a thickness of 80 nm with the O ₂ plasma generated thereby.

  FIG. 7 shows the relationship between the etching rate of the BARC 121 and the wafer radius position R under the above conditions. FIG. 7 further shows etching rates of an oxide film (hereinafter referred to as SiO film), a poly-Si film, and a SiN film under the same conditions. However, these results were measured on the front surface side (semiconductor device formation side) of the wafer. Under the above conditions, the BARC can be etched at a high selection ratio with respect to SiO, poly-Si, and SiN at the wafer end surface portion of R> 147 mm of the 300 mm wafer. Accordingly, the BARC hump 122 formed by the EBR process in the region from the outer periphery of the Si wafer 111 as described above to about 1.0 mm (R = 149 mm) is not etched significantly in the underlying SiN film 112. It is possible to remove. On the other hand, the outermost peripheral portion of the effective chip area can be set to a radius position of R = 146 mm, for example, and the BARC 121 in the effective chip area and the resist pattern 123 formed thereon are not etched.

  Note that the hump removing step in FIG. 2B may be performed after the rinsing process of the BARC 121 in FIG. 2A and before the resist pattern 123 is formed. Further, in the present application, “removing the hump” is not limited to removal until the increase in the BARC film thickness due to the hump is completely eliminated, and is such that etching is performed under normal over conditions in the subsequent BARC etching process. It also includes removing to thickness.

  Next, as shown in FIG. 2C, the BARC 121, the SiN film 112, and the Si wafer 111 are etched using the resist pattern 123 as a mask to form STI trenches (trench) 124 in the Si wafer 111. The depth of the trench 124 may be about 320 nm, for example. In the present embodiment, since the hump 122 has already been removed, the BARC 121 and the SiN film 111 that are not covered with the resist pattern 123 can be substantially completely removed.

  Next, as shown in FIG. 2D, the resist pattern 123 and the BARC 121 are removed from the entire surface of the Si wafer 111 by ashing or the like. No significant step is generated on the surface of the Si wafer 111 even at the location where the hump 122 on the wafer end face exists.

  Next, as shown in FIG. 2E, after the STI 125 is completed, an SiO film 131, a poly-Si film 132, and a BARC 141 are formed, and a resist pattern 143 for forming a gate electrode is formed by photolithography.

To complete the STI 125, first, for example, the trench 124 is filled with silicon dioxide (SiO ₂₎ , and excess SiO ₂ is removed using a chemical mechanical polishing (CMP) method. At this time, the SiN film 112 functions as a stopper. The SiN film 112 is removed by the CMP or subsequent etching. Note that after completion of the STI 125, an ion implantation process such as MOSFET well implantation or channel implantation may be performed.

  The SiO film 131 will later become a gate oxide film of the MOSFET, and has a thickness of 1.2 nm, for example. The poly-Si film 132 will later become a gate electrode of the MOSFET, and has a thickness of 100 nm, for example.

  The BARC 141 is subjected to a rinsing process such as EBR in the same manner as the BARC 121, and may have a hump 142 having a height of about twice or more the thickness of the BARC 141 (for example, about 75 nm) on the outermost peripheral portion.

Next, as shown in FIG. 2F, the hump 142 is removed. This step can be performed by bevel etching of the Si wafer 111 without using an additional mask, as in the step of FIG. For example, the outermost peripheral portion of the BARC 141 is etched by a thickness of 80 nm with O ₂ plasma. As described with reference to FIG. 7, the etching conditions under which BARC can be etched with a high selection ratio with respect to SiO and poly-Si are used, and without significantly etching the underlying poly-Si film 132 and SiO film 131, Only BARC 141 may be etched.

  Note that the hump removing step of FIG. 2F may be performed after the rinsing process of the BARC 141 of FIG. 2E and before the formation of the resist pattern 143.

  Next, as shown in FIG. 2G, the BARC 141, the poly-Si film 132, and the SiO film 131 are etched by anisotropic etching using the resist pattern 143 as a mask to form a gate electrode 132 and a gate oxide film 131. . In the present embodiment, the step of the surface of the Si wafer 111 is suppressed by the removal of the hump 122, and the hump 142 is removed, so that the poly Si residue is also present at the location where the humps 122 and 142 are formed. And generation of SiO residue can be suppressed.

  Next, as shown in FIG. 2H, the resist pattern 143 and the BARC 141 are removed from the entire surface of the Si wafer 111 by ashing or the like.

  Then, as shown in FIG. 2I, ion implantation of the source / drain (or source / drain extension region also called LDD) 151 of the MOSFET is performed. Further, the formation of the side wall spacer of the gate electrode 132, the silicidation of the surfaces of the gate electrode 132 and the source / drain 151, the back-end (wiring) process, and the like are appropriately performed to complete the semiconductor device in the effective chip area.

  In this embodiment, the hump 122 of the BARC 121 and the hump 142 itself of the BARC 141 are removed prior to the etching for forming the STI and the gate, respectively. Therefore, in the etching process at the time of forming the STI and the gate, it is possible to prevent the occurrence of steps and film residues due to the humps that have been seen in the past, and to avoid the scattering of foreign matters. In addition, since the removal of the humps 122 and 142 is performed using bevel etching that etches only the wafer end face, it is possible to avoid damaging the MOSFET gates and the like in the effective chip area without requiring an additional mask process. Can do.

(Second Embodiment)
Next, a wafer end surface processing method and a semiconductor device manufacturing method according to the second embodiment will be described with reference to FIG. FIG. 3 shows a typical example of a process for forming MOSFETs separated by STI in an effective chip area (semiconductor device formation region) of a Si wafer, in a sectional view near the wafer end face (bevel) in main process groups. ing. Descriptions of matters common to the first embodiment, such as various film thicknesses and STI embedding processes, are omitted.

  First, as shown in FIG. 3A, a resist pattern 223 for defining an STI formation portion is formed on the Si wafer 211 by photolithography. A SiN film 212 and a BARC 221 are formed on the Si wafer 211. The SiN film 212 can function as a polishing stopper during planarization after embedding the STI insulating film, but can be omitted depending on the STI process used.

  The BARC 221 is removed on the wafer end surface by a rinsing process such as edge rinsing (ER) or edge back rinsing (EBR) with a chemical solution. The rinsing process such as EBR is performed in an area from the outer periphery of the Si wafer 211 to about 1.0 mm, for example. By this rinsing process, a hump 222 having a height of about twice or more than the thickness of the BARC 221 can be formed on the outermost peripheral portion of the BARC 221.

  Next, as shown in FIG. 3B, the BARC 221, the SiN film 212, and the Si wafer 211 are etched using the resist pattern 223 as a mask to form an STI trench 224 in the Si wafer 211. At this time, the portions 221 ′ and 212 ′ of the BARC 221 and the SiN film 212 may remain at the place where the hump 222 was present. Further, a step 224 ′ may be generated on the surface of the Si wafer 211 by the film residues 221 ′ and 212 ′ acting as a mask.

  Next, as shown in FIG. 3C, the resist pattern 223 and the BARC 221 (and 221 ') are removed from the entire surface of the Si wafer 211 by ashing or the like. The SiN film residue 212 ′ and the Si step 224 ′ on the surface of the Si wafer 211 remain.

  Next, as shown in FIG. 3D, the SiN film residue 212 'is removed and the Si step 224' is smoothed. This step is performed by bevel etching in which only the outer peripheral portion of the Si wafer 211 is etched without using an additional mask.

This etching can be performed by, for example, a dry process using the plasma etching apparatus (bevel etcher) 500 shown in FIG. In this case, the etching conditions in the apparatus 500 may be, for example, d1: 1.15 mm, CF ₄ : 110 sccm, N ₂ : 110 sccm, pressure: 1.9 Torr, and power: 700 W. FIG. 8 shows the relationship between the etching rate of the SiO film, the poly-Si film, the SiN film, and the photoresist (RES) film and the wafer radial position R under these conditions, and shows the wafer (a) surface (semiconductor device formation side) and (B) It shows about each of the back. Under this condition, on a 300 mm wafer, (a) R> 148 mm on the front surface and (b) R> 146 mm on the back surface, the SiO, poly-Si, SiN and photoresist are etched substantially without selectivity. Can do. Accordingly, the removal of the SiN film residue 212 ′ caused by the BARC hump 222 formed by the EBR process in the region from the outer periphery of the Si wafer 211 as described above to about 1.0 mm (R = 149 mm) and the Si step 224 ′. Can be smoothed in the same and single etching step. On the other hand, the outermost peripheral portion of the effective chip area can be set to a radius position of R = 146 mm, for example, and the SiN film 212 and the trench 224 in the effective chip area are not etched.

Moreover, the etching process only for the outer peripheral portion of the Si wafer 211 performed in FIG. 3D can be performed by a wet process. FIG. 6 schematically shows a method that can be used for such a wet etching process. FIG. 6A shows a method of wiping the chemical solution from the chemical solution nozzle 601 disposed above the wafer 611 on the end surface of the rotating wafer 611 sprayed with N ₂ . As the chemical solution, for example, sulfuric acid, nitric acid, ammonia, hydrogen peroxide, or the like can be used. 6B, the chemical solution similar to FIG. 6A is vaporized and wiped from the vaporizing nozzle 602 arranged on the side of the wafer 611 on the end surface of the rotating wafer 611 sprayed with N ₂ . The method is shown. By performing wet etching with such a configuration, without etching the effective chip area of the Si wafer 211, the Si step 224 ′, SiN film residue 212 ′ on the wafer end surface, and poly Si film residue 232 ′, which will be described later, SiO 2 The film residue 231 ′ can be removed. Such a wet process can enhance the effect of smoothing the Si step 224 'as compared to the dry process.

  Next, as shown in FIG. 3E, after completion of the STI 225, an SiO film 231, a poly-Si film 232, and a BARC 241 are formed, and a resist pattern 243 for forming a gate electrode is formed by photolithography.

  The BARC 241 is subjected to a rinsing process such as EBR in the same manner as the BARC 221 and may have a hump 242 having a height of about twice or more the thickness of the BARC 241 (for example, about 75 nm) at the outermost peripheral portion.

  Next, as shown in FIG. 3F, the BARC 241, the poly-Si film 232, and the SiO film 231 are etched by anisotropic etching using the resist pattern 243 as a mask to form a gate electrode 232 and a gate oxide film 231. . At this time, a poly Si residue 232 ′ and a SiO film residue 231 ′ may be generated at a location where the hump 242 was present. In this embodiment, since the Si step 224 'is smoothed in FIG. 3D, the generation of the residue due to the hump 222 is suppressed because of the Si step 224'.

  Next, as shown in FIG. 3G, the resist pattern 243 and the BARC 241 are removed from the entire surface of the Si wafer 211 by ashing or the like.

Next, as shown in FIG. 3H, the poly-Si film residue 232 ′ and the SiO film residue 231 ′ are removed. This step can be performed by bevel etching of the Si wafer 211 using a dry process or a wet process as in the step of FIG. 3D without using an additional mask. For example, the plasma etching apparatus 500 of FIG. 5 and the above-described CF ₄ / N ₂ mixed gas conditions can be used. Thereby, as described with reference to FIG. 8, the poly Si film residue 232 ′ and the SiO film residue 231 ′ can be removed by the same and single etching process.

  In addition, you may perform the residue removal process of FIG.3 (h) between the process of FIG.3 (f), and the process of FIG.3 (g).

  Then, as shown in FIG. 3I, ion implantation of the source / drain 251 of the MOSFET is performed. Further, the formation of the sidewall spacer of the gate electrode 232, silicidation of the surfaces of the gate electrode 232 and the source / drain 251 and the back-end (wiring) process are appropriately performed to complete the semiconductor device in the effective chip area.

  In this embodiment, film residues generated by etching for STI formation and gate formation due to the BARC 221 hump 222 and the BARC 241 hump 242 can be removed, respectively, and scattering of foreign matters can be avoided. Further, since the removal of the film residue is performed using bevel etching that etches only the wafer end face, it is possible to avoid damaging the MOSFET gate and the like in the effective chip area without requiring an additional mask process. .

(Third embodiment)
Next, with reference to FIG. 4, a wafer end surface processing method and a semiconductor device manufacturing method according to the third embodiment will be described. FIG. 4 shows a typical example of a process for forming MOSFETs separated by STI in an effective chip area (semiconductor device formation region) of a Si wafer, in a sectional view near the wafer end face (bevel) in main process groups. ing. Descriptions of matters common to the first and / or second embodiments, such as various film thicknesses and STI embedding processes, are omitted.

  FIGS. 4A to 4C are the same as FIGS. 3A to 3C except that the first digit of each component is replaced with “3”. A step 324 ′ is generated on the surface of the Si wafer 311 at a location where the hump 322 is formed by rinsing the BARC 321.

  Next, as shown in FIG. 4D, after completion of the STI 325, an SiO film 331, a poly-Si film 332, and a BARC 341 are formed, and a resist pattern 343 for forming a gate electrode is formed by photolithography. The BARC 341 is subjected to a rinsing process such as EBR in the same manner as the BARC 321 and has a BARC 41 hump 342 on the outermost periphery.

  Next, as shown in FIG. 4E, the BARC 341, the poly-Si film 332, and the SiO film 331 are etched by anisotropic etching using the resist pattern 343 as a mask to form a gate electrode 332 and a gate oxide film 331. . Poly Si residue 332 'and SiO film residue 331' may be generated at the location where the hump 342 was present and at the Si step 324 '.

  Next, as shown in FIG. 4F, the resist pattern 343 and the BARC 341 are removed from the entire surface of the Si wafer 311 by ashing or the like.

Next, as shown in FIG. 4G, the poly-Si film residue 332 ′ and the SiO film residue 331 ′ are removed. This step is performed by bevel etching that uses the dry process or wet process in the same manner as the steps shown in FIGS. 3D and 3H, and etches only the outer peripheral portion of the Si wafer 311 without using an additional mask. Can be done. For example, the plasma etching apparatus 500 of FIG. 5 and the above-described CF ₄ / N ₂ mixed gas conditions can be used. Thereby, as described with reference to FIG. 8, the poly Si film residue 332 ′ and the SiO film residue 331 ′ can be performed in the same and single etching process.

  Although FIG. 4 shows that the positions of the humps 322 and 342 are shifted in the wafer radial direction, the humps 322 and 342 may be formed at the same wafer radial position. Therefore, in the third embodiment, residues 332 ′ and 331 ′ larger than the residues 232 ′ and 231 ′ of the second embodiment can be formed, but by extending the etching time, these residues are substantially completely removed. Can be removed.

  Then, as shown in FIG. 4H, ion implantation of the source / drain 351 of the MOSFET is performed. Further, the formation of the sidewall spacer of the gate electrode 332, silicidation of the surfaces of the gate electrode 332 and the source / drain 351, the back-end (wiring) process, and the like are appropriately performed to complete the semiconductor device in the effective chip area.

  In the present embodiment, the first and second embodiments reduce the number of additional steps by using wafer end surface processing for removing humps or steps and film residues caused by the humps once for a plurality of patterning steps. The same effect can be obtained.

  Although the embodiment has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist described in the claims. For example, in the first and second embodiments, the high selectivity etching for removing the hump in the first embodiment is used in the STI formation process, and the non-selective etching in the second embodiment is used in the gate formation process. It is possible to combine them. Further, the wafer end surface processing included in these embodiments can also be used in other semiconductor device manufacturing processes such as a photolithography process and / or an etching process following the back end process.

Regarding the above description, the following additional notes are disclosed.
(Appendix 1)
A rinsing step of removing an outer peripheral portion of the antireflection film formed on the semiconductor wafer on the end surface of the semiconductor wafer by rinsing, and a rinsing step in which a hump is formed on the outermost peripheral portion of the antireflection film;
An etching process for etching the antireflection film and its underlying structure using a resist pattern provided on the antireflection film,
Before or after the etching step, a bevel etching step of etching the position where the hump is formed without providing a mask in the region of the semiconductor wafer other than the end surface at the end surface;
A wafer end face processing method.
(Appendix 2)
The bevel etching process is performed after the etching process, the etching process leaves a part of the film constituting the base structure at a position where the hump is formed, and the bevel etching process removes a part of the film. The wafer end surface processing method according to attachment 1, wherein the wafer end surface processing method is removed.
(Appendix 3)
The bevel etching step is performed after the etching step, the etching step leaves a step on the surface of the semiconductor wafer at the position of the hump, and the bevel etching step removes the step. Wafer end face processing method.
(Appendix 4)
4. The wafer end surface processing method according to appendix 2 or 3, wherein the bevel etching step can etch polysilicon, silicon nitride, and silicon oxide without selectivity.
(Appendix 5)
The wafer end surface processing method according to appendix 1, wherein the bevel etching step is performed before the etching step to remove the hump.
(Appendix 6)
The wafer end surface processing method according to any one of appendices 1 to 5, wherein the bevel etching step uses plasma etching.
(Appendix 7)
The wafer end surface processing method according to any one of appendices 2 to 4, wherein the bevel etching step uses wet etching.
(Appendix 8)
The wafer etching method according to appendix 7, wherein the plasma etching selectively etches the hump with respect to the base structure.
(Appendix 9)
A method of manufacturing a semiconductor device using a photolithography process in the semiconductor device formation region of a semiconductor wafer having a semiconductor device formation region and an end face,
At least one photolithography step,
Forming an antireflection film on the semiconductor wafer;
In the end face, a rinsing step of removing the outer peripheral portion of the antireflection film by rinsing, and a rinsing step in which a hump is formed on the outermost peripheral portion of the antireflection film;
An etching process for etching the antireflection film and its underlying structure using a resist pattern provided on the antireflection film,
Before or after the etching step, a bevel etching step of etching the position where the hump is formed on the end face without providing a mask in the semiconductor device formation region;
A method for manufacturing a semiconductor device.
(Appendix 10)
The at least one photolithography step comprises:
The method of manufacturing the semiconductor device according to appendix 9, including a photolithography step of forming a gate electrode of the semiconductor device using the resist pattern in the etching step.
(Appendix 11)
The at least one photolithography step further includes
The method of manufacturing a semiconductor device according to appendix 10, further comprising: a photolithography step of forming a groove for shallow trench isolation of the semiconductor device in the semiconductor wafer using the resist pattern in the etching step.

111, 211, 311, 511, 611 Semiconductor wafer 112, 212, 312 Stopper film (SiN film)
121, 141, 221, 241, 321 and 341 Anti-reflective coating (BARC)
122, 142, 222, 242, 322, 342 Hump 123, 143, 223, 243, 323, 343 Resist pattern 124, 224, 324 Trench 125, 225, 325 STI
131, 231 and 331 Gate oxide film (SiO film)
132, 232, 332 Gate electrode (poly-Si film)
151, 251 and 351 Source / Drain 212 ', 221', 231 ', 232', 312 ', 321', 331 ', 332' Residue 224 ', 324' Step 500 Plasma etching apparatus (bevel etcher)
501 and 502 Electrode 503 Wafer stage 504 Plasma blocking plate 505 Gas injection port 601 Chemical nozzle 602 Vaporization nozzle

Claims (5)

A rinsing step of removing an outer peripheral portion of the antireflection film formed on the semiconductor wafer on the end surface of the semiconductor wafer by rinsing, and a rinsing step in which a hump is formed on the outermost peripheral portion of the antireflection film;
An etching process for etching the antireflection film and its underlying structure using a resist pattern provided on the antireflection film,
Before or after the etching step, a bevel etching step of etching the position where the hump is formed without providing a mask in the region of the semiconductor wafer other than the end surface at the end surface;
A wafer end face processing method.   The bevel etching process is performed after the etching process, the etching process leaves a part of the film constituting the base structure at a position where the hump is formed, and the bevel etching process removes a part of the film. The wafer end surface processing method according to claim 1, wherein the wafer end surface processing method is removed.   2. The wafer end surface processing method according to claim 1, wherein the bevel etching process is performed before the etching process to remove the hump. 3.   The wafer end surface processing method according to claim 1, wherein the bevel etching step uses plasma etching. A method of manufacturing a semiconductor device using a photolithography process in the semiconductor device formation region of a semiconductor wafer having a semiconductor device formation region and an end face,
At least one photolithography step,
Forming an antireflection film on the semiconductor wafer;
In the end face, a rinsing step of removing the outer peripheral portion of the antireflection film by rinsing, and a rinsing step in which a hump is formed on the outermost peripheral portion of the antireflection film;
An etching process for etching the antireflection film and its underlying structure using a resist pattern provided on the antireflection film,
Before or after the etching step, a bevel etching step of etching the position where the hump is formed on the end face without providing a mask in the semiconductor device formation region;
A method for manufacturing a semiconductor device.