CN114843173A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114843173A
CN114843173A CN202110140939.8A CN202110140939A CN114843173A CN 114843173 A CN114843173 A CN 114843173A CN 202110140939 A CN202110140939 A CN 202110140939A CN 114843173 A CN114843173 A CN 114843173A
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China
Prior art keywords
substrate
protective layer
layer
forming
coating
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Pending
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CN202110140939.8A
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Chinese (zh)
Inventor
余桥
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110140939.8A priority Critical patent/CN114843173A/en
Publication of CN114843173A publication Critical patent/CN114843173A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area, and an anti-reflection coating is formed on the substrate; forming a protective layer covering the substrate in the central area, wherein the protective layer exposes the anti-reflection coating of the edge area; removing the anti-reflection coating exposed from the protective layer; after removing the anti-reflection coating exposed by the protective layer, the protective layer and the residual anti-reflection coating in the central area are removed. In the process of forming the anti-reflection coating on the substrate, the problem that the thickness of the anti-reflection coating in the edge region is larger than that of the anti-reflection coating in the central region easily occurs, and the difficulty of removing the anti-reflection coating in the edge region is high.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity. In the development of integrated circuits, the functional density (i.e., the number of interconnect structures per chip) generally increases, while the geometric size (i.e., the minimum component size that can be produced by the process steps) decreases, which increases the difficulty and complexity of integrated circuit fabrication.
As the feature size is continuously reduced, photolithography is an important process, the difficulty of transferring the pattern in the mask plate to the photoresist layer is continuously increased, when the pattern is defined in the photoresist layer, because the semiconductor substrate (including the metal layer and the dielectric layer) under the photoresist has a high reflection coefficient, the exposure light source is easy to reflect on the surface of the semiconductor substrate, so that the deformation or the size deviation of the photoresist pattern is caused, and the incorrect transfer of the mask plate pattern is caused.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which improves the working performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area, and an anti-reflection coating is formed on the substrate; forming a protective layer covering the substrate in the central area, wherein the protective layer exposes the anti-reflection coating of the crystal edge area; removing the anti-reflection coating exposed by the protective layer; and after removing the anti-reflection coating exposed by the protective layer, removing the protective layer and the residual anti-reflection coating in the central area.
Optionally, the step of forming a protective layer on the substrate includes: forming a protective material layer covering the substrate and the anti-reflection coating; and removing the protective material layer positioned in the crystal edge area to expose the anti-reflection coating, wherein the rest protective material layer is used as a protective layer.
Optionally, in the step of providing a substrate, a planarization layer is further formed between the anti-reflection coating and the substrate; and in the step of removing the protective layer, simultaneously removing the planarization layer.
Optionally, in the step of providing the substrate, in the step of forming a protective layer covering the substrate in the central region, the protective layer and the planarization layer are made of the same material.
Optionally, the process of forming the protective layer includes a coating process.
Optionally, a dry etching process is used to remove the anti-reflection coating exposed from the protective layer.
Optionally, the protective material layer located in the wafer edge region is removed by an edge washing process.
Optionally, the edge washing process includes an EBR process or a WEE process.
Optionally, a wet etching process is used to remove the protective layer and the residual anti-reflection coating in the central region.
Optionally, in the step of providing the substrate, a pattern opening exposing a portion of the substrate is formed in the anti-reflective coating; before forming a protective layer covering the substrate in the central region, the method further comprises: and carrying out process treatment on the substrate exposed from the pattern opening.
Optionally, the process treatment includes ion doping treatment or etching treatment.
Optionally, in the step of forming a protective layer covering the substrate in the central region, a distance from a sidewall of the protective layer to a boundary of the edge region on a side away from the central region is 0.3 mm to 1 mm.
Optionally, the material of the protective layer comprises an organic material.
Optionally, the material of the protective layer comprises SOC material.
Optionally, the material of the anti-reflection coating includes a high-silicon-content anti-reflection layer material, wherein the mass percentage of silicon in the high-silicon-content anti-reflection layer material is greater than or equal to 40%.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, a substrate is provided, the substrate comprises a central area and a crystal edge area surrounding the central area, an anti-reflection coating is formed on the substrate, a protective layer covering the substrate is formed in the central area, the anti-reflection coating of the crystal edge area is exposed by the protective layer, and the anti-reflection coating exposed by the protective layer is removed; in the process of forming the anti-reflection coating on the substrate, the problem that the thickness of the anti-reflection coating in the edge region is larger than that of the anti-reflection coating in the central region is easy to occur, and compared with the anti-reflection coating in the central region, the difficulty in removing the anti-reflection coating in the edge region is higher.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the working performance of the semiconductor structure needs to be improved is analyzed by combining with a forming method of the semiconductor structure.
Fig. 1 to 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, which includes a central region 10Z and a edge region 10J surrounding the central region 10Z, and an anti-reflective coating 30 is formed on the substrate 10.
Note that, after the back contamination prevention cleaning during the coating process is performed, the antireflection coating 30 is liable to cause a problem of abnormal deposition in the edge region 10J, and as shown by a dotted circle in fig. 1, the thickness of the antireflection coating 30 in the edge region 10J is larger than that of the antireflection coating 30 in the central region 10Z. For example, the thickness of the anti-reflection coating 30 in the edge region 10J is ten times the thickness of the anti-reflection coating 30 in the central region 10Z.
The anti-reflective coating 30 has a pattern therein, and the anti-reflective coating 30 is patterned to serve as a mask for performing a process on the substrate 10.
Referring to fig. 2, the anti-reflective coating 30 is removed.
Since the anti-reflective coating 30 is abnormally deposited in the edge region 10J, that is, the thickness of the anti-reflective coating 30 in the edge region 10J is greater than that of the anti-reflective coating 30 in the central region 10Z, it is still difficult to remove the anti-reflective coating 30 after the etching and cleaning processes are performed on the anti-reflective coating 30, as shown in fig. 2, a part of the anti-reflective coating 30 remains in the edge region 10J, which affects the operation performance of the semiconductor structure. If the etching amount is increased to remove the anti-reflective coating 30 in the edge region 10J, other film layers below the anti-reflective coating 30 are easily damaged, which also affects the operation performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area, and an anti-reflection coating is formed on the substrate; forming a protective layer covering the substrate in the central area, wherein the protective layer exposes the anti-reflection coating of the crystal edge area; removing the anti-reflection coating exposed by the protective layer; and after removing the anti-reflection coating exposed by the protective layer, removing the protective layer and the residual anti-reflection coating in the central area.
In the forming method provided by the embodiment of the invention, a substrate is provided, the substrate comprises a central area and a crystal edge area surrounding the central area, an anti-reflection coating is formed on the substrate, a protective layer covering the substrate is formed in the central area, the anti-reflection coating of the crystal edge area is exposed by the protective layer, and the anti-reflection coating exposed by the protective layer is removed; in the process of forming the anti-reflection coating on the substrate, the problem that the thickness of the anti-reflection coating in the edge region is larger than that of the anti-reflection coating in the central region is easy to occur, and compared with the anti-reflection coating in the central region, the difficulty in removing the anti-reflection coating in the edge region is higher.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3 and 4, a substrate 100 is provided, which includes a central region 100Z and a edge region 100J surrounding the central region 100Z, and an anti-reflective coating 300 is formed on the substrate 100.
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.
In this embodiment, the substrate 100 includes a substrate (not shown).
In this embodiment, the substrate is made of silicon, in other embodiments, the substrate may also be made of one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
As an example, the substrate 100 further includes a target layer (not shown) on the substrate to be processed.
As an example, the target layer is made of amorphous silicon, and then a partial region of the target layer is ion-doped, so that there is an etching selectivity between the target layer doped with ions and the target layer not doped with ions, thereby forming a target pattern in the target layer by removing the target layer doped with ions or the target layer not doped with ions.
In this embodiment, the substrate 100 includes a central region 100Z and a crystal edge region 100J surrounding the central region 100Z.
As shown in fig. 4, in a process, a process is usually performed on the substrate 100, and a pattern opening 400 exposing a portion of the substrate 100 is formed in the anti-reflective coating 300, wherein the pattern opening 400 is used for defining an area for the subsequent process on the substrate 100.
Moreover, the pattern of the pattern opening 400 is defined by a photoresist layer, and the anti-reflective coating 300 is used to reduce a reflection effect during exposure during an exposure process for patterning the photoresist layer, thereby improving the pattern transfer accuracy.
Specifically, as shown in fig. 3, an anti-reflective coating 300 is formed to cover the entire substrate 100, and as shown in fig. 4, the anti-reflective coating 300 is patterned to form a pattern opening 400 in the anti-reflective coating 300.
In this embodiment, the anti-reflective coating 300 is formed by a spin coating process.
The anti-reflective coating 300 formed by the spin coating process has a good gap filling capability, can better cover the substrate 100, and forms a relatively flat surface.
Note that, after the back contamination prevention cleaning during the coating process is performed, the anti-reflective coating 300 is liable to cause an abnormal deposition problem in the edge region 100J, and as shown by a dotted circle in fig. 3, the thickness of the anti-reflective coating 300 in the edge region 100J is larger than that of the anti-reflective coating 300 in the central region 100Z. For example, the thickness of the anti-reflective coating 300 in the edge region 100J is ten times the thickness of the anti-reflective coating 300 in the central region 100Z.
In this embodiment, the Anti-Reflective layer 300 is a Bottom Anti-Reflective Coating (BARC) layer. As an example, the material of the anti-reflective layer 300 includes a Si-ARC (silicon-containing anti-reflective coating) material.
The Si-ARC (silicon-containing anti-reflective coating) material has a good effect on reducing reflection and standing wave problems, and the silicon-containing anti-reflective coating material has a higher hardness.
Specifically, the material of the anti-reflective coating 300 includes a high silicon content anti-reflective layer material, wherein the mass percentage of silicon in the high silicon content anti-reflective layer material is greater than or equal to 40%.
In this embodiment, in the step of providing the substrate 100, a planarization layer 200 is further formed between the anti-reflective coating 300 and the substrate 100.
The planarization layer 200 is used for providing a flat surface for the formation of the anti-reflection layer 300, so as to provide a flat surface for the formation of the photoresist layer, and further improve the pattern precision of the photoresist layer, so that the shape, size and formation position of the pattern formed in the photoresist layer meet the process requirements.
Specifically, in this embodiment, the pattern opening 400 further penetrates through the planarization layer 200 and exposes the substrate 100.
In this embodiment, the material of the planarization layer 200 is a Spin On Coating (SOC) material, and specifically, the material of the planarization layer 200 includes a polymer containing one or more elements of carbon, hydrogen, oxygen, or nitrogen. The planarization layer 200 is formed by a spin coating process, so that the process cost is low; moreover, by using spin-on materials, the flatness of the top surface of the planarization layer 200 is advantageously improved.
Specifically, as shown in fig. 3, before forming the anti-reflective coating 300 covering the entire substrate 100, the planarization layer 200 covering the substrate 100 is formed, and the anti-reflective coating 300 is formed on the planarization layer 200.
Accordingly, as shown in fig. 4, after the anti-reflective coating 300 is patterned, the method further includes: and etching the planarization layer 200 by using the patterned anti-reflection coating 300 as a mask to expose the substrate 100.
In this embodiment, etching the planarization layer 200 with the patterned anti-reflective coating 300 as a mask to expose the substrate 100 further includes: the substrate 100 exposed by the pattern opening 400 is processed.
The substrate 100 exposed by the pattern opening 400 is processed to meet the process requirements.
The anti-reflective coating 300 functions as a mask during the process of processing the substrate 100.
In this embodiment, the substrate 100 further includes a target layer located on the substrate, and correspondingly, the step of performing the process on the substrate 100 exposed by the pattern opening 400 includes: the target layer exposed by the pattern opening 400 is subjected to a process.
In this embodiment, the process includes an ion doping process or an etching process.
As an example, the target layer is made of amorphous silicon, and the target layer is ion-implanted to dope boron ions into the target layer exposed by the pattern opening 400.
Specifically, the process of the ion doping treatment may be an ion implantation process.
Referring to fig. 5 to 6, a protection layer 510 is formed on the central region 100Z to cover the substrate 100, and the protection layer 510 exposes the anti-reflective coating 300 in the edge region 100J.
Since the problem that the thickness of the anti-reflective coating 300 located in the edge area 100J is greater than the thickness of the anti-reflective coating 300 located in the central area 100Z is easily generated in the process of forming the anti-reflective coating 300 on the substrate 100, and the difficulty of removing the anti-reflective coating 300 in the edge area 100J is greater than that of the anti-reflective coating 300 in the central area 100Z, in the embodiment of the present invention, the protective layer 510 is formed on the substrate 100, and the protective layer 510 covers the substrate 100, which is beneficial for protecting the substrate 100 while removing the anti-reflective coating 300 in the edge area 100J, and reducing the probability that the substrate 100 in the central area 100J is damaged, thereby being beneficial for improving the working performance of the semiconductor structure.
In particular, in this embodiment, the material of the anti-reflection layer 300 is an anti-reflection layer material with a high silicon content, and is affected by viscosity, the anti-reflection layer 300 is more likely to be deposited in the edge area 100J, and the thickness of the anti-reflection layer 300 located in the edge area 100J is more likely to be too large, so that the anti-reflection layer 300 in the edge area 100J is easily removed by the method of this embodiment.
In this embodiment, in the step of forming the protective layer 510 covering the substrate 100 in the central region 100Z, a distance d from a sidewall of the protective layer 510 to a boundary of the edge region 100J far away from the central region 100Z is 0.3 mm to 1 mm.
The distance d from the sidewall of the protective layer 510 to the boundary of the edge region 100J far from the central region 100Z cannot be too large or too small. If the distance d is too large, the probability that the protective layer 510 is exposed out of the central region 100Z is easily increased, unnecessary process waste is caused, and the probability that a film layer (e.g., the substrate 100) in the central region 100Z is damaged is increased; if the distance d is too small, it is difficult to completely expose the anti-reflective coating 300 having a thickness greater than the thickness of the central region 100Z, resulting in difficulty in removing the anti-reflective coating 300 deposited on the edge of the wafer cleanly. Therefore, in this embodiment, the distance d from the sidewall of the protection layer 510 to the boundary of the edge region 100J far from the central region 100Z is 0.3 mm to 1 mm. For example, the distance d from the sidewall of the protective layer 510 to the boundary of the edge region 100J on the side away from the central region 100Z is 0.6 mm.
In this embodiment, the protective layer 510 is formed by a coating process.
The protective layer 510 formed by the coating process has good coverage, simple process and convenient operation.
In this embodiment, the material of the protection layer 510 includes an organic material, so as to reduce damage to the substrate 100 caused by a subsequent process for removing the protection layer 510.
In this embodiment, the material of the protection layer 510 includes SOC.
The protective layer 510 formed by the SOC material is smooth, and the protective layer 510 needs to be removed subsequently, so that the SOC material is easy to remove, and damage to other film layers is reduced in the process of removing the protective layer 510.
In this embodiment, in the step of providing the substrate 100, a planarization layer 200 is further formed between the anti-reflective coating 300 and the substrate 100; in the step of forming the protective layer 510 covering the substrate 100 in the central region 100Z, the material of the protective layer 510 and the planarization layer 200 is the same.
The protective layer 510 and the planarization layer 200 need to be removed later, and the materials of the protective layer 510 and the planarization layer 200 are the same, which is beneficial to simultaneously removing the protective layer 510 and the planarization layer 200, and simplifies the process flow.
Referring to fig. 5, the step of forming a protective layer 510 on the substrate 100 includes: a protective material layer 500 is formed covering the substrate 100 and the anti-reflective coating 300.
The protective material layer 500 is formed for forming the protective layer 510 later, and the protective material layer 500 is made of the same material as the protective layer 510.
Referring to fig. 6, the protective material layer 500 (shown in fig. 5) in the edge region 100J is removed to expose the anti-reflective coating 300, and the remaining protective material layer 500 serves as a protective layer 510.
Exposing the anti-reflective coating 300 for subsequent removal of the anti-reflective coating 300 in the edge region 100J.
In this embodiment, the edge-washing process is used to remove the protective material layer 500 in the wafer edge area 100J.
The edge washing process is beneficial to directionally removing the protective material layer 500 at the edge area of the wafer, reduces the damage to the protective material layer 500 at the central area 100Z, and reduces the probability of weakening the protective effect of the subsequently formed protective layer 510 due to the damage to the protective material layer 500 at the central area 100Z.
In this embodiment, the edge cleaning process includes an EBR (edge bead removal) process or a Wafer Edge Exposure (WEE) process.
The EBR process and the WEE process may both set a removal width of the protective material layer 500, and may remove a crystal edge region having a smaller width, which is advantageous to improve process accuracy in the edge washing process. The EBR process uses chemical solvents to achieve edge washing, and the WEE process uses exposure and development to achieve edge washing.
Referring to fig. 7, the anti-reflective coating 300 exposed by the protective layer 510 is removed.
The thickness of the anti-reflective coating 300 in the edge region 100J is greater than the thickness of the anti-reflective coating 300 in the central region 100Z, and the anti-reflective coating 300 in the edge region 100J is removed first, so that the remaining anti-reflective coating 300 has a smaller thickness, and the remaining anti-reflective coating 300 is easy to remove later.
In this embodiment, a dry etching process is used to remove the anti-reflective coating 300 exposed from the protective layer 510.
The dry etching process has the characteristic of anisotropic etching, so that the damage to other film layers in the etching process is favorably reduced by selecting the dry etching process.
Referring to fig. 8, after removing the anti-reflective coating 300 (shown in fig. 7) exposed by the protective layer 510 (shown in fig. 7), the protective layer 510 and the remaining anti-reflective coating 300 in the central region 100Z are removed.
The protection layer 510 and the remaining anti-reflective coating 300 in the central region 100Z are removed to prepare for the subsequent process.
In this embodiment, a wet etching process is used to remove the protective layer 510 and the remaining anti-reflective coating 300 in the central region 100Z.
The wet etching process has an isotropic characteristic, which is beneficial to clean the protective layer 510 and the residual anti-reflective coating 300 in the central region 100Z together.
It should be noted that, the thickness of the residual anti-reflective coating 300 in the central area 100Z is small, so that the residual anti-reflective coating 300 in the central area 100Z is easily removed in the wet etching process for removing the protection layer 510.
In this embodiment, after removing the anti-reflective coating 300 exposed by the protective layer 510 (as shown in fig. 7), the method further includes: the planarization layer 200 is removed.
The planarization layer 200 is removed in preparation for a subsequent process.
In this embodiment, the planarization layer 200 is removed by a wet etching process.
The wet etching has an isotropic characteristic, which is beneficial to removing the planarization layer 200 cleanly.
It should be noted that, in the present embodiment, the material of the protection layer 510 is the same as that of the planarization layer 200, and therefore, in the step of removing the protection layer 510, the planarization layer 200 is removed at the same time.
Accordingly, the remaining anti-reflective coating 300 is located between the protection layer 510 and the planarization layer 200, so that the protection layer 510, the planarization layer 200, and the remaining anti-reflective coating 300 in the central region 100Z can be removed together, thereby simplifying the process flow.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area, and an anti-reflection coating is formed on the substrate;
forming a protective layer covering the substrate in the central area, wherein the protective layer exposes the anti-reflection coating of the crystal edge area;
removing the anti-reflection coating exposed by the protective layer;
and after removing the anti-reflection coating exposed by the protective layer, removing the protective layer and the residual anti-reflection coating in the central area.
2. The method of forming a semiconductor structure of claim 1, wherein forming a protective layer on the substrate comprises: forming a protective material layer covering the substrate and the anti-reflection coating;
and removing the protective material layer positioned in the crystal edge area to expose the anti-reflection coating, wherein the rest protective material layer is used as a protective layer.
3. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, a planarization layer is further formed between the anti-reflective coating and the substrate;
and in the step of removing the protective layer, simultaneously removing the planarization layer.
4. The method of forming a semiconductor structure according to claim 3, wherein in the step of forming a protective layer covering the substrate in the central region, the protective layer and the planarizing layer are the same material.
5. The method of claim 1, wherein the process of forming the protective layer comprises a coating process.
6. The method of claim 1, wherein the anti-reflective coating exposed by the protective layer is removed by a dry etching process.
7. The method of claim 2, wherein an edge-washing process is used to remove the protective material layer in the edge region.
8. The method of forming a semiconductor structure of claim 7, wherein the edge-washing process comprises an EBR process or a WEE process.
9. The method of claim 1, wherein the protective layer and the remaining anti-reflective coating of the central region are removed using a wet etch process.
10. The method of claim 1, wherein in the step of providing a substrate, the anti-reflective coating layer has a pattern opening formed therein that exposes a portion of the substrate;
before forming a protective layer covering the substrate in the central region, the method further comprises: and carrying out process treatment on the substrate exposed from the pattern opening.
11. The method of claim 10, wherein the process comprises an ion doping process or an etching process.
12. The method of claim 1, wherein in the step of forming the protective layer covering the substrate in the central region, a distance from a sidewall of the protective layer to a boundary of the edge region away from the central region is 0.3 mm to 1 mm.
13. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises an organic material.
14. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer comprises a SOC material.
15. The method of claim 1, wherein the anti-reflective coating material comprises a high silicon content anti-reflective layer material, wherein the high silicon content anti-reflective layer material comprises silicon in an amount greater than or equal to 40% by mass.
CN202110140939.8A 2021-02-02 2021-02-02 Method for forming semiconductor structure Pending CN114843173A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116283301A (en) * 2023-03-23 2023-06-23 长春工程学院 Silicon carbide semiconductor material and preparation process thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116283301A (en) * 2023-03-23 2023-06-23 长春工程学院 Silicon carbide semiconductor material and preparation process thereof

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