CN114530369A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114530369A
CN114530369A CN202011324630.6A CN202011324630A CN114530369A CN 114530369 A CN114530369 A CN 114530369A CN 202011324630 A CN202011324630 A CN 202011324630A CN 114530369 A CN114530369 A CN 114530369A
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layer
material layer
pattern
forming
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李强
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

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Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region surrounding the first region, and the top surface of the second region is lower than that of the first region; forming a first pattern material layer on the layer to be etched; injecting first ions into the surface of the first pattern material layer to enable the first pattern material layer positioned on the second area to fall off, and adhering at least part of the fallen first pattern material layer to the surface of the layer to be etched to form residues; and cleaning to remove the residues, so that the first graph material layer which is not firmly adhered to the surface of the second area is separated and removed before subsequent processes are carried out, the subsequent etching process is prevented from being influenced, the influence of the height difference of the layer to be etched at the edge of the wafer on the etching process in the subsequent graph definition is reduced, the graph definition accuracy is improved, and the device performance is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the continuous development of integrated circuit manufacturing technology, in order to achieve faster operation speed, larger data storage capacity and more functions, integrated circuit chips are developed towards higher device density and higher integration level.
As the integration level of semiconductor chips is continuously increased, the feature size of transistors is continuously reduced, and the challenge to the photolithography process is increased. Critical dimension control of pattern line width is becoming an important direction in semiconductor development. In order to form finer patterns and fidelity in the process, a self-aligned dual patterning technique (SADP), a self-aligned quad patterning technique (SAQP), etc. are introduced to realize a smaller sized pattern.
However, the existing lithography techniques are yet to be further improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region surrounding the first region, and the top surface of the second region is lower than that of the first region; forming a first pattern material layer on the layer to be etched; injecting first ions into the surface of the first pattern material layer to enable the first pattern material layer positioned on the second area to fall off, and adhering at least part of the fallen first pattern material layer to the surface of the layer to be etched to form residues; cleaning to remove the residues; and after cleaning and removing the residues, forming an imaging structure on the surface of the first pattern material layer.
Optionally, the imaging structure has a first opening therein, and a portion of the first graphic material layer is exposed at the bottom of the first opening; the forming method further includes: injecting second ions into the bottom of the first opening to enable the first pattern material layer exposed at the bottom of the first opening to form a modified area; and removing the modified area to enable the first pattern material layer to form a first pattern layer.
Optionally, before forming the first pattern material layer, the method further includes: and forming a second pattern material layer on the surface of the layer to be etched, wherein the second pattern material layer is positioned between the first pattern material layer and the layer to be etched.
Optionally, the material of the second pattern material layer includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Optionally, first ions are implanted into the surface of the first pattern material layer, so that the first pattern material layer located on the second region is peeled off, and the second pattern material layer located on the second region is also peeled off.
Optionally, the method further includes: and forming a side wall on the side wall of the first pattern layer.
Optionally, the method further includes: before the side wall is formed, the imaging structure is also removed; and after the side wall is formed, removing the first graphic layer.
Optionally, the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
Optionally, the method further includes: and etching the second pattern material layer by taking the side wall as a mask until the surface of the layer to be etched is exposed to form a second pattern layer.
Optionally, the imaging structure includes a first anti-reflection layer located on the surface of the first pattern layer, a second anti-reflection layer located on the surface of the first anti-reflection layer, and a photoresist layer located on the surface of the second anti-reflection layer.
Optionally, the material of the first anti-reflective layer comprises a carbon-containing polymer.
Optionally, the material of the second anti-reflection layer comprises an organic polymer.
Optionally, the material of the first pattern material layer includes silicon.
Optionally, the process of cleaning and removing the residue is a wet process.
Optionally, the cleaning solution of the wet process includes carbon dioxide-containing deionized water.
Optionally, the process parameters of the first ion implantation include: the first ions include one or more of carbon ions, nitrogen ions, and oxygen ions, the implanted ions have an energy in a range from 5keV to 20keV, and the implanted ions have a concentration in a range from 1.0E14atom/cm3 to 1.0E20atom/cm 3.
Optionally, the material of the first pattern material layer includes silicon.
Optionally, the process parameters for implanting the second ions include: the second ions include P-type ions or N-type ions and have an energy ranging from 5keV to 20 keV.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, first ions are injected into the surface of the first graph material layer, the first graph material layer generates stress and surface static electricity due to the injection of the first ions, the stress enables the first graph material layer which is not firmly adhered and is positioned on the surface of the second area to be torn and separated from the weak point of adhesion, and residues formed by the part, adhered to the layer to be etched, of the fallen first graph material layer are removed by cleaning, so that the first graph material layer which is not firmly adhered and is positioned on the surface of the second area is separated and removed before subsequent processes are carried out, the subsequent etching process is prevented from being influenced, the influence of the height difference of the layer to be etched and positioned at the edge of a wafer on the etching process in the subsequent graph definition is reduced, the accuracy of the graph definition is improved, and the performance of a device is improved.
Furthermore, first ions are injected into the surface of the first graph material layer, so that the first graph material layer positioned on the second area falls off, the second graph material layer positioned on the second area also falls off, and the second graph material layer which is positioned on the surface of the second area and is not firmly adhered is separated and removed before subsequent processes are carried out, so that the subsequent etching process is not influenced, the influence of the height difference of the layer to be etched positioned at the edge of the wafer on the etching process in the subsequent graph definition is reduced, the graph definition accuracy is improved, and the performance of the device is improved.
Further, the process parameters of the first ion implantation include: the implanted ions comprising carbonOne or more of ions, nitrogen ions and oxygen ions, the energy of the implanted ions is in the range of 5keV to 20keV, and the concentration of the implanted ions is in the range of 1.0E14atom/cm3To 1.0E20atom/cm3. The process parameters for implanting the second ions comprise: the second ions include P-type ions or N-type ions and have an energy ranging from 5keV to 20 keV. The first ion implantation process and the second ion implantation process are different in ion type, so that the second ion implantation process is prevented from being influenced, and subsequent pattern definition is not influenced.
Drawings
FIGS. 1-3 are schematic cross-sectional views illustrating a process for forming a semiconductor structure;
fig. 4 to fig. 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
As described in the background, performance of semiconductor structures formed by conventional photolithography techniques is in need of improvement. An illustrative analysis will now be described in connection with a semiconductor structure.
Fig. 1-3 are cross-sectional views illustrating a semiconductor structure formation process.
Referring to fig. 1, a layer to be etched 101 is provided, where the layer to be etched 101 includes a first region i and a second region ii; forming a pattern material layer 102 on the layer to be etched 101; forming an amorphous silicon material layer 103 on the pattern material layer 102; a patterned photoresist layer 104 is formed on the surface of the amorphous silicon material layer 103, an opening 105 is formed in the photoresist layer 104, and the bottom of the opening 105 exposes a part of the amorphous silicon material layer 103 on the first region i and the amorphous silicon material layer 103 on the second region ii.
Referring to fig. 2, ions are implanted into the bottom of the opening 105, so that the amorphous silicon material layer 103 exposed by the opening 105 forms a modified region 106, and the amorphous silicon material layer 103 under the photoresist layer 104 forms a pattern layer 107.
The method is used in the pattern definition process, a bottom anti-reflection coating is used in an etching process before the pattern definition process, the bottom anti-reflection coating is made of a fluid organic polymer and is usually formed in a spin coating mode, the second area II is located at the edge of the wafer, liquid is easy to gather at the edge of the wafer under the action of centrifugal force, the bottom anti-reflection coating at the edge of the wafer is not easy to remove due to thick thickness, the residual bottom anti-reflection coating can cause poor adhesion between a film formed by subsequent deposition and a film of a lower layer, the film formed by subsequent deposition is separated, and therefore the height of the top surface of the second area II is lower than that of the top surface of the first area I.
In the process of implanting ions into the bottom of the opening 105, due to the relatively large stress generated by the ion implantation and the height difference between the first zone i and the second zone ii, the amorphous silicon material layer 103 and the pattern material layer 102 on the second zone ii may be torn, for example, a crack a is formed at the adhesion weak point, and the amorphous silicon material layer 103 and the pattern material layer 102 on the second zone ii may be partially peeled off. The residue B formed by the peeled off material adheres to the wafer surface with a large amount of static electricity (as shown in fig. 3), and when the residue B covers the opening 105, the residue B blocks ion implantation into the amorphous silicon material layer 103 (as shown in fig. 1) exposed by the opening 105, so that the amorphous silicon material layer 103 at the region C (the region marked by the dotted line in fig. 3) cannot form the modified region required by the target. Whether ions are implanted into the amorphous silicon material layer 103 or not can cause different etching rates, the modified region 106 is removed subsequently, and a side wall is formed on the side wall of the pattern layer 107, wherein the side wall is used for subsequent pattern definition. Since the modified region required by the target cannot be formed in the region C, the sidewall at the corresponding position is lost, and the sidewall with the uniform surface of the pattern material layer 102 cannot be formed, so that the sidewall cannot be used for accurately defining the pattern in the subsequent step. When the side wall is used as a mask pattern for forming the metal interconnection line, the position of the metal interconnection line cannot be accurately defined, bridging between the metal interconnection lines may be caused, electric leakage is generated, and the yield of the device is affected.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, wherein first ions are implanted into a surface of the first patterned material layer, since the first ion implantation causes the first pattern material layer to generate stress and surface static electricity, the stress enables the first graph material layer which is positioned on the surface of the second area and is not firmly adhered to the second area to be torn and separated from the weak adhesion point, residues formed by the part, adhered to the layer to be etched, of the first graph material layer which is peeled off are removed through cleaning, the first graph material layer which is positioned on the surface of the second area and is not firmly adhered to the second area is separated and removed before subsequent processes are carried out, the subsequent etching process is not influenced, the influence of the height difference of the layer to be etched, positioned on the edge of the wafer, on the etching process in the subsequent graph definition is reduced, the graph definition accuracy is improved, and therefore the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4 and 5, fig. 5 is a top view, fig. 4 is a cross-sectional view of the region a of fig. 5 along the XY direction, and a layer to be etched 201 is provided, where the layer to be etched 201 includes a first region i and a second region ii surrounding the first region i, and a top surface of the second region ii is lower than a top surface of the first region i.
The material of the etching layer 201 may be any material that needs to be etched, such as a dielectric material, a metal material, a semiconductor material, and the like. The etch layer 201 may be a single layer or a multi-layer stack structure. The layer 201 to be etched is located on a base (not shown), which is a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, a gallium arsenide substrate, or a germanium-on-insulator substrate. In one embodiment, the substrate has metal interconnection structures and the like therein. In this embodiment, the layer to be etched 201 is made of a metal material, and the substrate is a silicon wafer with a transistor device.
In this embodiment, the substrate has a device structure therein, and before the layer to be etched 201 is formed, a bottom anti-reflective coating is formed on the surface of the substrate through a photolithography process existing in the process of forming the device structure, the bottom anti-reflective coating is made of a fluid organic polymer, and the process of forming the bottom anti-reflective coating on the surface of the substrate is typically a spin coating process. In the process of forming the bottom anti-reflection coating, the second area II is located at the edge of the wafer, and liquid is easy to gather at the edge of the wafer under the action of centrifugal force, so that the bottom anti-reflection coating material on the second area II is difficult to remove after the photoetching process due to thick thickness. After the photolithography process and before the layer to be etched 201 is formed, when a film is formed on the surface of the substrate, the adhesion between the film and the substrate is poor due to the unremovable bottom anti-reflective coating material, which causes the film on the second region ii to be separated from the surface of the substrate, so that after the layer to be etched 201 is formed, the height of the top surface of the second region ii is lower than that of the top surface of the first region i.
It should be noted that the subsequent views in fig. 6 to 15 are all the same as the views in fig. 4.
Referring to fig. 6, a first pattern material layer 202 is formed on the layer to be etched 201.
In this embodiment, before the first pattern material layer 202 is formed, a second pattern material layer 203 is further formed on the surface of the layer to be etched 201, and the second pattern material layer 203 is located between the first pattern material layer 202 and the layer to be etched 201.
The material of the second pattern material layer 203 includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the material of the second pattern material layer 203 includes silicon dioxide, titanium nitride, and silicon oxycarbide. The second pattern material layer 203 has a multi-layer structure, and includes a silicon dioxide material layer (not shown) on the surface of the layer to be etched 201, a titanium nitride material layer (not shown) on the silicon dioxide layer, and a silicon oxycarbide material layer (not shown) on the titanium nitride material layer. The second pattern material layer 203 is used for forming a second pattern layer subsequently.
The material of the first pattern material layer 202 includes silicon. In this embodiment, the material of the first pattern material layer 202 is amorphous silicon. In other embodiments, the material of the first pattern material layer 202 may also be polysilicon, silicon oxide, silicon carbide, or the like. The first patterned material layer 202 is used to subsequently form a first patterned layer.
When the first pattern material layer 202 is formed, the bottom anti-reflective coating material in the photolithography process before the layer to be etched 201 is formed remains on the second region ii, so that the adhesion between the first pattern material layer 202 and the layer to be etched 201 is poor. Subsequently, a first ion is implanted into the surface of the first pattern material layer 202 to generate a stress in the first pattern material layer 202, and due to the height difference between the first area i and the second area ii, the stress at the adjacent position M of the first pattern material layer 202 between the first area i and the second area ii is the largest, and the adjacent position M between the first area i and the second area ii is easily the adhesion weak point of the first pattern material layer on the second area ii.
Referring to fig. 7 and 8, first ions 204 are implanted into the surface of the first pattern material layer 202 to peel off the first pattern material layer 202 located on the second region ii, and at least a portion of the peeled first pattern material layer 202 adheres to the surface of the layer to be etched 201 to form a residue 205.
The process parameters of the first ion 204 implantation include: the first ions include one or more of carbon ions, nitrogen ions, and oxygen ions, the implanted ions have an energy in a range of 5keV to 20keV, and a concentration in a range of 1.0E14atom/cm3To 1.0E20atom/cm3。
First ions 204 are implanted into the surface of the first graphic material layer 202, and the first graphic material layer 202 generates stress and surface static electricity due to the implantation of the first ions 204, and the stress causes the first graphic material layer 202 which is not firmly adhered and is positioned on the surface of the second zone II to tear apart and separate from the weak point of adhesion. In particular, the point of weakness is located at the point M where the first zone i and the second zone ii adjoin. Under the action of surface static electricity and gravity, a portion of the peeled off first pattern material layer 202 adheres to the layer 201 to be etched, forming a residue 205. And subsequently cleaning and removing the residues 205 to separate and remove the first pattern material layer 202 which is positioned on the surface of the second area II and is not firmly adhered before subsequent processes, so that the subsequent etching process is prevented from being influenced, the influence of the height difference of the layer to be etched 201 positioned on the edge of the wafer on the etching process in the subsequent pattern definition is reduced, the pattern definition accuracy is improved, and the device performance is improved.
In this embodiment, first ions 204 are implanted into the surface of the first pattern material layer 202, so that the first pattern material layer 202 located on the second region ii is peeled off, and the second pattern material layer 203 located on the second region ii is also peeled off. The residue 205 also includes a layer of second patterning material 203 that is peeled off and adheres to the surface of the layer to be etched 201.
Subsequently, after the residues are cleaned and removed, an imaging structure is formed on the surface of the first pattern material layer 202, the imaging structure has a first opening therein, and a part of the first pattern material layer 202 is exposed at the bottom of the first opening; and injecting second ions into the bottom of the first opening to enable the first pattern material layer exposed at the bottom of the first opening to form a modified area. The first ion implantation process and the second ion implantation process are different in ion type, so that the second ion implantation process is prevented from being influenced, and subsequent pattern definition is not influenced.
Referring to fig. 9, the residue 205 is cleaned.
The process of cleaning and removing the residue 205 is a wet process. In this embodiment, the cleaning solution of the wet process includes deionized water containing carbon dioxide. The wet process can reduce damage to the layer to be etched 201 during the cleaning process.
Referring to fig. 10, after cleaning and removing the residue 205, an image structure 206 is formed on the surface of the first pattern material layer 202.
The patterning structure 206 includes a first anti-reflective layer (not shown) on the surface of the first pattern material layer 202, a second anti-reflective layer (not shown) on the surface of the first anti-reflective layer, and a photoresist layer (not shown) on the surface of the second anti-reflective layer.
The method for forming the imaging structure 206 comprises the following steps: forming a first anti-reflective material layer (not shown) on the surface of the first pattern material layer 202, forming a second anti-reflective material layer (not shown) on the surface of the first anti-reflective material layer, and forming a photoresist material layer (not shown) on the surface of the second anti-reflective material layer; patterning the photoresist material layer to form a photoresist layer, and etching the first anti-reflection material layer and the second anti-reflection material layer by using the photoresist layer as a mask until the surface of the first pattern material layer 202 is exposed to form the first anti-reflection layer and the second anti-reflection layer.
The forming process of the first anti-reflection material layer comprises a spin coating process.
The material of the first anti-reflective material layer includes a carbon-containing polymer. The first anti-reflection material layer is used for forming a first anti-reflection layer, and the material of the first anti-reflection layer comprises carbon-containing polymer. During the etching process for forming the patterned structure 206, the first anti-reflective material layer plays a role of pattern transmission, and simultaneously, since the first anti-reflective material layer has etching resistance, the collapse of the second anti-reflective layer (and the photoresist layer on the second anti-reflective layer) supported by the first anti-reflective material layer can be reduced.
The forming process of the second anti-reflection material layer comprises a spin coating process.
The material of the second anti-reflection material layer comprises organic polymer. The second antireflection material layer is used for forming a second antireflection layer, and the material of the second antireflection layer comprises organic polymer. The second anti-reflection material layer is used for reducing reflection of light at the bottom of the photoresist material layer in the etching process.
In this embodiment, the patterned structure 206 has a first opening 207 therein, and a portion of the first patterned material layer 202 is exposed at the bottom of the first opening 207. The patterned structure 206 is subsequently used as a mask to form a first patterned layer.
Referring to fig. 11, second ions 208 are implanted into the bottom of the first opening 207, so that the modified region 209 is formed on the first pattern material layer 202 exposed at the bottom of the first opening 207.
The process parameters for implanting the second ions 208 include: the second ions include P-type ions or N-type ions and have an energy ranging from 5keV to 20 keV. In this embodiment, the second ions 208 are P-type ions, and specifically, the second ions 208 are boron.
Subsequently, the modified region 209 is removed, so that the first pattern material layer 202 forms a first pattern layer. After the second ions 208 are implanted, the etching rate of the first pattern material layer 202 is changed, and in the etching process for removing the modified region 209, the damage to the first pattern layer can be reduced while removing the modified region 209. On the other hand, since the residue 205 (as shown in fig. 8) is removed before the formation of the patterned structure 206, the process of implanting the second ions 208 is not affected, and the absence of the target first pattern layer is avoided, so as to form the first pattern layer uniformly distributed on the second pattern material layer 203.
Referring to fig. 12, the modified region 209 is removed (as shown in fig. 11), so that the first pattern material layer 202 forms a first pattern layer 210.
The first pattern layer 210 may be used as a mask layer for pattern definition, or may be used as a mandrel in a process of pattern definition (such as self-aligned dual pattern technology (SADP)), and then a sidewall is formed on a sidewall of the first pattern layer 210, where the sidewall is used to define a pattern with a smaller size. In this embodiment, the first pattern layer 210 is used as a mandrel, and then a sidewall is formed on a sidewall of the first pattern layer 210.
In this embodiment, before forming the sidewall, the imaging structure 206 is also removed.
The process of removing the patterned structure 206 includes one or a combination of dry and wet processes. In this embodiment, the process of removing the imaging structure 206 is a dry process, and specifically, the process of removing the imaging structure 206 is an ashing process. The ashing process can improve the removal rate of the patterned structure 206, reduce the damage to the first pattern layer 210 and the second pattern material layer 203 during the process of removing the patterned structure 206, and have high reliability.
Referring to fig. 13, a sidewall 211 is formed on the sidewall of the first pattern layer 210.
The material of the sidewall 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
The forming method of the side wall 211 comprises the following steps: depositing a side wall material layer (not shown) on the surfaces of the first pattern layer 210 and the second pattern layer 203, and etching back the side wall material layer until the top surfaces of the first pattern layer 210 and the second pattern layer 203 are exposed to form the side wall 211.
The width of the side wall 211 is determined by the thickness of the side wall material layer, and the width of the side wall 211 can be controlled by adjusting the thickness of the side wall material layer. The sidewall spacers 211 may be used as a mask for pattern definition. In order to improve the accuracy of pattern transfer, in this embodiment, the sidewall 211 is further configured to form a second pattern layer, where the second pattern layer is used as a mask for pattern definition. Please refer to fig. 14 to fig. 15 for a method of forming the second graphic layer.
Referring to fig. 14, after the sidewalls 211 are formed, the first pattern layer 210 is removed.
The process of removing the first pattern layer 210 includes one or a combination of a wet etching process and a dry etching process.
In this embodiment, the material of the first pattern layer 210 is determined by the material of the first pattern material layer 202, the first pattern layer 210 is amorphous silicon, and the process of removing the first pattern layer 210 is a wet etching process. The parameters of the wet etching process comprise: the adopted solution comprises ammonia water solution, the temperature is 30-80 ℃, and the concentration of the ammonia water is 30-70% (volume ratio). The ammonia water solution has high selectivity ratio to the amorphous silicon material and the silicon oxide material, so that damage to the side wall 211 is reduced in the process of removing the first pattern layer 210.
Since the first pattern layer 210 has the characteristic of uniform distribution, the formed sidewall 211 has the characteristic of uniform distribution in the second pattern material layer 203, and the accuracy of pattern definition can be improved by using the sidewall 211 as a mask.
Referring to fig. 15, the second pattern material layer 203 is etched by using the sidewall spacers 211 as masks until the surface of the layer 201 to be etched is exposed, so as to form a second pattern layer 212.
The process for etching the second pattern material layer 203 includes a dry etching process and a wet etching process. In this embodiment, the process of etching the second pattern material layer 203 is a dry etching process. The technological parameters of the dry etching process comprise: the etching gas comprises CF4、CHF3The power range is 300 watts to 1000 watts. The dry etching process facilitates the formation of the second pattern layer 212 with a better topography.
Subsequently, the second graphics layer 212 may be used as a mask in a graphics definition process. The second pattern layer 212 is obtained by pattern transfer of the side wall 211, so that the second pattern layer 212 also has the characteristic of uniform distribution on the surface of the layer to be etched 201, and the accuracy of pattern definition can be improved by using the second pattern layer 212 as a mask.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region surrounding the first region, and the top surface of the second region is lower than that of the first region;
forming a first pattern material layer on the layer to be etched;
injecting first ions into the surface of the first pattern material layer to enable the first pattern material layer positioned on the second area to fall off, and adhering at least part of the fallen first pattern material layer to the surface of the layer to be etched to form residues;
cleaning to remove the residues;
and after cleaning and removing the residues, forming an imaging structure on the surface of the first pattern material layer.
2. The method of claim 1, wherein the patterned structure has a first opening therein, and a portion of the first patterned material layer is exposed at a bottom of the first opening; the forming method further comprises: injecting second ions into the bottom of the first opening to enable the first pattern material layer exposed at the bottom of the first opening to form a modified area; and removing the modified area to enable the first pattern material layer to form a first pattern layer.
3. The method of forming a semiconductor structure of claim 2, further comprising, prior to forming the first patterned material layer: and forming a second pattern material layer on the surface of the layer to be etched, wherein the second pattern material layer is positioned between the first pattern material layer and the layer to be etched.
4. The method of claim 3, wherein the material of the second patterned material layer comprises one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
5. The method of claim 3, wherein the first ions are implanted into the surface of the first patterned material layer to exfoliate the first patterned material layer in the second region and the second patterned material layer in the second region.
6. The method of forming a semiconductor structure of claim 3, further comprising: and forming a side wall on the side wall of the first pattern layer.
7. The method of forming a semiconductor structure of claim 6, further comprising: before the side wall is formed, the imaging structure is also removed; and after the side wall is formed, removing the first pattern layer.
8. The method of claim 6, wherein the material of the sidewall spacers comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
9. The method of forming a semiconductor structure of claim 7, further comprising: and etching the second pattern material layer by taking the side wall as a mask until the surface of the layer to be etched is exposed to form a second pattern layer.
10. The method as claimed in claim 1, wherein the patterned structure comprises a first anti-reflection layer on the surface of the first pattern layer, a second anti-reflection layer on the surface of the first anti-reflection layer, and a photoresist layer on the surface of the second anti-reflection layer.
11. The method of forming a semiconductor structure of claim 10, wherein a material of the first anti-reflective layer comprises a carbon-containing polymer.
12. The method of forming a semiconductor structure of claim 10, wherein a material of the second anti-reflective layer comprises an organic polymer.
13. The method of forming a semiconductor structure of claim 1, wherein a material of the first layer of patterning material comprises silicon.
14. The method of forming a semiconductor structure of claim 1, wherein the cleaning to remove the residue is a wet process.
15. The method of forming a semiconductor structure of claim 14, wherein the wet process cleaning solution comprises carbon dioxide-containing deionized water.
16. The method of claim 1, wherein the process parameters of the first ion implantation comprise: the first ions include one or more of carbon ions, nitrogen ions, and oxygen ions, the implanted ions have an energy in a range of 5keV to 20keV, and a concentration in a range of 1.0E14atom/cm3To 1.0E20atom/cm3。
17. The method of forming a semiconductor structure of claim 1, wherein a material of the first layer of patterning material comprises silicon.
18. The method of claim 1, wherein the process parameters for implanting the second ions comprise: the second ions include P-type ions or N-type ions and have an energy ranging from 5keV to 20 keV.
CN202011324630.6A 2020-11-23 2020-11-23 Method for forming semiconductor structure Pending CN114530369A (en)

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