KR100265340B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR100265340B1 KR100265340B1 KR1019980025221A KR19980025221A KR100265340B1 KR 100265340 B1 KR100265340 B1 KR 100265340B1 KR 1019980025221 A KR1019980025221 A KR 1019980025221A KR 19980025221 A KR19980025221 A KR 19980025221A KR 100265340 B1 KR100265340 B1 KR 100265340B1
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- film
- conductive film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229920000642 polymer Polymers 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 22
- 239000000203 mixture Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
반도체소자 제조를 위한 감광막패턴 형성후 그 하부의 질화막을 실리콘기판에 손상을 가하는 일 없이 완벽하게 제거하기 위하여 반도체기판 상부에 제1도전막을 형성하는 단계와, 상기 제1전도막 상부에 질화막을 형성하는 단계, 상기 질화막 상부에 소정의 감광막패턴을 형성하는 단계, 상기 감광막패턴 측면에 플라즈마를 이용하여 폴리머를 형성함과 동시에 감광막패턴이 형성되지 않은 부분의 노출된 상기 질화막을 제거하는 단계, 상기 감광막패턴 및 폴리머를 마스크로 이용하여 상기 제1전도막을 건식식각하여 제1전도막패턴을 형성함과 동시에 상기 감광막패턴을 제거하고 그 하부의 질화막을 일정두께 제거하는 단계, 상기 폴리머를 제거하는 단계, 상기 반도체기판 전면에 절연막을 형성하는 단계, 상기 절연막을 선택적으로 식각하여 상기 반도체기판 및 제1전도막패턴의 소정부분을 노출시키는 콘택홀을 형성하는 단계 및 상기 콘택홀을 포함한 절연막 전면에 제2전도막을 형성하는 단계를 포함하여 구성되는 반도체소자 제조방법을 제공한다.After the formation of the photoresist pattern for manufacturing a semiconductor device to form a first conductive film on the semiconductor substrate to completely remove the lower nitride film without damaging the silicon substrate, and forming a nitride film on the first conductive film Forming a predetermined photoresist pattern on the nitride film, forming a polymer on the side of the photoresist pattern, and removing the exposed nitride film of a portion where the photoresist pattern is not formed; Dry etching the first conductive film using a pattern and a polymer as a mask to form a first conductive film pattern, and simultaneously removing the photoresist pattern and removing a predetermined thickness of a lower nitride film, removing the polymer; Forming an insulating film on the entire surface of the semiconductor substrate, selectively etching the insulating film to Providing a conductive substrate, and a first step of forming a contact hole exposing a predetermined portion of the conductive layer pattern and the second conductive semiconductor device manufacturing method which comprises a step of forming a film on the insulating film including over the contact hole.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자 제조를 위한 감광막패턴 형성후 그 하부의 질화막을 실리콘기판에 손상을 가하는 일 없이 완벽하게 제거하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for completely removing a nitride film under the silicon substrate without damaging the silicon substrate after forming the photoresist pattern for manufacturing the semiconductor device.
반도체소자 제조공정중 질화막은 감광막패턴 형성시 빛의 반사효과를 억제하여 패턴불량을 방지하고 균일한 크기의 패턴을 형성하는데 있어서 중요한 막이다. 그러나 이러한 질화막이 후속공정인 콘택홀 형성공정에서는 제거하기가 상당히 까다로운 막이어서 이를 제거하기 위해 타겟을 증가시키면 실리콘기판에 손상이 가해지므로 타겟을 증가시키는 것도 어렵다. 이러한 현상은 반도체소자가 집적화될수록 콘택홀의 크기도 작아지면서 동시에 실리콘기판에 주입되는 이온의 주입깊이도 얕아져 질화막 제거가 더욱 어렵게 되고 있다.In the semiconductor device manufacturing process, the nitride film is an important film for preventing pattern defects by forming a photoresist pattern and preventing pattern defects and forming a pattern having a uniform size. However, such a nitride film is a very difficult film to be removed in a subsequent process of forming a contact hole, so increasing the target to remove it causes damage to the silicon substrate, which makes it difficult to increase the target. As the semiconductor device is integrated, the contact hole becomes smaller and the depth of implantation of ions injected into the silicon substrate becomes shallower, making it more difficult to remove the nitride film.
도 1a 내지 도 1d를 참조하여 종래기술에 의하여 반도체소자 제조를 위한 감광막패턴 형성후 그 하부의 질화막을 제거하는 방법을 설명한다.1A to 1D, a method of removing the nitride film under the photoresist film pattern for manufacturing a semiconductor device according to the prior art will be described.
도 1a을 참조하면, 실리콘기판(1)상에 소정의 패턴(1)(게이트(1)와 게이트 캡산화막(2) 및 게이트 측벽스페이서(3)로 이루어진)을 형성한 후, 기판 전면에 제1전도막(4)을 형성하고, 그 상부에 질화막(5)을 형성한다. 이어서 질화막(5)위에 감광막을 도포하고 노광하여 소정의 감광막패턴(6)을 형성한다.Referring to FIG. 1A, a predetermined pattern 1 (composed of a gate 1, a gate cap oxide film 2, and a gate sidewall spacer 3) is formed on a silicon substrate 1, and then the front surface of the substrate is formed on the silicon substrate 1. One conductive film 4 is formed, and a nitride film 5 is formed thereon. Subsequently, a photoresist film is applied and exposed on the nitride film 5 to form a predetermined photoresist pattern 6.
이어서 도 1b를 참조하면, 상기 감광막패턴(6) 측면에 플라즈마를 이용하여 폴리머(7)를 형성하여 패턴의 크기를 늘리면서 동시에 감광막패턴이 형성되지 않은 부분의 질화막을 제거한다.Subsequently, referring to FIG. 1B, the polymer 7 is formed on the side surface of the photoresist pattern 6 to increase the size of the pattern, and at the same time, the nitride film of the portion where the photoresist pattern is not formed is removed.
도 1c를 참조하면, 상기 감광막 및 폴리머패턴(6,7)을 마스크로 이용하여 제1전도막(4)을 건식식각하여 제1전도막패턴을 형성한다.Referring to FIG. 1C, the first conductive film 4 is dry-etched using the photosensitive films and the polymer patterns 6 and 7 as masks to form a first conductive film pattern.
도 1d를 참조하면, 상기 감광막 및 폴리머패턴을 제거한 후, 기판 전면에 절연막(8)을 형성한 다음 선택적으로 식각하여 소정위치에 콘택홀을 형성한다. 이어서 상기 콘택홀을 포함한 절연막(8) 전면에 제2전도막(9)을 형성한다. 이때, 도시된 바와 같이 콘택홀 형성시 실리콘기판의 손상을 방지하기 위하여 식각타겟을 증가시키지 못하는 이유로 제1전도막패턴(4) 상부에 남아 있는 질화막(5)이 완전히 제거되지 않는다. 이와 같이 남아 있는 질화막은 제2전도막 형성시 제1전도막과의 연결을 방해하여 단선(open)에 의한 페일(fail)을 유발하여 (도 1d의 A부분 참조) 반도체소자의 신뢰성 및 수율을 저하시킨다.Referring to FIG. 1D, after removing the photoresist film and the polymer pattern, an insulating film 8 is formed on the entire surface of the substrate and then selectively etched to form a contact hole at a predetermined position. Subsequently, a second conductive film 9 is formed over the insulating film 8 including the contact hole. In this case, the nitride film 5 remaining on the upper portion of the first conductive film pattern 4 is not completely removed because the etching target is not increased to prevent damage to the silicon substrate when forming the contact hole. The remaining nitride film interrupts the connection with the first conductive film when the second conductive film is formed, causing a failure due to disconnection (see part A of FIG. 1D) to improve the reliability and yield of the semiconductor device. Lowers.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 감광막패턴 형성후 그 하부의 반사방지막을 실리콘기판에 손상을 가하는 일 없이 완벽하게 제거하는 반도체소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device which completely removes an anti-reflection film under the photoresist pattern without damaging the silicon substrate.
도 1a 내지 도 1d는 종래기술에 의한 반도체소자 제조를 위한 감광막패턴 형성후 그 하부의 질화막을 제거하는 방법을 도시한 공정순서도,1A to 1D are process flowcharts illustrating a method of removing a nitride film below a photoresist pattern for forming a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체소자의 제조방법을 도시한 공정순서도.2A to 2D are process flowcharts illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3a 내지 도 3c는 본 발명을 반도체소자 제조에 실제로 적용한 예를 나타낸 사진.3A to 3C are photographs showing an example in which the present invention is actually applied to manufacturing a semiconductor device.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1.게이트 2.게이트 캡산화막1.gate 2.gate cap oxide
3.게이트 측벽스페이서 4.제1전도막3. Gate sidewall spacer 4. First conductive film
5.질화막 6.감광막패턴5.nitride film 6.photoresist pattern
7.폴리머 8.절연막7.Polymer 8.Insulation Film
9.제2전도막9.second conductive film
상기 목적을 달성하기 위하여 본 발명에 의한 반도체소자의 제조방법은 반도체기판 상부에 제1도전막을 형성하는 단계와; 상기 제1전도막 상부에 질화막을 형성하는 단계; 상기 질화막 상부에 소정의 감광막패턴을 형성하는 단계; 상기 감광막패턴 측면에 플라즈마를 이용하여 폴리머를 형성함과 동시에 감광막패턴이 형성되지 않은 부분의 노출된 상기 질화막을 제거하는 단계; 상기 감광막패턴 및 폴리머를 마스크로 이용하여 상기 제1전도막을 건식식각하여 제1전도막패턴을 형성함과 동시에 상기 감광막패턴을 제거하고 그 하부의 질화막을 일정두께 제거하는 단계; 상기 폴리머를 제거하는 단계; 상기 반도체기판 전면에 절연막을 형성하는 단계; 상기 절연막을 선택적으로 식각하여 상기 반도체기판 및 제1전도막패턴의 소정부분을 노출시키는 콘택홀을 형성하는 단계 및 상기 콘택홀을 포함한 절연막 전면에 제2전도막을 형성하는 단계를 포함하여 구성된다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a first conductive film on an upper surface of a semiconductor substrate; Forming a nitride film on the first conductive film; Forming a predetermined photoresist pattern on the nitride film; Forming a polymer on the side of the photoresist pattern using plasma and removing the exposed nitride layer of a portion where the photoresist pattern is not formed; Dry etching the first conductive film using the photosensitive film pattern and the polymer as a mask to form a first conductive film pattern, and simultaneously removing the photosensitive film pattern and removing a predetermined thickness of a lower nitride film; Removing the polymer; Forming an insulating film on the entire surface of the semiconductor substrate; Selectively etching the insulating film to form a contact hole exposing a predetermined portion of the semiconductor substrate and the first conductive film pattern, and forming a second conductive film on an entire surface of the insulating film including the contact hole.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2d에 본 발명의 일실시예에 의한 반도체소자의 제조방법을 공정순서에 따라 도시하였다.2A to 2D illustrate a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of a process.
먼저, 도 2a를 참조하면, 실리콘기판(1)상에 소정의 도전층 패턴(1)(게이트(1)와 게이트 캡산화막(2) 및 게이트 측벽스페이서(3)로 이루어진)을 형성한 후, 기판 전면에 제1전도막(4)으로서, 예컨대 비정질실리콘을 증착하고, 그 상부에 질화막(5)을 형성한다. 이어서 질화막(5)위에 감광막을 도포하고 노광하여 소정의 감광막패턴(6)을 형성한다.First, referring to FIG. 2A, a predetermined conductive layer pattern 1 (composed of a gate 1, a gate cap oxide film 2, and a gate sidewall spacer 3) is formed on a silicon substrate 1. As the first conductive film 4, for example, amorphous silicon is deposited on the entire surface of the substrate, and the nitride film 5 is formed thereon. Subsequently, a photoresist film is applied and exposed on the nitride film 5 to form a predetermined photoresist pattern 6.
이어서 도 2b를 참조하면, 상기 감광막패턴(6) 측면에 플라즈마를 이용하여 폴리머(7)를 형성하여 패턴의 크기를 늘리면서 동시에 감광막패턴이 형성되지 않은 부분의 질화막을 제거한다. 상기 폴리머는 HBr가스 또는 HBr을 함유하는 가스등을 이용하여 플라즈마를 발생시켜 형성한다.Subsequently, referring to FIG. 2B, the polymer 7 is formed on the side surface of the photoresist pattern 6 to increase the size of the pattern, and at the same time, the nitride film of the portion where the photoresist pattern is not formed is removed. The polymer is formed by generating plasma using HBr gas or a gas containing HBr.
도 2c를 참조하면, 상기 감광막 및 폴리머패턴(6,7)을 마스크로 이용하여 제1전도막(4)을 건식식각하는 바, 일단 제1전도막을 건식식각하여 제1전도막패턴(4)을 형성한 후, 감광막에 대하여 낮은 식각선택비를 갖는 건식식각을 실시하여 제1전도막패턴(4) 상부에 존재하는 감광막패턴(6)을 제거함과 동시에 감광막 하부에 위치하고 있는 질화막(5)을 일정두께 식각하고 일정두께만 남도록 한다. (A부분 참조) 이때 제1전도막(4)에 대한 식각선택비는 상당히 높아야 한다. 보다 구체적으로 설명하면, 상기 감광막패턴 제거를 위한 건식식각시 제1전도막에 대해서는 식각선택비가 60이상이고, 감광막에 대해서는 5이하이며, 감광막패턴 제거후, 질화막 제거를 위한 건식식각시 질화막에 대한 식각선택비는 15이하인 것이 바람직하다. 상기 건식식각은 플라즈마를 이용하여 행하는데 플라즈마 발생시 Cl2가스를 주된 식각물질로 사용하고 O2, N2, HBr, SF6, NF3등을 혼합하여 사용한다. 또한, 상기 질화막을 식각하기 위한 건식식각은 O2를 함유하는 가스의 플라즈마를 이용하여 행한다. 상기 제1전도막패턴 형성 및 감광막패턴 제거는 1회의 식각공정에 의해 동시에 실시하거나 2단계 이상의 건식식각을 이용하여 각각 제거할 수 있다.Referring to FIG. 2C, the first conductive film 4 is dry-etched using the photoresist film and the polymer patterns 6 and 7 as a mask, so that the first conductive film is dry-etched once to form the first conductive film pattern 4. After forming the photoresist, dry etching having a low etching selectivity with respect to the photoresist film is performed to remove the photoresist pattern 6 existing on the first conductive film pattern 4 and to simultaneously remove the nitride film 5 positioned below the photoresist film. Etch a certain thickness and leave only a certain thickness. In this case, the etching selectivity of the first conductive film 4 should be considerably high. In more detail, the etching selectivity of the first conductive film during the dry etching process for removing the photoresist pattern is 60 or more, the photoresist film has an etching selectivity of 5 or less, and after removing the photoresist pattern, the nitride film for the dry etching process for removing the nitride film The etching selectivity is preferably 15 or less. The dry etching is performed by using a plasma. When plasma is generated, Cl 2 gas is used as a main etching material, and O 2 , N 2 , HBr, SF 6 , and NF 3 are mixed and used. In addition, dry etching for etching the nitride film is performed using a plasma of a gas containing O 2 . The formation of the first conductive film pattern and the removal of the photosensitive film pattern may be simultaneously performed by one etching process or may be removed by using two or more dry etching processes.
도 2d를 참조하면, 상기 폴리머를 제거한 후, 기판 전면에 절연막(8)을 형성한 다음 선택적으로 식각하여 소정위치에 콘택홀을 형성한다. 이어서 상기 콘택홀을 포함한 절연막(8) 전면에 제2전도막(9)을 형성한다. 이때, 상기한 바와 같이 질화막을 미리 일정두께 식각해 놓음으로써 상기 콘택홀 형성시 실리콘기판의 손상도 방지하면서 콘택홀 내부의 질화막도 완전히 제거할 수 있다. (B참조) 따라서 제1전도막(4)과 제2전도막(9)의 연결에 전혀 문제가 없는 안정된 소자를 제조할 수 있다.Referring to FIG. 2D, after the polymer is removed, an insulating film 8 is formed on the entire surface of the substrate and then selectively etched to form a contact hole at a predetermined position. Subsequently, a second conductive film 9 is formed over the insulating film 8 including the contact hole. At this time, the nitride film is etched in a predetermined thickness as described above, thereby preventing the damage of the silicon substrate during the formation of the contact hole, and completely removing the nitride film inside the contact hole. Therefore, a stable element having no problem in connection between the first conductive film 4 and the second conductive film 9 can be manufactured.
도 3a 내지 도 3c는 본 발명을 반도체소자 제조에 실제로 적용한 예를 사진으로 나타낸 것으로, 도 3a는 상기 제1전도막패턴을 형성한 후의 단면형상이고, 도 3b는 콘택홀 형성후, 그리고 도 3c는 제2전도막 형성후의 단면형상을 나타낸 것이다. 도시된 바와 같이 질화막이 완벽히 제거되어 제1전도막과 제2전도막의 연결이 잘 이루어짐을 알 수 있다3A to 3C are photographs showing an example of the present invention actually applied to manufacturing a semiconductor device. FIG. 3A is a cross-sectional shape after the first conductive film pattern is formed. FIG. 3B is a view after forming a contact hole, and FIG. 3C. Shows the cross-sectional shape after formation of the second conductive film. As shown in the drawing, the nitride film is completely removed, and thus the first conductive film and the second conductive film are well connected.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명에 의하면, 소자동작에 치명적인 단선에 의한 페일(fail)을 완벽하게 제거할 수 있으며, 동시에 실리콘기판의 접합영역의 손상이 거의 없으므로 소자의 신뢰성을 향상시킬 수 있다. 또한, 반도체소자의 수율을 증대시킬 있고, 신규장비에 대한 투자없이도 반도체소자의 집적도를 높일 수 있다.According to the present invention, it is possible to completely eliminate the fail due to the disconnection which is fatal to the operation of the device, and at the same time, there is almost no damage to the junction area of the silicon substrate, thereby improving the reliability of the device. In addition, the yield of semiconductor devices can be increased, and the degree of integration of semiconductor devices can be increased without investment in new equipment.
Claims (10)
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