KR19990005859A - Word line formation method of flash memory device - Google Patents
Word line formation method of flash memory device Download PDFInfo
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- KR19990005859A KR19990005859A KR1019970030077A KR19970030077A KR19990005859A KR 19990005859 A KR19990005859 A KR 19990005859A KR 1019970030077 A KR1019970030077 A KR 1019970030077A KR 19970030077 A KR19970030077 A KR 19970030077A KR 19990005859 A KR19990005859 A KR 19990005859A
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs
본 발명은 스플릿 게이트 구조의 플래쉬 메모리 소자에서 워드라인(Word Line) 형성방법에 관한 것으로, 특히 워드라인 형성을 위한 식각공정 후에 워드라인의 가장자리 부분에 발생되는 언더컷(Undercut)을 방지할 수 있는 플래쉬 메모리 소자의 워드라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a word line in a flash memory device having a split gate structure, and more particularly, to prevent undercuts occurring at edge portions of word lines after an etching process for forming word lines. A word line forming method of a memory device.
2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve
워드라인 형성을 위한 식각공정후에 발생하는 도전성 잔류물을 제거하기 위하여 실시되는 비등방성 식각시 워드라인의 가장자리 부분에 발생되는 언더컷을 방지하고자 한다.It is intended to prevent undercuts generated at the edges of word lines during anisotropic etching, which is performed to remove conductive residues generated after the etching process for forming word lines.
3.발명의 해결방법의 요지3. Summary of the solution of the invention
워드라인 형성을 위한 식각공정후에 발생하는 도전성 잔류물을 제거하지 않은 상태에서 절연막 스페이서를 형성한 후 식각공정으로 도전성 잔류물을 제거하여 워드라인의 언더컷 발생 및 소자의 전기적 단락을 방지할 수 있다.After forming the insulating film spacer without removing the conductive residue generated after the etching process for forming the word line, the conductive residue may be removed by the etching process to prevent undercut of the word line and electrical short circuit of the device.
4.발명의 중요한 용도4. Important uses of the invention
반도체 소자 제조Semiconductor device manufacturing
Description
본 발명은 스플릿 게이트 구조의 플래쉬 메모리 소자에서 워드라인(Word Line) 형성방법에 관한 것으로, 특히 워드라인 형성을 위한 식각공정 후에 워드라인의 가장자리 부분에 발생되는 언더컷(Undercut)을 방지할 수 있는 플래쉬 메모리 소자의 워드라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a word line in a flash memory device having a split gate structure, and more particularly, to prevent undercuts occurring at edge portions of word lines after an etching process for forming word lines. A word line forming method of a memory device.
일반적으로, 스플릿 게이트 구조를 갖는 플래쉬 메모리 소자에서 워드라인을 형성하기 위한 식각공정후에 워드라인용 도전성 잔류물이 남게되어 이웃하는 워드라인이 전기적으로 단락되는 등의 문제가 있다. 이를 해결하기 위하여, 식각공정을 추가로 실시하여 도전성 잔류물을 제거하는데 도 1a 내지 도 1c를 참조하여 설명하면 다음과 같다.In general, there is a problem in that a conductive residue for a word line remains after an etching process for forming a word line in a flash memory device having a split gate structure, such that an adjacent word line is electrically shorted. In order to solve this problem, an etching process is further performed to remove conductive residues, which will be described below with reference to FIGS. 1A to 1C.
도 1a 내지 도 1c는 종래 스플릿 게이트 구조를 갖는 플래쉬 메모리 소자의 워드라인 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for describing a word line forming method of a conventional flash memory device having a split gate structure.
도 1a는 필드 산화막(2)이 형성되어 있는 반도체 기판(1) 상에 플로팅 게이트 및 콘트롤 게이트(도시않음)를 형성한 후 워드라인을 형성하기 위하여, 폴리실리콘층(3), 실리사이드막(4) 및 감광막 패턴(5)을 순차적으로 형성한 상태의 단면도이다.FIG. 1A illustrates a polysilicon layer 3 and a silicide film 4 in order to form a word line after forming a floating gate and a control gate (not shown) on a semiconductor substrate 1 on which a field oxide film 2 is formed. ) And the photosensitive film pattern 5 are sectional views sequentially.
도 1b는 상기 감광막 패턴(5)을 마스크로 이용한 식각공정으로 상기 실리사이드막(4) 및 폴리실리콘층(3)을 패터닝한 상태의 단면도이다. 그런데 식각공정후 폴리실리콘 잔류물(3A)이 남게된다.FIG. 1B is a cross-sectional view of the silicide layer 4 and the polysilicon layer 3 patterned by an etching process using the photosensitive layer pattern 5 as a mask. However, after the etching process, the polysilicon residue 3A remains.
도 1c는 상기 폴리실리콘 잔류물(3A)을 비등방성 식각공정으로 제거하여 워드라인(10)이 형성된 상태의 단면도이다. 그러나 비등방성 식각공정시 폴리실리콘층(3)이 일부식각되어 워드라인(10)의 가장자리 부분에 언더컷(6)이 발생된다.1C is a cross-sectional view of the word line 10 formed by removing the polysilicon residue 3A by an anisotropic etching process. However, during the anisotropic etching process, the polysilicon layer 3 is partially etched to generate the undercut 6 at the edge of the word line 10.
상술한 바와같이 비등방성 식각공정으로 폴리실리콘 잔류물(3A)을 제거하여 워드라인(10) 간의 단락현상을 방지할 수는 있으나 워드라인(10) 가장자리부분에 언더컷(6)이 발생되어 소자의 전기적 특성저하를 유발시키는 문제가 있다.As described above, the polysilicon residue 3A may be removed by an anisotropic etching process to prevent a short circuit between the word lines 10, but an undercut 6 may be generated at the edge of the word line 10 so that There is a problem causing electrical deterioration.
따라서, 본 발명은 소자의 전기적 특성 및 프로파일을 개선할 할 수 있는 플래쉬 메모리 소자의 워드라인 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a word line forming method of a flash memory device capable of improving the electrical characteristics and the profile of the device.
상기한 목적을 달성하기 위한 본 발명은 반도체 기판 상에 플로팅 게이트 및 콘트롤 게이트를 형성한 후 워드라인을 형성하기 위하여, 제 1 도전층, 제 2 도전층 및 반사방지막을 순차적으로 형성하는 단계와, 상기 반사방지막, 제 2 도전층 및 제 1 도전층을 순차적으로 패터닝하고, 이때 상기 반도체 기판상의 일부분에 제 1 도전층 잔류물이 남게되는 단계와, 상기 패터닝 공정후의 전체상부면에 절연막을 형성한 후 스페이서 식각을 실시하여 상기 패터닝된 반사방지막, 제 2 도전층 및 제 1 도전층 측벽에 절연막 스페이서를 형성하는 단계와, 상기 반사방지막 및 상기 절연막 스페이서를 식각 마스크로 한 식각공정으로 상기 제 1 도전층 잔류물을 제거하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming the first conductive layer, the second conductive layer and the anti-reflection film to form a word line after forming the floating gate and the control gate on the semiconductor substrate, Patterning the antireflection film, the second conductive layer, and the first conductive layer sequentially, wherein a first conductive layer residue remains on a portion of the semiconductor substrate; and an insulating film is formed on the entire upper surface after the patterning process. And etching the spacers to form insulating film spacers on sidewalls of the patterned anti-reflective film, the second conductive layer and the first conductive layer, and etching the first anti-reflective film and the insulating film spacer using an etching mask. Removing layer residues.
도 1a 내지 도 1c는 종래 플래쉬 메모리 소자의 워드라인 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a word line forming method of a conventional flash memory device.
도 2a 내지 도 2d는 본 발명에 따른 플래쉬 메모리 소자의 워드라인 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a word line forming method of a flash memory device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
1 및 11 : 반도체 기판 2 및 12 : 필드 산화막1 and 11: semiconductor substrate 2 and 12: field oxide film
3 및 13 : 폴리실리콘층 3A 및 13A : 폴리실리콘 잔류물3 and 13: polysilicon layer 3A and 13A: polysilicon residue
4 및 14 : 실리사이드막 5 및 16 : 감광막 패턴4 and 14: silicide film 5 and 16: photosensitive film pattern
6 : 언더컷 15 : 반사방지막6: undercut 15: antireflection film
17 : 절연막 17A : 절연막 스페이서17 insulating film 17A insulating film spacer
10 및 20 : 워드라인10 and 20: wordline
이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.
도 2a 내지 도 2d는 본 발명에 따른 스플릿 게이트 구조를 갖는 플래쉬 메모리 소자의 워드라인 형성방법을 설명하기 위한 소자의 단면도이다.2A through 2D are cross-sectional views illustrating a device for forming a word line of a flash memory device having a split gate structure according to the present invention.
도 2a는 필드 산화막(12)이 형성되어 있는 반도체 기판(11) 상에 플로팅 게이트 및 콘트롤 게이트(도시않음)를 형성한 후 워드라인을 형성하기 위하여, 폴리실리콘층(13), 실리사이드막(14), 반사방지막(15) 및 감광막 패턴(16)을 순차적으로 형성된 상태의 단면도이다.FIG. 2A illustrates a polysilicon layer 13 and a silicide layer 14 in order to form a word line after forming a floating gate and a control gate (not shown) on a semiconductor substrate 11 on which a field oxide layer 12 is formed. ), The anti-reflection film 15 and the photosensitive film pattern 16 are sectional views sequentially formed.
도 2b는 상기 감광막 패턴(16)을 마스크로 이용한 식각공정으로 상기 반사방지막(15), 실리사이드막(14), 폴리실리콘층(13)을 순차적으로 식각하여 패터닝한 후 전체 상부면에 절연막(17)을 형성한 상태의 단면도이다. 이때 식각공정 후 폴리실리콘층(13)은 완전히 제거되지 않고 필드산화막(12) 및 반도체 기판(11) 상의 일부분에 폴리실리콘 잔류물(13A)이 남게 된다. 그리고 상기 절연막(17)은 폴리실리콘 및 산화물 중 어느 하나를 이용한 증착공정으로 형성한다.FIG. 2B illustrates an etching process using the photoresist pattern 16 as a mask, sequentially etching and patterning the antireflection film 15, the silicide film 14, and the polysilicon layer 13, and then insulating the insulating film 17 on the entire upper surface thereof. It is sectional drawing of the state formed. At this time, the polysilicon layer 13 is not completely removed after the etching process, and the polysilicon residue 13A remains on the field oxide layer 12 and a part of the semiconductor substrate 11. The insulating layer 17 is formed by a deposition process using any one of polysilicon and oxide.
도 2c는 스페이서 식각공정으로 상기 패터닝된 상기 반사방지막(15), 실리사이드막(14) 및 폴리실리콘층(13) 양 측벽에 절연막 스페이서(17A)를 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of an insulating film spacer 17A formed on both sidewalls of the anti-reflection film 15, the silicide film 14, and the polysilicon layer 13 patterned by a spacer etching process.
도 2d는 폴리실리콘 잔류물(13A)을 반사방지막(15) 및 절연막 스페이서(17A)를 식각 마스크로 한 습식 또는 건식 식각방법으로 제거하여 워드라인(20)이 형성된 상태의 단면도이다.FIG. 2D is a cross-sectional view of the word line 20 formed by removing the polysilicon residue 13A by a wet or dry etching method using the antireflection film 15 and the insulating film spacer 17A as an etching mask.
상술한 바와같이 종래 잔존 폴리실리콘층을 제거하기 위한 비등방성 식각으로 인하여 언더 컷이 발생되는 문제를 해소하기 위하여, 본 발명에서는 절연막 스페이서를 형성한 후 잔존 폴리실리콘층을 제거하므로 전기적 단락 및 언더 컷이 발생되는 문제를 해소하여 소자의 프로파일 및 전기적 특성이 향상되는 효과가 있다.As described above, in order to solve the problem that the undercut is generated due to anisotropic etching for removing the conventional residual polysilicon layer, the present invention removes the remaining polysilicon layer after forming the insulating film spacer, thereby reducing the electrical short and the undercut. This problem is solved to improve the profile and electrical properties of the device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030077A KR100274355B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming a word line in a flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030077A KR100274355B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming a word line in a flash memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990005859A true KR19990005859A (en) | 1999-01-25 |
| KR100274355B1 KR100274355B1 (en) | 2001-02-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970030077A KR100274355B1 (en) | 1997-06-30 | 1997-06-30 | Method of forming a word line in a flash memory device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100274355B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100376270B1 (en) * | 1999-12-28 | 2003-03-17 | 주식회사 하이닉스반도체 | Method of manufacturing a split gate type flash memory device |
| KR20040017125A (en) * | 2002-08-20 | 2004-02-26 | 삼성전자주식회사 | Method of manufacturing a flouting gate in non-volatile memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0141195B1 (en) * | 1994-06-08 | 1998-07-15 | 김광호 | Fabrication method of semiconductor device having low-resistance gate electrod |
-
1997
- 1997-06-30 KR KR1019970030077A patent/KR100274355B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100376270B1 (en) * | 1999-12-28 | 2003-03-17 | 주식회사 하이닉스반도체 | Method of manufacturing a split gate type flash memory device |
| KR20040017125A (en) * | 2002-08-20 | 2004-02-26 | 삼성전자주식회사 | Method of manufacturing a flouting gate in non-volatile memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100274355B1 (en) | 2001-02-01 |
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