KR100208450B1 - Method for forming metal wiring in semiconductor device - Google Patents

Method for forming metal wiring in semiconductor device Download PDF

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Publication number
KR100208450B1
KR100208450B1 KR1019960011721A KR19960011721A KR100208450B1 KR 100208450 B1 KR100208450 B1 KR 100208450B1 KR 1019960011721 A KR1019960011721 A KR 1019960011721A KR 19960011721 A KR19960011721 A KR 19960011721A KR 100208450 B1 KR100208450 B1 KR 100208450B1
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South Korea
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forming
cleaning process
semiconductor device
metal wiring
film
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KR1019960011721A
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Korean (ko)
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KR970072316A (en
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정창원
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 금속층간의 접촉 저항을 감소시키기 위하여 비아 홀을 형성한 후 비아 홀의 측벽이 피해를 받지 않으며, 폴리머가 완전히 제거되도록 세정 공정을 실시하므로써 소자의 동작시 누설 전류의 발생이 방지되며, 폴리머의 완전한 제거로 금속층간의 접촉 저항이 감소되어 소자의 전기적 특성이 향상될 수 있는 반도체 소자의 다중 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a multi-metal layer of a semiconductor device, and after forming the via hole in order to reduce the contact resistance between the metal layers, the sidewalls of the via hole are not damaged and the cleaning process is performed to completely remove the polymer. The present invention relates to a method of forming a multi-metal layer of a semiconductor device in which leakage current is prevented during operation, and the contact resistance between metal layers is reduced by the complete removal of the polymer, thereby improving the electrical characteristics of the device.

Description

반도체 소자의 다중 금속층 형성 방법Method of forming multiple metal layers in semiconductor devices

제1a도 내지 제1c도는 종래 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a multiple metal layer of a conventional semiconductor device.

제2a도 내지 제2d도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming a multi-metal layer of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 및 11 : 실리콘 기판 2 및 12 : 절연층1 and 11: silicon substrate 2 and 12: insulating layer

3 및 13 : 하부 금속배선 4 및 14 : 제1금속층간 절연막3 and 13: lower metal wiring 4 and 14: first interlayer insulating film

5 및 15 : SOG막 6 및 16 : 제2금속층간 절연막5 and 15: SOG film 6 and 16: Second metal interlayer insulating film

7 및 17 : 감광막 8 및 18 : 비아 홀7 and 17: photoresist 8 and 18: via hole

9 및 19 : 폴리머 10 및 20 : 상부 금속층9 and 19: polymer 10 and 20: upper metal layer

본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 특히 금속층간의 접촉 저항을 감소시킬 수 있도록 한 반도체 소자의 다중 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a multi-metal layer of a semiconductor device, and more particularly, to a method for forming a multi-metal layer of a semiconductor device to reduce the contact resistance between the metal layers.

일반적으로 반도체 소자의 제조 공정에서 금속층은 이중 또는 다중 구조로 형성되며, 금속층간에는 절연 및 평탄화를 위하여 금속층간 절연막을 형성한다. 또한 금속층간의 접속은 금속층간 절연막에 형성된 비아 홀(Via hole)을 통해 이루어지는데, 반도체 소자가 고집적화됨에 다라 비아홀의 크기가 감소되기 때문에 금속층간의 접속이 어려워지는 실정이다. 그러면 종래 반도체 소자의 다중 금속층 형성 방법을 제1a도 내지 제1c도를 통해 설명하면 다음과 같다.In general, in the process of manufacturing a semiconductor device, the metal layer is formed in a double or multiple structure, and an intermetallic insulating film is formed between the metal layers for insulation and planarization. In addition, the connection between the metal layers is made through via holes formed in the interlayer insulating film. Since the size of the via hole is reduced due to the high integration of semiconductor devices, the connection between the metal layers becomes difficult. A method of forming a multi-metal layer of a conventional semiconductor device will now be described with reference to FIGS. 1A through 1C.

제1a도 내지 제1c도는 종래 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도로서,1A to 1C are cross-sectional views of a device for describing a method of forming a multiple metal layer of a conventional semiconductor device.

제1a도는 절연층(2)이 형성된 실리콘 기판(1)상에 하부 금속층을 형성한 후 패터닝하여 하부 금속배선(3)을 형성하고, 전체 상부면에 제1금속층간 절연막(4), SOG(Spin-On-Glass)막(5), 제2금속층간 절연막(6) 및 감광막(7)을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막(7)을 패터닝한 상태의 단면도이다.FIG. 1A illustrates the lower metal layer 3 formed on the silicon substrate 1 on which the insulating layer 2 is formed, and then patterned to form the lower metal wiring 3. The first interlayer insulating film 4 and the SOG ( The cross-sectional view of the state which patterned the said photosensitive film 7 using the contact mask after forming a spin-on-glass film 5, the 2nd metal interlayer insulation film 6, and the photosensitive film 7 sequentially is shown.

제1b도는 상기 패터닝된 감광막(7)을 마스크로 이용한 식각 공정으로 상기 제2금속층간 절연막(6)을 소정 깊이 습식 식각하고, 나머지 두께의 상기 제2금속층간 절연막(6), SOG막(5) 및 제1금속층간 절연막(4)을 순차적으로 건식 식각하여 상기 하부 금속배선(3)의 소정 부분이 노출되도록 비아 홀(8)을 형성한 후 상기 감광막(7)을 제거한 상태의 단면도인데, 상기 식각 공정시 반응 부산물로 인해 생성된 폴리머(Polymer; 9)가 상기 비아 홀(8)의 기저부 및 측벽에 잔류된다.FIG. 1B illustrates a wet etching process of the second interlayer insulating film 6 to a predetermined depth by an etching process using the patterned photoresist 7 as a mask, and the second interlayer insulating film 6 and the SOG film 5 having remaining thicknesses. ) And the first interlayer insulating film 4 are sequentially etched to form a via hole 8 so that a predetermined portion of the lower metal wiring 3 is exposed, and then the photosensitive film 7 is removed. Polymer 9 produced by the reaction by-products during the etching process remains on the base and sidewalls of the via hole 8.

제1c도는 상기 폴리머(9)가 제거 공정을 실시한 후 전체 상부면에 금속을 증착하여 상기 하부 금속 배선(3)과 접속되도록 상부 금속층(10)을 형성한 상태의 단면도인데, 이때 완전히 제거되지 않고 잔류되는 상기 폴리머(9)로 인하여 상기 하부 금속 배선(3)과 상부 금속층(9)간의 접속이 불량해진다. 그러므로 금속층간의 접촉 저항이 증가된다. 또한 상기 폴리머(9) 제거 공정시 상기 비아 홀(8)내의 노출된 측벽도 피해를 받는데, 이로 인해 소자의 동작시 누설 전류가 발생된다.FIG. 1C is a cross-sectional view of a state in which the upper metal layer 10 is formed so as to be connected to the lower metal wiring 3 by depositing metal on the entire upper surface after performing the removal process of the polymer 9. The remaining polymer 9 causes poor connection between the lower metal wiring 3 and the upper metal layer 9. Therefore, the contact resistance between the metal layers is increased. In addition, the exposed sidewalls in the via holes 8 are also damaged during the polymer 9 removal process, which results in leakage currents during operation of the device.

따라서 본 발명은 비아 홀을 형성한 후 비아 홀의 측벽이 피해를 받지 않으며, 폴리머가 완전히 제거되도록 세정 공정을 실시하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 다중 금속층 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a multi-metal layer of a semiconductor device capable of solving the above-mentioned disadvantages by performing a cleaning process so that the sidewalls of the via holes are not damaged after the via holes are formed and the polymer is completely removed. have.

상기한 목적을 달성하기 위한 본 발명은 절연층이 형성된 실리콘기판상에 하부 금속배선을 형성하는 단계와, 상기 단계로부터 전체 상부면에 금속층간 절연막 및 감광막을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 금속층간 절연막을 식각하여 상기 하부 금속배선의 소정 부분이 노출되도록 비아 홀을 형성하는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 상기 금속층간 절연막상에 존재하는 감광막 성분을 제거하기 위하여 1차 세정 공정을 실시하는 단계와, 상기 단계로부터 상기 비아 홀내에 존재하는 폴리머를 제거하기 위하여 2차 세정 공정을 실시하는 단계와, 상기 단계로부터 노출된 상기 하부 금속배선상에 잔류하는 금속 산화물을 제거하기 위하여 3차 세정 공정을 실시하는 단계와, 상기 단계로부터 전체 상부면에 금속을 증착하여 상기 하부 금속배선과 접속되도록 상부 금속층을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a lower metal wiring on a silicon substrate with an insulating layer, and sequentially forming a metal interlayer insulating film and a photosensitive film on the entire upper surface from the step by using a contact mask Patterning the photoresist film, and etching the interlayer insulating film by an etching process using the patterned photoresist film as a mask to form a via hole so that a predetermined portion of the lower metal wiring is exposed; Performing a first cleaning process to remove the photoresist component present on the intermetallic insulating film after removing the photoresist film; and performing a second cleaning process to remove polymer present in the via hole from the step. And remaining on the lower metallization exposed from the step Performing a tertiary cleaning process to remove the metal oxide; and forming an upper metal layer to be connected to the lower metal wiring by depositing metal on the entire upper surface from the step.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2a도 내지 제2d도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도로서,2A to 2D are cross-sectional views of devices for describing a method of forming a multi-metal layer of a semiconductor device according to the present invention.

제2a도는 절연층(12)이 형성된 실리콘 기판(11)상에 하부 금속층을 형성한 후 패터닝하여 하부 금속배선(13)을 형성하고, 전체 상부면에 제1금속층간 절연막(14), SOG막(15), 제2금속층간 절연막(16) 및 감광막(17)을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막(17)을 패터닝한 상태의 단면도이다.2A illustrates a lower metal layer 13 formed on the silicon substrate 11 on which the insulating layer 12 is formed, and then patterned to form the lower metal wiring 13, and the first interlayer insulating layer 14 and the SOG film on the entire upper surface thereof. (15) is a cross-sectional view of a state in which the photosensitive film 17 is patterned using a contact mask after the second interlayer insulating film 16 and the photosensitive film 17 are sequentially formed.

제2b도는 상기 패터닝된 감광막(17)을 마스크로 이용한 식각 공정으로 상기 제2금속층간 절연막(16)을 소정 깊이 습식 식각하고, 나머지 두께의 상기 제2금속층간 절연막(16), SOG막(15) 및 제1금속층간 절연막(14)을 순차적으로 건식 식각하여 상기 하부 금속배선(13)의 소정 부분이 노출되도록 비아 홀(18)을 형성한 후 상기 감광막(17)을 제거한 상태의 단면도인데, 상기 식각 공정시 반응 부산물로 인해 생성된 폴리머(19)가 상기 비아 홀(18)의 기저부 및 측벽에 잔류된다.FIG. 2B is a wet etching process of the second interlayer insulating film 16 by a predetermined depth by an etching process using the patterned photoresist film 17 as a mask, and the second interlayer insulating film 16 and the SOG film 15 having remaining thicknesses. ) And the first metal interlayer insulating film 14 are sequentially etched to form a via hole 18 so that a predetermined portion of the lower metal wiring 13 is exposed, and then the photosensitive film 17 is removed. The polymer 19 produced by the reaction by-products during the etching process remains at the base and sidewalls of the via hole 18.

제2c도는 1차 세정 공정을 실시하여 상기 제2금속층간 절연막(16)상에 존재하는 감광막 성분을 제거하고, 2차 세정 공정을 실시하여 상기 비아 홀(18)내에 존재하는 폴리머(19)를 제거한 후 3차 세정 공정을 실시하여 노출된 상기 하부 금속배선(13)상에 잔류하는 금속 산화물을 제거한 상태의 단면도로서, 상기 세정 공정에 의해 상기 비아 홀(18) 측벽이 피해를 받지 않으며, 상기 폴리머(19)가 완전히 제거된다. 여기서 상기 1차 세정 공정은 60 내지 100℃ 온도의 H2SO4및 H2O2가 3 : 1로 혼합된 용액을 사용하여 10 내지 30분동안 실시하며, 상기 2차 세정 공정은 20 내지 30℃ 온도의 ISO 프로필 알콜(Prophyle Alcohol; IPA)을 사용하여 5 내지 15분동안 실시한다. 그리고 상기 3차 세정 공정은 순수(Deionized Water; DI Water)를 사용하여 실시한다.FIG. 2C illustrates a first cleaning process to remove photoresist components present on the second interlayer insulating film 16, and a second cleaning process to remove the polymer 19 present in the via hole 18. A cross-sectional view of a metal oxide remaining on the lower metal wiring 13 exposed by performing a third cleaning process after removal, wherein the sidewalls of the via holes 18 are not damaged by the cleaning process. The polymer 19 is completely removed. Here, the primary cleaning process is carried out for 10 to 30 minutes using a solution of H 2 SO 4 and H 2 O 2 3: 3 at a temperature of 60 to 100 ℃, the secondary cleaning process is 20 to 30 It is carried out for 5 to 15 minutes using ISO propyl alcohol (IPA) at a temperature of ℃. The tertiary washing process is performed using deionized water (DI water).

제2d도는 전체 상부면에 금속을 증착하여 상기 하부 금속 배선(13)과 접속되도록 상부 금속층(20)을 형성한 상태의 단면도이다.FIG. 2D is a cross-sectional view of the upper metal layer 20 formed by depositing metal on the entire upper surface to be connected to the lower metal wiring 13.

상술한 바와 같이 본 발명에 의하면 폴리머 제거를 위한 세정 공증시 비아 홀의 측벽이 피해를 받지 않아 소자의 동작시 누설 전류의 발생이 방지되며, 폴리머의 완전한 제거로 금속층간의 접촉 저항이 감소되어 소자의 전기적 특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the sidewalls of the via holes are not damaged during the cleaning notarization to remove the polymer, thereby preventing the occurrence of leakage current during operation of the device, and the contact resistance between the metal layers is reduced due to the complete removal of the polymer. There is an excellent effect that the electrical properties can be improved.

Claims (5)

반도체 소자의 다중 금속층 형성 방법에 있어서, 절연층이 형성된 실리콘 기판상에 하부 금속배선을 형성하는 단계와, 상기 단계로부터 전체 상부면에 금속층간 절연막 및 감광막을 순차적으로 형성한 후 콘택 마스크를 이용하여 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 금속층간 절연막을 식각하여 상기 하부 금속배선의 소정 부분이 노출되도록 비아 홀을 형성하는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 상기 금속층간 절연막상에 존재하는 감광막 성분을 제거하기 위하여 1차 세정 공정을 실시하는 단계와, 상기 단계로부터 상기 비아 홀내에 존재하는 폴리머를 제거하기 위하여 2차 세정 공정을 실시하는 단계와, 상기 단계로부터 노출된 상기 하부 금속배선상에 잔류하는 금속 산화물을 제거하기 위하여 3차 세정 공정을 실시하는 단계와, 상기 단계로부터 전체 상부면에 금속을 증착하여 상기 하부 금속배선과 접속되도록 상부 금속층을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.In the method for forming a multi-metal layer of a semiconductor device, forming a lower metal wiring on a silicon substrate with an insulating layer, and sequentially forming an intermetallic insulating film and a photosensitive film on the entire upper surface from the step and using a contact mask Patterning the photoresist film, and etching the interlayer insulating film by an etching process using the patterned photoresist film as a mask to form a via hole so that a predetermined portion of the lower metal wiring is exposed; Performing a first cleaning process to remove the photoresist component present on the intermetallic insulating film after removing the photoresist film; and performing a second cleaning process to remove polymer present in the via hole from the step. And on the lower metal wiring exposed from the step Performing a tertiary cleaning process to remove residual metal oxide; and forming an upper metal layer to be connected to the lower metal wiring by depositing metal on the entire upper surface from the step. Of forming multiple metal layers. 제1항에 있어서, 상기 1차 세정 공정은 60 내지 100℃ 온도의 H2SO4및 H2O2가 혼합된 용액을 사용하여 10 내지 30분동안 실시하는 것을 특징으로 하는 반도체 소자의 다중 금속증 형성 방법.The multiple metal of the semiconductor device of claim 1, wherein the first cleaning process is performed for 10 to 30 minutes using a solution in which H 2 SO 4 and H 2 O 2 are mixed at a temperature of 60 to 100 ° C. 3. How to form. 제2항에 있어서, 상기 H2SO4및 H2O2가 3 : 1로 혼합된 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 2, wherein the H 2 SO 4 and H 2 O 2 are mixed at 3: 1. 제1항에 있어서, 상기 2차 세정 공정은 20 내지 30℃ 온도의 ISO 프로필 알콜을 사용하여 5 내지 15분동안 실시하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 1, wherein the secondary cleaning process is performed for 5 to 15 minutes using ISO propyl alcohol at a temperature of 20 to 30 ° C. 3. 제1항에 있어서, 상기 3차 세정 공정은 순수를 사용하여 실시하는 것을 특징으로 하는 반도체 소자의 다중 금속층 형성 방법.The method of claim 1, wherein the tertiary cleaning step is performed using pure water.
KR1019960011721A 1996-04-18 1996-04-18 Method for forming metal wiring in semiconductor device KR100208450B1 (en)

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KR100474856B1 (en) * 2001-12-29 2005-03-08 매그나칩 반도체 유한회사 Method of cleaning in a semiconductor device
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