JPH11186274A - Dual damascene technique - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dual damascene technique which is capable of preventing etching damages and making a change small in critical dimensions. SOLUTION: A first and a second photoresist layer are each previously formed in the prescribed regions of a narrow opening and a wide opening of a dual damascene. A composite layer 37 composed of an HSQ(hydrogen silsesquioxane) layer 34 and an oxide layer 36 provided on the layer 34 is formed surrounding the first and second photoresist layer respectively. After the photoresist layers are removed, the left opening 42 is filled up with an adhesive/barrier layer and a metal layer 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to dual damascene technology, and more particularly, to dual damascene technology for baking a photoresist layer using ultraviolet light. Dual damascene technology can be successfully applied to sub-micron integrated circuit (IC) processes.

[0002]

BACKGROUND OF THE INVENTION As the degree of integration of integrated circuits (ICs) increases, the chip surface for forming interconnects becomes insufficient. In order to meet the requirement that more wiring is required as device size decreases, the structure of multilayer interconnects is required for IC fabrication. The multilayer interconnect is a three-dimensional interconnect structure. To form a multilayer interconnect structure, a first metal interconnect layer, ie, a lower metal interconnect layer, is first formed and connected to source / drain regions of a metal oxide semiconductor transistor (MOS) on a substrate, and then Forming a second metal wiring layer;
To the metal wiring of the metal wiring layer. The metal wiring can be formed from metal or any conductive material such as polysilicon. If necessary, three or more metal wiring layers can be formed.

[0003] However, for IC devices of sub-micron size, conventional dual damascene techniques are not satisfactory. For example, copper, a common material that fills as a plug, is difficult to etch away during the etchback process,
It is also difficult to select an appropriate etchant. Also, if the step coverage during the process of performing metal deposition on plugs, ie, dielectric deposits, between each metal interconnect is low, voids and trapping of impurities are formed. Accordingly, conventional dual damascene techniques have been proposed that overcome the drawbacks associated with miniaturization of IC devices and create a uniform dielectric surface.

Most commonly used dual damascene techniques use chemical mechanical polishing (CMP) during the patterning operation. This chemical mechanical polishing,
For example, the choice of wiring metals, such as aluminum, copper and aluminum alloys, is widened, thus satisfying the requirements of low electrical resistance and low electrical transfer. As a result, chemical mechanical polishing is commonly used for VLSI (very large scale integrated circuit) processes of less than 0.25 μm.

Referring to FIGS. 1-4, a conventional dual damascene technique is illustrated by a process flow diagram.
Referring first to FIG. 1, an intermetal dielectric layer 12, which is an oxide layer, is provided on a substrate. Next, the intermetal dielectric layer 12 is patterned to form a wide opening 14 in the substrate 10.

Referring to FIG. 2, the wide opening 14
The bottom of the substrate is further patterned and etched to form a narrow opening 16 exposing the substrate 10.

Referring to FIG. 3, a metal 18 is filled in the openings 16 and 14.

Referring to FIG. 4, the metal 18 is polished by performing an etch-back technique or a CMP technique to expose the surface of the intermetal dielectric layer 12, thereby causing the surface of the metal 18 to be exposed to the intermetal dielectric. The height is the same as the height of the layer 12.

However, the ordinary dual damascene technique has at least the following problems (1) and (2).

(1) Since both the opening 14 and the opening 16 are etched by dry etching, serious plasma damage occurs.

(2) During the patterning process for forming the narrow opening, the non-uniform topography or topography is caused by the prior art dry etching process for forming the wide opening, so that the critical dimension is reduced. Large fluctuation.

[0012]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a dual damascene technique which overcomes the disadvantages of the conventional dual damascene technique.

It is another object of the present invention to provide a dual damascene technique that is useful for fabricating metal interconnects.

It is yet another object of the present invention to provide a dual damascene technique that is compatible with sub-micron processes.

It is yet another object of the present invention to provide a dual damascene technique that reduces the problem of misalignment and does not cause problems due to the etching process.

[0016]

SUMMARY OF THE INVENTION A method is disclosed for fabricating a landless metal via in a multilayer interconnect.

A photoresist layer (ie, a first photoresist layer and a second photoresist layer) is previously formed in a predetermined region of each of the narrow opening and the wide opening of the dual damascene. Two composite layers consisting of an HSQ layer and an oxide layer thereon are formed around the first and second photoresist layers. After removing these photoresist layers, the remaining openings are filled with an adhesive / barrier layer and metal.

Other objects, features and advantages of the present invention will become apparent from the following description, taken in conjunction with the non-limiting preferred embodiments with reference to the drawings.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
A semiconductor device is first formed on 0. The semiconductor device is formed in an active region insulated by a field structure 21, such as a shallow trench isolation structure.
Metal oxide semiconductor field effect transistor (MOSFE)
T) 22. This MOSFET 22
Includes a source / drain region 24.

Referring to FIG. 6, a photoresist layer 26 having a desired narrow opening pattern is formed in sufficient contact with the source / drain regions 24. Preferably, a deep UV (ultraviolet) firing process is performed. Next, hydrogen silsesquioxax (hydrogen silsesquioxav)
e: HSQ) layer 28 is spin-coated on at least the MOSFET 22.

Referring now to FIG. 7, at least HSQ
Silicon oxide layer 3 on layer 28 and photoresist layer 26
0 is formed. This silicon oxide layer is formed by chemical vapor deposition (CV).
It is preferably formed by D). Next, the silicon oxide layer 30 is polished by CMP to remove a part of the silicon oxide layer 30 at least until the upper surface of the photoresist layer 26 is exposed. As a result, the upper surface of the silicon oxide layer 30 becomes almost the same height as the upper surface of the photoresist layer 26. Therefore, the silicon oxide layer 30 and the HS
A composite layer 31 consisting of the Q layer 28 is formed. The composite layer 31 configured to withstand a continuous process has excellent properties such as a short RC time delay, water resistance, and high density. The superior properties of composite layer 31 result in part from the fact that HSQ layer 28 has a low dielectric constant of about 2.6, which substantially eliminates the RC time delay problem. Also,
The silicon oxide layer 30 formed on the upper side includes a composite layer 31.
This increases the density and water resistance of the HSQ layer, thereby eliminating the problem of the HSQ layer 28 being dense and adsorbing water.

Referring now to FIG. 8, a photoresist layer 32 having a desired wide opening pattern is formed in sufficient contact with the photoresist layer 26. Again, it is preferable to perform a deep UV firing process. Next, a hydrogen silsesquiox (HSQ) layer 34 is spin-coated on at least the silicon oxide layer 30.

Referring now to FIG. 9, at least HSQ
Silicon oxide layer 3 on layer 34 and photoresist layer 32
6 is formed. This silicon oxide layer is preferably formed by CVD. Next, the silicon oxide layer 36 is subjected to CMP.
To remove at least part of the silicon oxide layer 36 until at least the upper surface of the photoresist layer 32 is exposed. As a result, the upper surface of the silicon oxide layer 36 is almost as high as the upper surface of the photoresist layer 32. Accordingly, a composite layer 37 including the silicon oxide layer 36 and the HSQ layer 34 is formed. Like the composite layer 31, the composite layer 37 configured to withstand a continuous process has excellent characteristics such as a short RC time delay, water resistance, and high density. .

Referring to FIG. 10, the photoresist layer 3
2 and photoresist layer 26 are sequentially removed, preferably by an ashing or ashing operation, to form dual damascene openings 42. Also, C
The barrier / adhesive layer 38 is formed by VD so as to cover at least the periphery and the bottom of the opening 42. The composition of the barrier / adhesive layer 38 can be, for example, Ti / TiN. Next, a metal layer 40 is provided to form a barrier /
The adhesive layer 38 is covered and the opening 42 is filled. Metal layer 40
Preferably comprises copper or tungsten. The metal layer 40 is etched back, so that the upper surface of the metal layer 40 is almost as high as the silicon oxide layer 36.

Thus, it is clear that the invention is not limited to two layer metallization or metallization, but is applicable to multilayer interconnects. For example, a three-layer metallization process can be performed by a process similar to the process described above.

In summary, the dual damascene technique of the present invention has the following advantages (1) to (4).

(1) A photoresist layer can be pre-formed in desired areas of the narrow and wide openings to prevent etching damage caused by conventional dual damascene techniques.

(2) Variations in critical dimensions can be reduced by making the surface on which the photoresist layer is formed uniform. Therefore, the present invention is suitable for a deep type submicron process.

(3) The dual damascene technique of the present invention can be applied to multilayer interconnects.

(4) The width of the contact window or via can be kept constant with high reliability regardless of misalignment.

Although the invention has been described by way of example with reference to preferred embodiments, it should be understood that the invention is not limited to such embodiments. Rather,
The invention is intended to cover various modifications and similar structures and procedures, and therefore, the description of the claims is to be accorded the widest scope so as to cover all such modifications and similar structures and procedures. Must be interpreted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one step of a normal process of a dual damascene technique.

FIG. 2 is a cross-sectional view showing one step of a normal process of the dual damascene technique.

FIG. 3 is a cross-sectional view showing one step of a normal process of the dual damascene technique.

FIG. 4 is a cross-sectional view showing one step of a normal process of the dual damascene technique.

FIG. 5 is a cross-sectional view showing one step of a process of a dual damascene technique according to a preferred embodiment of the present invention.

FIG. 6 is a cross-sectional view showing one step of a process of a dual damascene technique according to a preferred embodiment of the present invention.

FIG. 7 is a cross-sectional view showing one step of a process of a dual damascene technique according to a preferred embodiment of the present invention.

FIG. 8 is a cross-sectional view showing one step of a process of a dual damascene technique according to a preferred embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating one step of a process for dual damascene technology according to a preferred embodiment of the present invention.

FIG. 10 is a cross-sectional view showing one step of a process of a dual damascene technique according to a preferred embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20 semiconductor substrate 22 MOSFET 24 source / drain region 26, 32 photoresist layer 28, 34 HSQ layer 30, 36 silicon oxide layer 31, 37 composite layer 38 adhesive / barrier layer 40 metal layer 42 opening

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Chen Jinrai, No. 215, Guang Yuan South Street, Yangmei Town, Taoyuan County, Taiwan

Claims (14)

[Claims] 1. A dual damascene technique, comprising: providing a substrate on which a region desired to be in contact with a wiring is already formed; and forming a first photoresist layer having a first pattern. Contacting the first photoresist layer sufficiently with the region, forming a first insulating layer having a uniform surface, and adjusting the height of the first insulating layer to the first photoresist layer. Forming a second photoresist layer having a second pattern having a cross-sectional area that is sufficiently wider than the cross-sectional area of the first pattern; Bringing a resist layer into sufficient contact with the first photoresist layer; forming a second insulating layer having a uniform surface, wherein the second insulating layer has a height substantially equal to the height of the second photoresist layer; Making the same, and the first Forming the opening by removing the photoresist layer and the second photoresist layer, and filling the opening with a metal. 2. The dual damascene technique according to claim 1, further comprising a step of performing deep ultraviolet (UV) baking after the step of forming the first photoresist layer.・ Damask technology. 3. The dual damascene technique according to claim 1, further comprising a step of performing deep UV baking after the step of forming the second photoresist layer. . 4. The dual damascene technique according to claim 1, wherein the first insulating layer is formed of hydrogen silsesquioxane.
A dual damascene technique characterized by comprising a quixave (HSQ) layer and a silicon oxide layer formed on the HSQ layer. 5. The dual damascene technique according to claim 1, wherein said second insulating layer comprises an HSQ layer and said HSQ layer.
And a silicon oxide layer formed on the Q layer. 6. The dual damascene technique of claim 1, wherein the step of filling the metal comprises applying an adhesive / adhesive.
A dual damascene technique wherein a barrier layer is formed to cover the periphery and bottom of the opening. 7. The dual damascene technique according to claim 1, wherein the area desirably in contact with the wiring is one of a source / drain area. 8. The dual damascene technique according to claim 4, wherein the HSQ layer is formed by spin coating. 9. The dual damascene technique according to claim 5, wherein the HSQ layer is formed by spin coating. 10. The dual damascene technique of claim 4, wherein the silicon oxide layer is formed by chemical vapor deposition (CV).
D) and dual damascene technology characterized by being formed by chemical mechanical polishing (CMP). 11. The dual damascene technique of claim 5, wherein said silicon oxide layer is formed by CVD and CMP.
Dual damascene technology characterized by being formed by. 12. The dual damascene technique according to claim 6, wherein said adhesive / barrier layer is a Ti / TiN layer. 13. The dual damascene technique according to claim 1, wherein said metal is made of copper. 14. The dual damascene technique according to claim 1, wherein said metal is made of tungsten.