JPH11111843A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can enhance performance and reliability of a wiring layer having a copper layer, and a method for manufacturing the device. SOLUTION: Grooves 11 are made in an inter-layer insulating film 10 above a semiconductor substrate 1, copper layers 13 embedded in the grooves 11 form part of wiring layer, cap barrier films 15 as silicon nitride films are formed on the associated copper layers 13, and barrier films 12 made of metal are formed only on side and bottom surfaces of the copper layers 13 or only on the side surfaces thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit device capable of improving the performance and reliability of a wiring layer having a copper (Cu) layer. The present invention relates to the manufacturing method.

[0002]

2. Description of the Related Art The present inventors have studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a wiring layer in a semiconductor integrated circuit device, a wiring metal layer such as an aluminum layer is formed on an interlayer insulating film by a sputtering method, and then the wiring metal layer is formed by a photolithography process. A photoresist film pattern having the same shape as the wiring pattern is formed on the photoresist film disposed thereon, and the wiring pattern is formed by a dry etching process using the photoresist film as a mask.

In this case, LSI (Large Scale Integrat)
In order to solve the problems of wiring delay and migration resistance due to the miniaturization of ed circuits, it has been studied to adopt a wiring layer in which a groove is formed in the interlayer insulating film and a copper layer is embedded in the groove. I have.

[0005] Incidentally, as a document describing a technology for forming a wiring layer in a semiconductor integrated circuit device, for example, “Ninety-Sixth Latest Semiconductor Process Technology” published on November 2, 1989 by Press Journal, p. p273
Some are described in

[0006]

However, in the above-described method for manufacturing a wiring layer in a semiconductor integrated circuit device,
When a wiring layer in which a groove is formed in an interlayer insulating film and a copper layer is buried in the groove is employed, when a single-layer copper layer is used, an electric field is applied to a silicon oxide film as an interlayer insulating film. , Copper ions drift at high speed, and TDDB (Time D
ependence on Dielectric Breakdown, or time-dependent dielectric breakdown).

Therefore, a barrier film made of a barrier material such as TiN, Ta, W, or WN is formed on the bottom and sides of the groove formed in the interlayer insulating film to prevent TDDB from occurring. However, even if the wiring layer is made of a copper layer having the above-described barrier film, the TDD
It has become clear that the occurrence of B cannot be prevented. That is, the structure has no barrier film above the groove.

An object of the present invention is to provide a semiconductor integrated circuit device capable of improving the performance and reliability of a wiring layer having a copper layer and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor integrated circuit device according to the present invention has a wiring layer in which a groove is formed in an insulating film such as an interlayer insulating film on a substrate such as a semiconductor substrate, and a copper layer embedded in the groove is provided. Is formed, and a cap barrier film made of a silicon nitride film is formed on the surface of the copper layer,
A barrier film made of an insulating film or a metal film is formed only on the side and bottom or on the side of the copper layer.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, after a groove is formed in an insulating film such as an interlayer insulating film on a substrate such as a semiconductor substrate, only the side and bottom or side of the groove are formed. A step of forming a barrier film made of an insulating film or a metal film and, after depositing a copper layer on the substrate, using a CMP method to remove an unnecessary copper layer and remove the copper layer embedded in the trench. Forming a wiring layer and forming a recess for the cap barrier film, and on the substrate,
After depositing a cap barrier film made of a silicon nitride film, removing unnecessary cap barrier films other than the cap barrier film deposited on the surface of the copper layer embedded in the trench.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

FIGS. 1 to 12 are schematic sectional views showing steps of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. The feature of the method of manufacturing a semiconductor integrated circuit device of the present embodiment is a method of manufacturing a wiring layer made of a copper layer embedded in a trench, and other methods of manufacturing a semiconductor integrated circuit device adopt various aspects. Can be applied. The semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 1, a p-type semiconductor substrate (substrate) 1 made of, for example, single crystal silicon is prepared.
Various techniques, such as the prior art, are used to form MOSFETs.

That is, a selective region on the surface of a p-type semiconductor substrate 1 made of, for example, single crystal silicon is thermally oxidized to form a field insulating film for element isolation made of a silicon oxide film having a LOCOS (Local Oxidation of Silicon) structure. Form 2

Next, after a gate insulating film 3 made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 1, a gate electrode 4 made of a conductive polycrystalline silicon film is deposited. Thereafter, an insulating film 5 made of a silicon oxide film or the like is formed on the gate electrode 4, and a pattern such as the gate electrode 4 is formed by using a photolithography technique and a selective etching technique. A side wall spacer 6 made of a silicon oxide film or the like is formed on the side wall.

Thereafter, an n-type impurity such as phosphorus is ion-implanted into the semiconductor substrate 1 and diffused to form an n-type semiconductor region 7 serving as a source and a drain of the MOSFET. Next, an insulating film 8 is formed on the semiconductor substrate 1.
The insulating film 8 is formed, for example, by forming a silicon oxide film by CVD (Chemical
After being formed by the Vapor Deposition method, the surface is polished and the surface thereof is flattened to form a flattened insulating film 8. In the planarization process, the surface of the insulating film 8 is subjected to, for example, an etch-back method or a CMP (Chemical Mecha).
An embodiment in which the surface is flattened by a method such as nical polishing or chemical mechanical polishing can be employed. Thereafter, a through hole (connection hole) is formed in a selective region of the insulating film 8 using a photolithography technique and a selective etching technique, and then a conductive material such as conductive polycrystalline silicon or tungsten is filled in the through hole. The plug 9 is buried to form a plug 9 in the through hole.

Next, after a first-layer interlayer insulating film (insulating film) 10 is formed on the semiconductor substrate 1, a trench 11 for wiring is formed therein (FIG. 2). That is, for example, a silicon oxide film is formed on the semiconductor substrate 1 as the interlayer insulating film 10 by CV.
After the formation using the method D, the groove 11 is formed in a portion where the wiring layer is to be disposed by using a photolithography technique and a selective etching technique such as dry etching.

In this case, the first interlayer insulating film 10 has a small dielectric constant in order to reduce the capacitance of the wiring layer formed in the trench 11 and the wiring layer in which the interlayer insulating film 10 is interposed. Silicon oxide film (insulating film with a dielectric constant of about 4.2)
Alternatively, a coating insulating film (an insulating film having a dielectric constant of about 4 or less) such as an inorganic SOG (Spin On Glass) film is used. Therefore, use of an insulating film having a high dielectric constant such as a silicon nitride film (an insulating film having a dielectric constant of about 8) is avoided.

The depth of the groove 11 is, for example, 500-1.
000 nm, and in the present embodiment, 500 nm.

Thereafter, a barrier film (silicon nitride barrier film) 1 made of a silicon nitride film having a thickness of, for example, 50 nm is formed on the semiconductor substrate 1 by sputtering.
2 (FIG. 3).

In this case, the barrier film 12 made of a silicon nitride film prolongs the TDDB life of the interlayer insulating film 10 that is in contact with a wiring layer having a copper layer described later, and improves the copper diffusion resistance. Used as a membrane for The barrier film 12 made of a silicon nitride film is used as a film for improving the adhesion between a wiring layer having a copper layer described later and the interlayer insulating film 10.

Therefore, when a silicon nitride film is applied as the barrier film 12, an interlayer in contact with a wiring layer having a copper layer described later is compared with a barrier film made of a metal layer used in the prior art. The TDDB life of the insulating film 10 can be extended, and the copper diffusion resistance can be improved.

Next, an operation of removing the barrier film 12 made of a silicon nitride film on the plug 9 is performed by using a photolithography technique and a selective etching technique (FIG. 4).

Thereafter, a copper layer 13 is deposited on the semiconductor substrate 1 with a thickness of, for example, 800 nm by using a sputtering method to bury the copper layer 13 in the groove 11 (FIG. 5). In this case, the copper layer 13 as a wiring layer is
When completely depositing the copper layer 13,
The film thickness (for example, 800 nm) is larger than the depth of the groove 11 (for example, 500 nm).

Next, the surface of the copper layer 13 is polished from the surface of the copper layer 13 using a CMP method using a CMP apparatus to remove the copper layer 13 other than the copper layer 13 embedded in the groove 11. Perform the work (FIG. 6). In this case, the surface of the copper layer 13 buried in the trench 11 is flush with the surface of the interlayer insulating film 10, and the barrier film 12 made of the silicon nitride film on the interlayer insulating film 10 is removed.

Then, after performing the above-mentioned operation of removing the unnecessary copper layer 13, overetching is performed using a CMP apparatus, and a recess (recess, recess) is formed in the surface portion of the copper layer 13 buried in the groove 11. The recess 14 is formed with a depth of, for example, 50 nm (FIG. 7). In this case, as a result of the study by the present inventor, by adopting a mode such as using a soft material for the CMP polishing pad in the CMP apparatus, the groove 1 is formed.
A recess 14 having a rectangular cross-sectional shape can be formed in the surface layer portion of the copper layer 13 buried in 1.

Next, the copper layer 13 buried in the trench 11
Then, hydrogen annealing (heat treatment in a hydrogen atmosphere) is performed to reduce the surface layer portion of the copper layer 13 oxidized by the CMP process or the like, and to smooth fine irregularities formed on the surface of the copper layer 13. An operation for flattening is performed (FIG. 8).

Thereafter, a cap barrier film (silicon nitride cap barrier film) 15 made of a silicon nitride film having a thickness of, for example, 50 nm is formed on the semiconductor substrate 1 by a sputtering method (FIG. 9).

In this case, the cap barrier film 15 made of a silicon nitride film extends the TDDB life of the interlayer insulating film 10 that is in contact with the copper layer 13 as a wiring layer, and improves copper diffusion resistance. Used as a membrane.

Therefore, since the silicon nitride film is applied as the cap barrier film 15 for capping the copper layer 13 as the wiring layer, the interlayer insulating film 10 and the second interlayer insulating film formed thereon are formed. For example, when the material is different from a material such as a silicon oxide film, the selectivity in the selective etching technique (for example, the selective etching technique used when forming a through hole) can be increased, and the copper layer 13 as a wiring layer can be formed. Can be protected.

Next, a cap barrier film 15 made of a silicon nitride film capping the copper layer 13 as a wiring layer.
Barrier film 15 made of a silicon nitride film other than
Work. In this case, as described below,
As a method for removing the unnecessary cap barrier film 15 made of a silicon nitride film, a method using a photolithography technique and a selective etching technique or a method using a CMP method can be applied.

First, a cap barrier film 15 made of a silicon nitride film capping the copper layer 13 as a wiring layer
Barrier film 15 made of a silicon nitride film other than
Is described using a photolithography technique and a selective etching technique.

That is, as shown in FIG. 10, a photoresist film patterned by photolithography on a cap barrier film 15 made of a silicon nitride film on a copper layer 13 as a wiring layer. After the formation of the cap film 16, a cap barrier made of a silicon nitride film deposited on the interlayer insulating film 10 is formed by using the photoresist film 16 as an etching mask and using a selective etching technique such as dry etching. An operation of removing the film 15 (unnecessary cap barrier film 15) is performed.

Thereafter, the unnecessary photoresist film 1
6 is removed using a resist peeling device such as an ashing device (FIG. 11). In this case, since the surface of the copper layer 13 as a wiring layer is capped by the cap barrier film 15 made of a silicon nitride film, the copper layer 13 is not exposed in an oxygen atmosphere such as in an ashing process. In the case of processing or the like, oxidation of the copper layer 13 can be prevented, and as a result, the performance and reliability of the copper layer 13 as a wiring layer can be prevented from being reduced.

Next, a cap barrier film 15 made of a silicon nitride film capping the copper layer 13 as a wiring layer.
Barrier film 15 made of a silicon nitride film other than
Will be described using a CMP method.

That is, as shown in FIG. 12, the surface of a cap barrier film 15 made of a silicon nitride film on a copper layer 13 as a wiring layer is subjected to a CMP using a CMP apparatus.
The surface is polished using a method to remove the cap barrier film (unnecessary cap barrier film) 15 made of the silicon nitride film deposited on the interlayer insulating film 10.

In this case, the cap barrier film 15 made of the silicon nitride film on the surface of the copper layer 13 as the wiring layer is embedded in the recess 14 so that the silicon nitride film on the surface of the copper layer 13 as the wiring layer is formed. Without removing the cap barrier film 15 made of, only the cap barrier film (unnecessary cap barrier film) 15 made of the silicon nitride film deposited on the interlayer insulating film 10 can be removed.

After that, according to the design specifications, the above-described manufacturing method of forming the first interlayer insulating film 10 and the copper layer 13 as the first wiring layer is applied, After depositing the second interlayer insulating film, a groove for forming a second wiring layer is formed in a selective area thereof, and a copper layer as a second wiring layer is formed in the groove. . After the above-described manufacturing process is repeatedly used to form a multilayer wiring layer as necessary, a passivation film (not shown) is formed, and the manufacturing process of the semiconductor integrated circuit device of the present embodiment is completed. .

According to the semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, the interlayer insulating film (insulating film)
Copper layer 13 as a wiring layer is formed in groove 11 formed in
By embedding the wiring layer,
By forming the copper layer 13 as a wiring layer without using a conventional wiring layer pattern manufacturing process of forming a wiring layer pattern using a photolithography technique and a selective etching technique, Even if the wiring layer structure has a very small layer width and a short distance between adjacent wiring layers, the wiring layer can be manufactured with high dimensional accuracy by fine processing.

Therefore, it is possible to miniaturize a semiconductor integrated circuit device such as an LSI. In addition, since the wiring layer is made of the copper layer 13 buried in the groove 11, problems of wiring delay and migration resistance can be solved.

According to the semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment, the trench 11 formed in the interlayer insulating film (insulating film) 10 is formed from the silicon nitride film on the surface of the copper layer 13 as a wiring layer. Since the barrier film 12 made of a silicon nitride film is formed on the side and bottom (side and bottom) of the copper layer 13, an interlayer insulating film to which an electric field is applied is formed. In the (for example, silicon oxide film) 10, the problem that copper ions drift at high speed and TDDB is generated can be prevented. That is, since the TDDB life can be extended and the copper diffusion resistance can be improved, a wiring layer composed of the copper layer 13 having high performance and high reliability can be obtained.

In this case, a through hole is formed at the bottom of the copper layer 13, and when the plug 9 is electrically connected to the bottom of the copper layer 13, a side portion excluding the bottom of the copper layer 13 is formed. Only the barrier film 12 made of a silicon nitride film needs to be provided. Further, as the barrier film 12 formed only on the side and bottom or on the side of the copper layer 13, an insulating film in which silicon in the silicon nitride film is partially oxidized can be used in addition to the silicon nitride film. In addition, copper layer 1
3 and barrier film 12 formed only on the bottom or side
A metal film such as a refractory metal film (such as a titanium film, a tungsten film or a tantalum film) or a TiN (titanium nitride) film can be used.

According to the semiconductor integrated circuit device of this embodiment and the method of manufacturing the same, the cap barrier film 15 made of a silicon nitride film is formed only on the surface of the copper layer 13 as the wiring layer.
Is formed, the capacitance can be reduced even when a silicon nitride film having a large capacitance is used as the cap barrier film 15.

Since the surface of the copper layer 13 as a wiring layer is covered with a cap barrier film 15 made of a silicon nitride film, a silicon nitride film as the cap barrier film 15 and a silicon oxide film as the interlayer insulating film 10 are formed. Since the selectivity in the selective etching with the film can be increased, when the silicon nitride film as the cap barrier film 15 or the silicon oxide film as the interlayer insulating film 10 is patterned using the selective etching technique, In addition, it is possible to accurately perform the etching and prevent unnecessary etching. Also, in various manufacturing processes such as selective etching thereof, since the surface of the copper layer 13 as a wiring layer is covered with the cap barrier film 15 made of a silicon nitride film, the copper layer 13 as a wiring layer is formed. Can be prevented, so that the performance and reliability of the copper layer 13 as the wiring layer can be prevented from being reduced.

Further, by covering the surface of the copper layer 13 as a wiring layer with the cap barrier film 15 made of a silicon nitride film, an interlayer insulating film is formed on the copper layer 13 as a wiring layer. When a through hole is formed in an interlayer insulating film by using a selective etching technique, since the cap barrier film 15 made of a silicon nitride film has a function as a stopper, the copper layer 1 as a wiring layer is formed.
3 can protect the copper layer 1 as a wiring layer.
3 can be prevented from being reduced in performance and reliability.

Furthermore, when the unnecessary photoresist film 16 is removed by using a resist peeling device such as an ashing device, the surface of the copper layer 13 as a wiring layer is formed by a cap barrier film 15 made of a silicon nitride film. Since the copper layer 13 is not exposed to an oxygen atmosphere such as in an ashing process, the copper layer 13 can be prevented from being oxidized in an ashing process or the like. It is possible to prevent the performance and reliability as the wiring layer from being reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, according to the present invention, a semiconductor substrate on which a semiconductor element is formed can be changed to an SOI (Siliconon Insulator) substrate.
And a semiconductor integrated circuit device in which various semiconductor elements such as bipolar transistors are combined, and a method of manufacturing the same.

Further, the present invention relates to a MOSFET, a CMO
Logic system or DR with SFET etc. as components
AM (Dynamic Random Access Memory), SRAM (St
The present invention can be applied to various semiconductor integrated circuit devices having a memory system such as an aticRandom Access Memory) and a method of manufacturing the same.

[0052]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, photolithography is achieved by forming a copper layer as a wiring layer in a groove formed in an interlayer insulating film (insulating film). Forming the wiring layer pattern using the technology and the selective etching technology Without using the conventional wiring layer pattern manufacturing process, by forming the copper layer as the wiring layer, the wiring layer width and Even if the wiring layer structure has an extremely small distance between adjacent wiring layers, the wiring layer can be manufactured with high dimensional accuracy by fine processing.

Therefore, it is possible to miniaturize a semiconductor integrated circuit device such as an LSI. In addition, since the wiring layer is made of a copper layer embedded in the trench, problems of wiring delay and migration resistance can be solved.

(2). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, a cap barrier film made of a silicon nitride film is formed on a surface of a copper layer as a wiring layer in a groove formed in an interlayer insulating film (insulating film). In addition, since a barrier film made of a silicon nitride film is formed only on the side and bottom or on the side of the copper layer, high-speed copper ions can be generated in an interlayer insulating film (for example, a silicon oxide film) to which an electric field is applied. And the problem that TDDB is generated can be prevented. That is, since the TDDB life can be extended and the copper diffusion resistance can be improved, a wiring layer composed of the copper layer 13 having high performance and high reliability can be obtained.

(3). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, since the cap barrier film made of the silicon nitride film is formed only on the surface of the copper layer as the wiring layer, the silicon nitride film having a large capacitance can be capped. Even when used as a barrier film, the capacity can be reduced.

Since the surface of the copper layer as the wiring layer is covered with the cap barrier film made of the silicon nitride film, the silicon nitride film as the cap barrier film and the silicon oxide film as the interlayer insulating film (insulating film) are formed. Since the selectivity in the selective etching with the film can be increased, when the silicon nitride film as the cap barrier film or the silicon oxide film as the interlayer insulating film is patterned by using the selective etching technique, the patterning is performed. Accurate and unnecessary etching can be prevented.
In addition, during various manufacturing processes such as selective etching thereof, by covering the surface of the copper layer as a wiring layer with a cap barrier film made of a silicon nitride film,
Since the copper layer as the wiring layer can be protected, the performance and reliability of the copper layer as the wiring layer can be prevented from being reduced.

Further, by covering the surface of the copper layer as a wiring layer with a cap barrier film made of a silicon nitride film, an interlayer insulating film is formed on the copper layer as a wiring layer. When a through hole is formed by using a selective etching technique, the cap barrier film made of the silicon nitride film has a function as a stopper, so that the copper layer as the wiring layer can be protected. The performance and reliability of the copper layer as the wiring layer can be prevented from being reduced.

Further, when the unnecessary photoresist film is removed by using a resist peeling device such as an ashing device, the surface of the copper layer as a wiring layer is capped with a cap barrier film made of a silicon nitride film. By doing so, the copper layer is not exposed in an oxygen atmosphere such as in an ashing process, so that oxidation of the copper layer can be prevented in the case of an ashing process, and as a result, the performance of the copper layer as a wiring layer and It is possible to prevent the reliability from being reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a schematic sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 11 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 12 is a schematic cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate (substrate) 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall spacer 7 semiconductor region 8 insulating film 9 plug 10 interlayer insulating film (insulating film) 11 groove 12 barrier film 13 copper layer 14 recess 15 Cap barrier film 16 Photoresist film

Claims (9)

[Claims] A groove is formed in an insulating film on a substrate,
A wiring layer including a copper layer embedded in the trench is formed, and a cap barrier film made of a silicon nitride film is formed on a surface of the copper layer, and a side portion and a bottom portion of the copper layer are formed. A semiconductor integrated circuit device, wherein a barrier film is formed only on a side portion. 2. The semiconductor integrated circuit device according to claim 1, wherein a cap barrier film made of a silicon nitride film formed on a surface of each of the copper layers is formed of a cap barrier film of another adjacent copper layer. A semiconductor integrated circuit device, which is not in contact with a cap barrier film made of a silicon nitride film formed on a surface. 3. The semiconductor integrated circuit device according to claim 1, wherein an insulating film or a metal film is used as the barrier film formed only on the side and bottom or on the side of the copper layer. A semiconductor integrated circuit device. 4. A step of forming a groove in an insulating film on a substrate; a step of forming a barrier film made of an insulating film or a metal film only on a side portion and a bottom portion or a side portion of the groove; Forming a wiring layer composed of the copper layer embedded in the trench while removing the unnecessary copper layer using a CMP method after depositing a copper layer; After depositing a cap barrier film made of a silicon nitride film, removing the unnecessary cap barrier film other than the cap barrier film deposited on the surface of the copper layer embedded in the trench. A method for manufacturing a semiconductor integrated circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein a surface layer portion of said copper layer is removed after a step of forming a wiring layer made of said copper layer embedded in said trench. Forming a recess on the surface of the copper layer. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein a surface portion of said copper layer is removed to form a recess in a surface of said copper layer, wherein a CMP method is used. A method of manufacturing a semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein said cap barrier film is deposited on a surface of said copper layer embedded in said groove. A method for manufacturing a semiconductor integrated circuit device, wherein a photolithography technique and a selective etching technique are used when removing unnecessary cap barrier films other than the above. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said cap barrier film is deposited on a surface of said copper layer embedded in said groove. A method for manufacturing a semiconductor integrated circuit device, wherein a CMP method is used when removing the unnecessary cap barrier film other than the above. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the barrier film formed only on the side and bottom or on the side of the copper layer is silicon nitride. A method for manufacturing a semiconductor integrated circuit device, comprising using a film.